JPH06140636A - Quantum fine line transistor and manufacture thereof - Google Patents

Abstract

PURPOSE:To evenly arrange gate electrodes relative to each quantum fine line by disposing gates relative to quantum fine wires, made of a semiconductor without a surface depletion layer, with a space between them. CONSTITUTION:Each external end of a source region 117, a drain region 118 and a gate region 113 is electrically connected to a double-layer semiconductor layer 16 at least at each region. A source electrode 17S, a drain electrode 18D and a gate electrode 13G, each serving as a terminal lead, are alloyed deep to reach the double-layer semiconductor layer 16 on each region. Thereby, two-channel type quantum fine wire 11, that is, two quantum fine wires 11 are formed between the source and the drain, whereby a quantum fine line transistor which is electrically parallel can be constituted. Hence, sufficient control can be effected by an electric field that is caused by the application of a voltage to the gates 13 arranged on definite locations via a space 12.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a quantum wire transistor and its manufacturing method.

[0002]

2. Description of the Related Art Recently, application of quantum wires, which are expected to have high electron mobility, to transistors has been drawing attention.

The width of the quantum wire is, for example, d-10.
It is a mechanism that electrons are confined two-dimensionally at about nm.
The remaining one-dimensional conduction is less affected by scattering, and high mobility is expected.

This is because the same state of electron energy is
The wave vectors are only | k> and | -k>, and k
This is because scattering from the transition to -k is unlikely to occur, and there is almost only forward scattering.

Therefore, if such a quantum wire is applied to a transistor, a transistor having a good mutual conductance Gm can be constructed.

However, in practice, in this quantum wire,
Since a sufficient amount of current cannot be handled, a plurality of quantum wires 1 are arranged in parallel between a source (emitter) S and a drain (collector) D as shown in the perspective view of FIG. Proposals have been made for adopting the configured configuration.

In this case, the current between the source and the drain is controlled by arranging the gate electrode G on the plurality of quantum wires 1 so as to extend across the insulating layer and controlling the voltage applied thereto. Done.

By the way, as described above, a plurality of quantum wires 1
When all the quantum wires are arranged in parallel, the shapes, dimensions, and characteristics of all the quantum wires must match. However, when the quantum wires 1 are arranged side by side in a plane as described above, the occupied area increases as the number increases. As a result of the increase in size, this causes more problems in homogenization.

Further, there is a problem that the electric field applied to each quantum wire 1 by the gate electrode is made uniform.

In order to solve the problem of the occupied area and the like, a plurality of quantum wires 1 may be laminated with an insulating layer 2 interposed therebetween, as shown in FIG.

However, in this case, a problem arises in that the gate electrodes are evenly arranged for each quantum wire 1.

[0012]

SUMMARY OF THE INVENTION The present invention relates to a single-channel type quantum wire transistor using a single quantum wire, as well as to a transistor having a multi-channel structure in which a plurality of quantum wires are provided in parallel. , Especially the formation of the gate part can be simplified,
The present invention relates to a quantum wire transistor capable of uniformly arranging a gate electrode for each quantum wire even when the quantum wires are stacked and the manufacturing method thereof.

[0013]

According to the first aspect of the present invention, a semiconductor having no surface depletion layer is shown in FIG. 1 which is an enlarged perspective view of an example thereof, and FIG. 2 is an enlarged sectional view of a quantum wire portion thereof. For example, a quantum wire 11 made of InAs is provided with a gate 13 via a space 12.

Similarly, as shown in FIGS. 1 and 2, in the second invention, quantum wires 11 each made of a semiconductor having no surface depletion layer are stacked via a barrier layer 14 for electrons, and each quantum wire 11 is formed. A gate 13 made of the same semiconductor layer as each quantum wire 11 is arranged to face the wire 11 with a space.

A third aspect of the present invention, as shown in the perspective view of FIG. 3, has a semiconductor layer 16 having no surface depletion layer on a substrate 15.
And a barrier layer 14 for electrons are laminated to form a laminated semiconductor layer. On the other hand, as shown in a perspective view of FIG. 4, a source region portion 117, a drain region portion 118,
A quantum wire portion 111 extending between the source region portion 117 and the drain region portion 118, and the quantum wire portion 1
11 and the gate portion 113 which is separated by a required distance are left at the same time to perform patterning at the same time to form a target quantum wire transistor.

[0016]

In the present invention, at least the depletion layer is formed in the quantum wire 11 at the interface with a semiconductor having no surface depletion layer, that is, a space (for example, vacuum), as shown in the conduction band model diagram of FIG. By forming the semiconductor that is not formed, for example, InAs, the interface between the quantum wire 11 and the space 12, that is, the quantum wire 1
Since, so to speak, a channel is formed on the surface of No. 1, it can be controlled by an electric field by applying a voltage to the gate 13 opposed to this channel through the space 12 having a required gap.

Therefore, when a plurality of quantum wires 11 are laminated, the gates 13 may be formed on the end faces of the quantum wires 11 with the same semiconductor layers as the semiconductor layers of the quantum wires 11. As described in the manufacturing method of the present invention, the pattern of the quantum wire portion 111 in which a plurality of quantum wire 11 are stacked and the gates forming each gate 13 can be obtained. It is possible to adopt a procedure of patterning the portion 113 and the portion 113 at the same time, and the gate 13 can be uniformly formed for a plurality of quantum wires 11 by the manufacturing method of the present invention.

[0018]

EXAMPLE An example of the quantum wire transistor according to the present invention will be described together with an example of the manufacturing method of the present invention. In this example, two quantum wires are electrically formed in parallel.

First, as shown in FIG. 3, for example, GaAs
A substrate 15 made of a single crystal is prepared.

Then, the barrier layer 1 is formed on the substrate 15.
4. A semiconductor layer 16 having no surface depletion layer, a similar barrier layer 14, and a semiconductor layer 16 having no surface depletion layer are successively epitaxially grown to form a laminated semiconductor layer.

The upper and lower semiconductor layers 16 have no surface depletion layer, that is, an n-type semiconductor layer 16 which does not have a depletion layer at the interface with the vacuum or the space corresponding thereto.
It can be made of nAs, and the thickness thereof is, for example, about 10 nm, which is thin enough to form a quantum wire.

On the other hand, the barrier layer 14 is well lattice-matched with the substrate 15 and the semiconductor layer 16, and can form a barrier against electrons with respect to the semiconductor layer 16, that is, the quantum wire 11 to be finally formed. The relationship between the barrier layer 14 and the semiconductor layer 16 is shown in FIG.
As shown in the band model diagram of 1., the conduction band of the barrier layer 14 is higher than the conduction band of the semiconductor layer 16, and the valence band of the barrier layer 14 is the conduction band of the semiconductor layer 16. It is composed of a semiconductor material that constitutes a lower type heterojunction. As such a barrier layer 14, for example, Al having a thickness of about 50 nm is used.
It is composed of GaSb.

Then, for the laminated semiconductor layer in which the semiconductor layer 16 having no surface depletion layer and the barrier layer 14 for electrons are laminated in this way, finally obtain as shown by a chain line in FIG. A source region portion to be taken, a drain region portion, a quantum thin line portion extending between the source region portion and the drain region portion, and a photoresist or the like on the gate portion at a required distance from the quantum thin line portion. The etching mask M is formed.

The masks M are formed by, for example, coating the entire surface of a photoresist, exposing by electronic drawing, and developing.

Thereafter, the laminated semiconductor layer not covered with the mask M is selectively etched to a depth that traverses at least the entire thickness of the entire semiconductor layer 16, as shown in FIG. 117 and the drain region 11
8 and these source region part 117 and drain region part 1
18 and a pair of gate portions 113 are formed on both sides of the quantum thin wire portion 111 with the quantum thin wire portion 111 interposed between the quantum thin wire portion 111 and the quantum thin wire portion 111 at a required distance, for example, 10 nm.

The etching in this case is performed by vertical anisotropic etching such as RIE (reactive ion etching) so that the pattern after etching has the same size and shape with respect to the upper and lower semiconductor layers 16. .

Thus, in the source region 117 and the drain region 118, each semiconductor layer 16 is formed.
The two-layer source region 17 and the drain region 18 are formed by
8 and the quantum wire portion 111 is formed in the same manner as the quantum wire portion 111, and two layers of the quantum wire 11 are formed by the respective semiconductor layers 16. A two-layer gate 13 is formed by each semiconductor layer 16 of the pair of gate portions 113 while maintaining a space 12 of 10 nm between the end face and a required distance.

Then, as shown in FIG. 1, each source region 117, drain region 118, and gate 113.
For example, the source electrode 17S, the drain electrode 18D, and the gate electrode 13 that electrically connect at least the two semiconductor layers 16 in each part to each terminal and lead to each terminal
G and G are formed by alloying to a depth across the two semiconductor layers 16 in each part.

In this way, a two-channel type quantum wire 11, that is, two quantum wires 11 are laminated between the source and the drain to form a quantum wire transistor electrically formed in parallel.

According to the quantum wire transistor having this structure, the quantum wire 11 is composed of the semiconductor layer 16 having no surface depletion layer so that a channel is formed on the surface thereof, that is, near the interface with the space 12. ,
The control for this can be sufficiently controlled by the electric field due to the voltage application to the gate 13 arranged through the space 12.

By making such a structure possible, the gate 13 is formed for each quantum wire 11 so that the semiconductor layer 1 forming the quantum wire 11 is formed.
6 to form the quantum wire 11 (quantum wire portion 1
11)) and the gate portion 113 is formed at the same time, that is, by patterning, the positional relationship between each quantum wire 11 and each corresponding gate 13 is as follows.
The predetermined positional relationship is surely faced, and the predetermined interval is also accurately set.

In the above example, the substrate 15 is made of Ga.
As for the case of using an As substrate, when it is composed of AlGaSb which itself can form a barrier, the lower semiconductor layer 16 can be directly epitaxially grown on it.

Further, in the above-mentioned example, a two-channel type quantum thin line transistor is constructed, and therefore, although two semiconductor layers 16 are used, it is applicable to a quantum thin line transistor having three or more channels. Alternatively, in this case, three or more semiconductor layers 16 may be stacked with the barrier layer 14 interposed therebetween.

The space 12 between the quantum wire 11 and the gate 13 is filled with a vacuum or an inert gas which is substantially equivalent to this, filled with SiO ₂ , or AlG.
It is also possible to fill aSb, and at the same time, it is also possible to form AlGaSb so as to cover the quantum wire portion 111 and the like.

Further, in the illustrated example, one quantum wire transistor is formed on the substrate 15, but a plurality of quantum wire transistors or a plurality of quantum wire transistors or a plurality of quantum wire transistors may be formed on the common substrate 15 after forming a plurality of quantum wire transistors at the same time. It is also possible to adopt a configuration in which the quantum wires of are arranged side by side.

Further, in the above example, the gate portions 113 are arranged on both sides of the quantum wire portion 111, but it is possible to arrange only one of them, or the gate portions 113 on both sides.
It is also possible to make various changes without being limited to the above-mentioned example or the illustrated example, such as a structure in which the outside ends of the source region portion or the drain region portion are connected to each other.

[0037]

According to the quantum wire transistor of the present invention, the quantum wire 11 is constituted by the semiconductor layer 16 having no surface depletion layer, and a channel is formed on the surface thereof, that is, near the interface with the space 12. Because I did
The control for this can be sufficiently controlled by the electric field due to the voltage application to the gate 13 arranged through the space 12.

Therefore, according to the present invention, the formation of the gate 13 for each quantum wire 11 is performed by the same semiconductor layer as the semiconductor layer 16 forming the quantum wire 11, and the formation of the quantum wire 11 (of the quantum wire portion 111). At the same time, the gate portion 113 can be formed, that is, can be formed by patterning, so that the positional relationship between the quantum wires 11 and the corresponding gates 13 can be surely made to face a predetermined positional relationship. Moreover, since the interval can be accurately set, the yield can be increased and the multi-channel quantum wire transistor can be efficiently manufactured.

Since the plurality of quantum wires 11 connected in parallel to each other are arranged vertically, each quantum wire 11 is
There are many advantages such as avoiding inconveniences such as variations in characteristics between the channels and therefore current concentration on some channels.

[Brief description of drawings]

FIG. 1 is a schematic perspective view of an example of a quantum wire transistor according to the present invention.

FIG. 2 is a schematic cross-sectional view of a main part of an example of a quantum wire transistor according to the present invention.

FIG. 3 is a process drawing of an example of a method of manufacturing a quantum wire transistor according to the present invention.

FIG. 4 is a process drawing of an example of a method of manufacturing a quantum wire transistor according to the present invention.

FIG. 5 is an energy band model diagram for explaining the present invention.

FIG. 6 is a model diagram of a conduction band of an energy band used for explaining the present invention.

FIG. 7 is a perspective view of a conventional quantum wire transistor.

FIG. 8 is a perspective view of a conventional quantum wire transistor.

[Explanation of symbols]

 11 quantum thin wire 111 quantum thin wire portion 12 space 13 gate 113 gate portion 16 semiconductor layer 14 barrier layer

Claims (3)

[Claims] 1. A quantum wire transistor comprising a quantum wire made of a semiconductor having no surface depletion layer and a gate provided through a space. 2. A quantum wire made of a semiconductor having no surface depletion layer is laminated via a barrier layer for electrons, and a gate made of the same semiconductor layer as each quantum wire faces each quantum wire with a space. A quantum wire transistor, characterized in that each is arranged. 3. A laminated semiconductor layer in which a semiconductor layer having no surface depletion layer and a barrier layer for electrons are laminated on a substrate, and a source region portion and a drain region portion are formed on the laminated semiconductor layer. A quantum wire transistor which is characterized by simultaneously patterning a quantum wire part extending between the source region part and the drain region part and a gate part separated from the quantum wire part by a required distance. Manufacturing method.