JPH06139180A - Interface circuit - Google Patents

Abstract

PURPOSE:To easily set up channel sequence, frequency and priority, to reduce the interposition of a CPU during the period of the setting operation and to reduce the load of the CPU by preparing an operation sequence list block to be set up from the CPU. CONSTITUTION:The CPU 1 previously writes channel sequence, describing all the operation sequence of input channels in the sequence list block 7. The channel sequence wirtten in a sequence list of the block 7 is sequentially read out by a control part 2a and all conversion is executed in accordance with the channel sequence without using the CPU 1. Since the CPU 1 is used only for the writing of the channel sequence for setting up the conversion sequence to be executed prior to converting operation and a preparation step such as mode setting utilizing a control register which is executed before the conversion, the load of the CPU 1 can be reduced as compared with a convensional method.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an interface between a CPU and peripheral I / O functional blocks in a microcontroller, and more particularly to an interface circuit used for A / D converter and serial communication.

[0002]

2. Description of the Related Art As an example of this type of interface circuit, FIG. 6 shows an A / D converter section in a conventional microcontroller and its peripheral functional block configuration. The operation will be described with reference to the processing flow relating to the CPU in FIG.

First, in steps 201 and 202,
The CPU 1 sets an operation mode and conversion channel in a control register (not shown) included in the control unit 2b. Usually, simple operation modes such as single-channel conversion in which conversion is performed a fixed number of times for one channel and multi-channel scan conversion in which conversion is performed only once for all channels are used as operation modes. Next, in step 203, when the conversion start command is sent from the CPU 1 to the control unit 2b, the control unit 2b switches the multiplexer 5 and converts the conversion result register 3b.
Perform address selection and start conversion.

The signal from the selected input channel 4 is
It is supplied to the A / D converter 6 through the multiplexer 5, is A / D converted, and then stored in the conversion result register 3b. When the A / D conversion for one channel is completed by the A / D converter 6, a completion signal is sent to the control unit 2b, and the control unit 2b receiving the completion signal sends the address of the conversion result register 3b to store the next conversion result. Is set, and when there is a channel change such as multi-channel scan conversion, the multiplexer 5 is switched and the next conversion is executed. By repeating the above, all conversions according to the set operation mode are performed.

When all the conversions corresponding to the operation mode are completed, the control section 2b asserts the completion flag. CPU1
Monitors the completion flag at a predetermined timing (steps 204 and 205), detects completion by the completion flag (step 205), and reads the conversion result from the A / D conversion result register 3b (step 206). Is to do.

Generally, the conversion frequency and the priority of each channel related to the conversion data required by the related system are not the simple ones that can be handled by the above-mentioned simple operation mode, and the desired conversion data are required. A complex transformation sequence is often required to obtain the data. Therefore, in practice, a predetermined number of conversions (2
01-207) and data processing (step 208) for selecting conversion data. Therefore, CP
Since U1 must intervene each time, CPU1
There was a problem that it put a heavy burden on him. Also, the actual procedure had to be programmed in advance, which put a load on the programmer. The polling operation in serial communication is similar.

[0007]

As described above, the conventional A /
When the A / D conversion of a plurality of input channels is performed by the D converter, the conversion sequence of the plurality of channels must be set by the CPU each time, and the intervention of the CPU is required for each conversion of a series. It was Further, when it is necessary to set the conversion frequency and the priority for the plurality of channels, the program must be used to set the operation mode and the channel each time. As a result, C
The burden on the PU has become quite heavy.

The present invention has been made in consideration of the above circumstances, and an object thereof is to set a channel sequence, a frequency, and a priority in the operation of a plurality of channels of a peripheral I / O function block. An object of the present invention is to provide an interface circuit which can facilitate the operation and reduce the intervention of the CPU during its operation and reduce the load on the CPU.

[0009]

The essence of the present invention is to provide an operation sequence list block that can be set by the CPU in order to easily set the channel sequence, the frequency and the priority and reduce the intervention of the CPU. Especially.

That is, according to the present invention, the interface circuit connecting the CPU and the peripheral I / O functional block is provided with means for storing a plurality of operation channel numbers of the peripheral I / O functional block and the execution order thereof. Is characterized by.

[0011]

In the present invention, the operation sequence list that can be set by the CPU is provided in the interface between the CPU and the peripheral I / O function block. Then, the CPU sets the channel and polling execution sequence in the operation of the I / O function block in this sequence list, so that the I / O function block independently executes each possible operation according to the set sequence. Therefore, in the operation of the peripheral I / O function block after the setting of the sequence list, it is not necessary to intervene the CPU for each operation, and the operation time can be shortened and the load on the CPU can be drastically reduced.

[0012]

The details of the present invention will be described below with reference to the illustrated embodiments.

FIG. 1 is a block diagram showing an interface circuit according to an embodiment of the present invention. Although the basic configuration is the same as that of FIG. 6, a sequence list block 7, which is a feature of this embodiment, is additionally provided. The important point is that the sequence list block 7 has CPU 1
Is to write a channel sequence describing the entire operation sequence of the input channel. The channel sequence written in the sequence list 11 (see FIG. 4) of the sequence list block 7 is read by the sequential control unit 2a, and all conversions according to the channel sequence are performed without intervention of the CPU. .

First, the sequence list block used in this embodiment will be described with reference to FIGS. FIG. 3 is an example of a sequence list used in this embodiment. The A / D conversion sequence in this example is as follows. Channel 1 → Channel 3 → Channel 1 → Channel 5 → Channel 1 → ……… → Channel n

By checking the sequence end code of the next code of channel n, the control unit 2a judges the end of the sequence, and returns to the beginning of the list again. Incidentally, the operation mode may be introduced, for example, when the operation mode is the single mode, the conversion is ended, and in the continuous mode, the conversion may be continued from the beginning of the sequence list again. This sequence list can be set in a variable manner according to the application and the number of channels, and by using the above sequence end code, it is not always necessary to use the entire list.

FIG. 4 is a block diagram of the sequence list block and control unit 2a used in this embodiment. First, C
The PU1 writes data to the sequence list 11. The setting unit 12, which has received the address to be written, sets the value in the counter 13, and the counter 13 sets the address to be written in the sequence list 11. The data indicating the channel number is stored from the data bus from the set address.

When the conversion is started, the counter 13 is incremented each time the completion signal is received, and the sequence list 11 moves to the next address. The setting section 12 simultaneously determines the sequence end each time, and when detecting the sequence end code, presets the counter 13 and resets the address. The control unit 2a controls the entire conversion.

Next, by using the interface of the present embodiment, the A / D converter 6 is used for A of a plurality of input channels 4.
The operation when performing the D / D conversion will be described with reference to the schematic configuration diagram of FIG. 1 and the process flow of the CPU of FIG. First, in step 101, the CPU 1 sets the conversion sequence of the plurality of channels for the sequence list block 7 of the interface as shown in FIG. 3, and in step 102, the control unit 2a.
Mode setting is performed. Next, step 102.
At, the CPU 1 issues an instruction to start the conversion sequence to the control unit 2a. Here, what is different from the conventional one is that there is no intervention for each conversion of the CPU 1 thereafter.

By the instruction to start the conversion sequence,
The control unit 2a reads the data indicating the channel number at the top address of the channel sequence written in the sequence list 11 of the sequence list block 7, switches the multiplexer 5 and selects the address of the conversion result register 3a, Start conversion. After the conversion by the A / D converter 6 is completed, the conversion result is stored in the address of the A / D conversion result register 3a corresponding to the channel number, and the completion signal is sent to the control unit 2a. Upon receiving the completion signal, the control unit 2a reads the data indicating the channel number in the next channel sequence written in the sequence list 11 of the sequence list block 7,
Thereafter, in the same manner, according to the channel sequence set in the sequence list 11 of the sequence list block 7, C
The conversion is performed without going through PU1.

As described above, the CPU 1 intervenes between the writing of the channel sequence for setting the conversion sequence performed before the conversion operation and the control register (not shown).
Confirmation of conversion completion for each series of conversions, operation mode and channel setting, which is only required at the preparatory stage before conversion such as mode setting using Also, the processing of selecting data after all conversion is unnecessary, and the load on the CPU 1 can be reduced. This can be understood more clearly by comparing FIGS. 2 and 7.

Further, the conversion result data is constructed such that the latest data is always stored in the corresponding address of the conversion result register 3a, and can be read by the CPU 1 as needed or collectively after conversion. (Step 104).

It should be noted that instead of transmitting a channel sequence from the CPU 1 to the sequence list block 11 during conversion, a plurality of channel sequences are transmitted in advance,
The ID number of the channel sequence used at the time of conversion may be transmitted.

Next, another embodiment of the present invention will be described with reference to FIG. FIG. 5 shows an embodiment in which the present invention is applied to a polling operation of serial communication used in a microcontroller.

The polling operation is an operation when serial communication is performed with a plurality of slaves 30, and a control signal is sequentially sent from the master 20 to the slaves, and the slaves receiving the control signals respond whether or not there is communication data. If there is communication data, communication is executed between the master 20 and its slave, and if there is no communication data, the function moves to the next slave.

In this embodiment, the sequence for the plurality of slaves 30 is written in the sequence list block 7 in the master 20, and the control unit 8 of the master 20 starts and executes the serial communication according to the sequence.
As a result, the access frequency to each slave and the priority of each slave can be set, and as a result, it becomes possible to perform a selective polling operation in consideration of functional conditions and situations.
Further, it is possible to reduce the load on the CPU 1. It should be noted that the present invention is not limited to the above-described embodiments, and various modifications can be carried out without departing from the scope of the invention.

[0026]

As described above, according to the present invention, the conversion sequence setting of a plurality of input channels in the A / D converter and the polling sequence setting in the serial communication, which have not been performed in the prior art, are executed using the interface. By doing so, it is possible to reduce the time required by the CPU, which has been conventionally required, to reduce the overall operation time and to significantly reduce the load on the CPU.

[Brief description of drawings]

FIG. 1 is a block diagram of peripheral functional blocks according to an embodiment of the present invention.

FIG. 2 is a diagram showing a processing flow relating to a CPU in A / D conversion of the embodiment.

FIG. 3 is a schematic configuration diagram of a sequence list according to the embodiment.

FIG. 4 is a schematic configuration diagram of a sequence list block according to the embodiment.

FIG. 5 is a block diagram of peripheral functions in serial communication according to another embodiment.

FIG. 6 is a block diagram of a conventional peripheral function block.

FIG. 7 is a diagram showing a processing flow relating to a CPU in a conventional A / D conversion.

[Explanation of symbols]

1 ... CPU, 2a, 2b ... Control unit, 3a, 3b ... Conversion result register, 4 ... Input channel, 5 ... Multiplexer,
6 ... A / D converter, 7 ... Sequence list block, 8 ... Serial communication control section, 11 ... Sequence list, 12 ... Setting section, 13 ... Counter, 20 ... Master,
30 ... slave.

Claims (1)

[Claims] 1. An interface circuit for connecting between a CPU and a peripheral function block, a storage unit for storing an operation execution order of the peripheral function block, and a predetermined operation according to the execution order stored in the storage unit. An interface circuit comprising: a control unit that executes the following.