JPS58137050A - Processing method of request signal - Google Patents
Processing method of request signalInfo
- Publication number
- JPS58137050A JPS58137050A JP1945582A JP1945582A JPS58137050A JP S58137050 A JPS58137050 A JP S58137050A JP 1945582 A JP1945582 A JP 1945582A JP 1945582 A JP1945582 A JP 1945582A JP S58137050 A JPS58137050 A JP S58137050A
- Authority
- JP
- Japan
- Prior art keywords
- request
- memory
- request signal
- processing
- signal
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/46—Multiprogramming arrangements
- G06F9/48—Program initiating; Program switching, e.g. by interrupt
- G06F9/4806—Task transfer initiation or dispatching
- G06F9/4812—Task transfer initiation or dispatching by interrupt, e.g. masked
Abstract
Description
【発明の詳細な説明】
本発明は、１スキヤンで全ての要求信号を処理できる要
求信号の処理方法に関する０
一般に、コンピュータ等で複数の要求信号の中から希望
の要求信号を捜し出す場合、該当する信号が入力するま
で同一内容の操作を繰り返し行わせるようＫなっている
ものが多い。このような方式では、該当信号が入力する
までは他の仕事を行わせることができない。また、デン
ジ１ンテーブル方式のコンビ、−夕等においては、１回
のスキャンで同一プログラムの繰り返し操作はでき彦く
、類偏動作を行わせるにしても時間を要する。このよう
に、複数の要求信号の中から希望の要求信号のみを検出
しようとすると時間がかかる。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a request signal processing method that can process all request signals in one scan.In general, this is applicable when a computer or the like searches for a desired request signal from among a plurality of request signals. Many devices are designed so that the same operation is repeated until a signal is input. In such a system, other work cannot be performed until the corresponding signal is input. Furthermore, in digital single table system combinations, etc., it is not possible to repeat the same program in one scan, and it takes time to perform similar operations. In this way, it takes time to detect only a desired request signal from among a plurality of request signals.
本発明は、このような点に鑑みてなされたもので、同一
内容の処理を行う複数の要求信号については、要求受付
時に予め全ての要求信号を取込んでおき次の要求受付時
までの間に取込んだ要求を一定の順序で処理するように
して１スキヤンで全ての要求信号を処゛理する方法を実
現したものである。以下、図面を参照して本発明の詳細
な説明する。The present invention has been made in view of the above points, and in order to deal with multiple request signals that perform processing of the same content, all request signals are captured in advance at the time of receiving a request, and the processing is performed until the next request is received. This method realizes a method of processing all request signals in one scan by processing requests taken in in a fixed order. Hereinafter, the present invention will be described in detail with reference to the drawings.
第１図は本発明を説明するためのタイミングチャートで
ある。図において、Ｐｌはサンプリング要求信号、Ｐ２
は要求受付信号、ｐ５は処理シーケンスを示す図である
。Ｐ、のパルスには、予め定められた番号が付されてい
る。更に、サンプリング要求信号Ｐ、の各々の内容は全
て同様の処理内容をもっているものとする。時刻ｔ１に
おいて要求受付信号Ｐ２を発生させるＯｌｌにおいて、
図に示すような５゜２、１０．７からなるサンプリング
要求信号のパルストレインがこの順序で内蔵のメモリに
記憶されていたものとする。５．２．１０．７の履で入
力された各要求信号は、処理されるときにはＰ３に示す
ように２、５．７．１０の順に並べ換えて処理が実行さ
れる〇ここでは、たまたｔ２．５．７．１０の順に処理
を行ったが、この処理の順序は予め如何ようにでも決め
ておくことがで龜る。また、この処、現時間は２〜１０
の何れもほぼ一定である＠
次に、時刻ｔ２において要求受付信号が発生し、この時
点でサンプリング要求信号が１５． Ｓ、 １２．８゜
５の願に入力しメモリに記憶されていた。これら取込ま
れたサンプリング要求信号は、Ｌ ５ｔ ”１１２、１
５の順で処理が実行される。以下、同様の７−ケンスが
繰返されるのであるが、要求受付時刻ｔ５． ｔ４のよ
うに要求信号が１個しか発生しなかりたときは、即処理
が実行されることになる。上述したように１本発明では
特定の要求信号を受付けるため仕事を中断して待ってい
る状態が生じない。FIG. 1 is a timing chart for explaining the present invention. In the figure, Pl is a sampling request signal, P2
is a request acceptance signal, and p5 is a diagram showing a processing sequence. A predetermined number is attached to the pulse P. Furthermore, it is assumed that the contents of each sampling request signal P have the same processing contents. In the Oll that generates the request acceptance signal P2 at time t1,
Assume that the pulse train of the sampling request signal consisting of 5°2 and 10.7 as shown in the figure is stored in the built-in memory in this order. When each request signal input in step 5.2.10.7 is processed, it is rearranged in the order of 2 and 5.7.10 as shown in P3. Although the processing was performed in the order of .5.7.10, it is difficult to decide the order of the processing in any way beforehand. Also, the current time here is 2-10
Both are almost constant @Next, a request acceptance signal is generated at time t2, and at this point the sampling request signal reaches 15. S, 12.8゜5 request was entered and stored in memory. These captured sampling request signals are L 5t ”112, 1
The processes are executed in the order of 5. Thereafter, the same 7-en sequence is repeated, but at the request reception time t5. When only one request signal is generated as at t4, immediate processing is executed. As described above, according to the present invention, there is no need to interrupt work and wait in order to receive a specific request signal.
従って１１スキヤンで全ての処理を行うことができる。Therefore, all processing can be performed with 11 scans.
第２図は、本発明を実施するための制御システムの一構
成を示す電気的接続図である。図において、ｓｗｌ乃至
８Ｗ、はそれぞれ６接点をもつ接点入力スイッチ部であ
る。２１乃至２ｓは、それぞれスイクテ部ＳＷ１〜ＳＷ
、からの接点入力を受ける入力回路である・２４は、こ
れら入力回路の出力を受けるＣＰＵである。１ｍ ＣＰ
Ｕとしては、例えばマイクロコンビ纂−夕が用いられる
。ａｉｌＫ示す回路において、接点入力スイッチ部ＳＷ
、〜’ＢＷ！Ｉからサンプリング要求信号が入力する。FIG. 2 is an electrical connection diagram showing one configuration of a control system for implementing the present invention. In the figure, swl to 8W are contact input switch sections each having six contacts. 21 to 2s are the switch parts SW1 to SW, respectively.
, and 24 is a CPU that receives outputs from these input circuits. 1m CP
As U, for example, a micro combination assembly is used. In the circuit shown in ailK, the contact input switch section SW
,~'BW! A sampling request signal is input from I.
入力し是要求信号は、それぞれのグループの入力回路内
に設けられたメモリ内に記憶される。入力回路１に内蔵
のメモリをメモリ１、入力回路２に内蔵のそれをメモリ
２、入力回路５のそれをメ七り３とする。ＣＰＵ２４は
、ある時間ごとく要求受付信号を出力し各接点入力部か
らのサンプリング要求信号を受付ける。このため、・メ
モリ１〜メモリ３にデータが格納されているかどうかを
チェックする。データが格納されていた場合、これらデ
ータをＣＰＨに内蔵のバッファメモリに移し必要な処理
を行う。以下、同様の操作を繰り返す。なお、グループ
ごとの接点数は６接点に限る必要はなく、またグループ
数も３つである必要はない。The input request signal is stored in a memory provided within the input circuit of each group. The built-in memory of the input circuit 1 is referred to as memory 1, the built-in memory of the input circuit 2 is referred to as memory 2, and that of the input circuit 5 is referred to as memory 3. The CPU 24 outputs a request acceptance signal at certain time intervals and accepts sampling request signals from each contact input section. Therefore, it is checked whether data is stored in memory 1 to memory 3. If data is stored, these data are transferred to the buffer memory built into the CPH and necessary processing is performed. Thereafter, repeat the same operation. Note that the number of contacts per group does not need to be limited to six, and the number of groups does not need to be three.
第３図は、本発明の動作シーケンスを示す７０−テヤー
トである。図より明らかなように、帰還ループは皆無で
あシ１スギャンで全ての処理が終了することを示してい
る。FIG. 3 is a 70-tayat showing the operating sequence of the present invention. As is clear from the figure, there is no feedback loop and all processing is completed without any system gyan.
以上、詳細に説明したように、本発明によれば同一内容
の処理を行う複数の要求信号について、要求受付時に予
め全ての要求信号を取込んでおき次の要求受付時までの
間に取込んだ要求を一定の順序で処理するよう圧して１
スキヤンで全ての要求信号を処理する方法を実現するこ
とができる。As explained in detail above, according to the present invention, regarding multiple request signals that perform processing of the same content, all request signals are captured in advance at the time of receiving a request, and are captured until the time of receiving the next request. 1 by forcing requests to be processed in a certain order.
It is possible to implement a method of processing all request signals by scanning.
第１図は本発明を説明するためのタイミングチャート、
第２図は本発明を実施するための制御システムの一構成
を示す電気的接続図、第３図は本発明の動作シーケンス
を示す７０−チャートである。
２１〜２５・・・入力回路、ＳＷ、〜ＳＷ５・・・接点
入力スイッチ部、２４・・・ＣＰＵ 。FIG. 1 is a timing chart for explaining the present invention,
FIG. 2 is an electrical connection diagram showing one configuration of a control system for carrying out the present invention, and FIG. 3 is a 70-chart showing the operation sequence of the present invention. 21-25...Input circuit, SW, ~SW5...Contact input switch section, 24...CPU.
Claims (1)
おいて、 （イ）ある期間ごとに発生する複数の要求信号を記憶し
ておくメモリをもち、 （ロ） 要求信号を受付けるための要求受付信号をある
期間ごとに入力し、 （ハ）要求受付信号発生時において前記メモ９に記憶さ
れていた要求を、ある定まり′九順序に従って処理する よ５Ｋしたことを特徴とする請求信号の処理方法Ｏ[Scope of Claims] In the case of processing a plurality of request signals having similar processing contents, (a) having a memory for storing a plurality of request signals generated in each certain period; (b) request signals; (c) requests stored in the memo 9 at the time the request acceptance signal was generated are processed according to a certain prescribed order. Processing method of request signal O
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1945582A JPS58137050A (en) | 1982-02-09 | 1982-02-09 | Processing method of request signal |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1945582A JPS58137050A (en) | 1982-02-09 | 1982-02-09 | Processing method of request signal |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS58137050A true JPS58137050A (en) | 1983-08-15 |
Family
ID=11999788
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1945582A Pending JPS58137050A (en) | 1982-02-09 | 1982-02-09 | Processing method of request signal |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS58137050A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS64142U (en) * | 1987-06-16 | 1989-01-05 | ||
| DE19753488B4 (en) * | 1996-12-06 | 2007-01-18 | Aisin Aw Co., Ltd. | Internal toothed part and method and apparatus for its shaping |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS4999245A (en) * | 1973-01-26 | 1974-09-19 | ||
| JPS5289437A (en) * | 1976-01-21 | 1977-07-27 | Hitachi Ltd | Priority order control system |
-
1982
- 1982-02-09 JP JP1945582A patent/JPS58137050A/en active Pending
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS4999245A (en) * | 1973-01-26 | 1974-09-19 | ||
| JPS5289437A (en) * | 1976-01-21 | 1977-07-27 | Hitachi Ltd | Priority order control system |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS64142U (en) * | 1987-06-16 | 1989-01-05 | ||
| JPH0517709Y2 (en) * | 1987-06-16 | 1993-05-12 | ||
| DE19753488B4 (en) * | 1996-12-06 | 2007-01-18 | Aisin Aw Co., Ltd. | Internal toothed part and method and apparatus for its shaping |
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