JPH0613429A - Bonding method for outer lead using photo-curing resin - Google Patents

Bonding method for outer lead using photo-curing resin

Info

Publication number
JPH0613429A
JPH0613429A JP16808392A JP16808392A JPH0613429A JP H0613429 A JPH0613429 A JP H0613429A JP 16808392 A JP16808392 A JP 16808392A JP 16808392 A JP16808392 A JP 16808392A JP H0613429 A JPH0613429 A JP H0613429A
Authority
JP
Japan
Prior art keywords
outer lead
photo
package
wiring pattern
bonding
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP16808392A
Other languages
Japanese (ja)
Inventor
Kyotaro Nakamura
京太郎 中村
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sharp Corp
Original Assignee
Sharp Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sharp Corp filed Critical Sharp Corp
Priority to JP16808392A priority Critical patent/JPH0613429A/en
Publication of JPH0613429A publication Critical patent/JPH0613429A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00Apparatus or processes for manufacturing printed circuits
    • H05K3/30Assembling printed circuits with electric components, e.g. with resistor
    • H05K3/32Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
    • H05K3/325Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by abutting or pinching, i.e. without alloying process; mechanical auxiliary parts therefor
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00Apparatus or processes for manufacturing printed circuits
    • H05K3/30Assembling printed circuits with electric components, e.g. with resistor
    • H05K3/32Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
    • H05K3/328Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by welding

Landscapes

  • Electric Connection Of Electric Components To Printed Circuits (AREA)
  • Wire Bonding (AREA)

Abstract

PURPOSE:To make it possible to join an outer lead without generating a heat effect on an LSI or some other parts, and take off a package from a board in a necessary repairing step, by using a frame-shaped polyethylene-telephthalate sheet coated with a photo-curing resin, and by swelling a resin with a solvent in the repairing step. CONSTITUTION:After an LSI-chip package 1 is mounted on a board 3, which has a wiring pattern 4 for an electric circuit, an outer-lead leg 2 of the package 1 is aligned with the wiring pattern 4. A frame-shaped polyethylene-telephthalate sheet 6 that is coated with an photo-curing resin 5 is so placed that the coated side thereof is put in contact with the outer-lead leg 2. Then, while the polyethylene-telephthalate sheet 6 is pressed downward by the bonding tool 7, an ultraviolet ray is cast through the bonding tool 7 so that the photo-curing resin 5 is hardened in shrinking, and thereby the outer-lead leg 2 and the wiring pattern 4 are joined electrically.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【従来の技術】従来、電子機器に使用するICまたはL
SIパッケージを電子回路パターンを配したプリント基
板若しくはフレキシブル基板に装着するアウターリード
ボンディング法としては、ハンダ付け法が最も広く用い
られている。この方法の1つとして例えばプリント基板
の配線パターン上にハンダスクリーン印刷でハンダペー
ストを供給した後、LSIチップを搭載し、リフロー炉
で加熱して接合し、その後洗浄して処理を完了するリフ
ローボンディング法がある。また、他の1つとしてプリ
ント基板の配線パターン上に電解メッキ或いはスーパー
メッキでハンダメッキし、LSIチップを搭載してLS
Iチップのアウターリード脚を配線パターンに位置決め
した後、ボンディングツールで加圧、加熱して接合し、
その後洗浄して処理を完了するツールボンディング法が
ある。
2. Description of the Related Art Conventionally, ICs or Ls used in electronic equipment
The soldering method is most widely used as the outer lead bonding method for mounting the SI package on the printed circuit board or the flexible circuit board on which the electronic circuit pattern is arranged. As one of the methods, for example, reflow bonding in which a solder paste is supplied on a wiring pattern of a printed circuit board by solder screen printing, an LSI chip is mounted on the printed circuit board, heated and joined in a reflow furnace, and then washed to complete the process. There is a law. Also, as another one, solder plating is performed by electrolytic plating or super plating on the wiring pattern of the printed circuit board, the LSI chip is mounted, and the LS is mounted.
After positioning the outer lead legs of the I-chip on the wiring pattern, press and heat with a bonding tool to join,
After that, there is a tool bonding method of cleaning and completing the process.

【0002】その他の実装方法としては、配線パターン
を配したプリント基板上の異方性導電膜を載置し、該異
方性導電膜上にLSIチップを位置決めしながら搭載し
た後、ボンディングツールで加圧、加熱して接合し処理
を完了する異方性導電膜による方法がある。この異方性
導電膜は、絶縁性の接着剤中に繊維状導電体を混入して
おり、加圧、加熱により反応してLSIチップのアウタ
ーリード脚とプリント基板の配線パターン間のみが導通
するものである。
As another mounting method, an anisotropic conductive film is placed on a printed circuit board on which a wiring pattern is arranged, and an LSI chip is positioned and mounted on the anisotropic conductive film, and then a bonding tool is used. There is a method of using an anisotropic conductive film to complete the treatment by bonding under pressure and heating. This anisotropic conductive film has a fibrous conductor mixed in an insulative adhesive, and reacts with pressure and heat to conduct only between the outer lead leg of the LSI chip and the wiring pattern of the printed circuit board. It is a thing.

【0003】[0003]

【発明が解決しようとする課題】上記従来のハンダ付け
法の欠点としては、先ずリフローボンディング法の場
合、スクリーン印刷のためファインピッチ化が困難であ
ること、またテープキャリアパッケージのアウターリー
ド脚のフォーミング形状の制御を厳しくする必要があ
る。また、ツールボンディング法の場合、ハンダメッキ
法に工夫が必要であり、例えば電解メッキではメッキリ
ードの引き廻し、無電解メッキのときはスーパーソルダ
ー等特別な方法が必要である。尚、フラックス塗布工程
も必要である。
The disadvantages of the above-mentioned conventional soldering method are that, in the case of the reflow bonding method, it is difficult to form a fine pitch due to screen printing, and the forming of the outer lead leg of the tape carrier package is difficult. The shape needs to be tightly controlled. Further, in the case of the tool bonding method, it is necessary to devise a solder plating method. For example, in electroplating, a special method such as arranging plating leads, and in the case of electroless plating, a super solder is required. A flux applying step is also required.

【0004】また、上記ハンダ付け法自体の問題として
ボンディング後にフラックスを洗浄除去しなければなら
ず、この工程ではフロンによる洗浄が主流で、フロン全
廃の動向から早急な対応が望まれている。
Further, as a problem of the soldering method itself, the flux must be removed by washing after bonding. In this process, washing with chlorofluorocarbon is the mainstream, and there is a demand for an immediate response from the trend of complete elimination of chlorofluorocarbon.

【0005】上記異方性導電膜による方法では、不透明
な異方性導電膜をプリント基板に載置すること、またボ
ンディングツールで該異方性導電膜越しに加圧しなけれ
ばならないことにより、パターンの位置合わせが困難で
ある等の課題があった。
In the method using the anisotropic conductive film, a pattern is formed by placing an opaque anisotropic conductive film on a printed board and pressing the anisotropic conductive film with a bonding tool. There was a problem that it was difficult to align the positions.

【0006】[0006]

【課題を解決するための手段】本発明の光硬化性樹脂を
用いたアウターリードボンディング法は、上記の課題を
解決するため、電気回路の配線パターンを配した基板上
にLSIチップのパッケージを搭載して該配線パターン
に該パッケージのアウターリード脚を位置合わせし、該
LSIチップのアウターリード脚に対応する枠状の、光
硬化性樹脂を塗布したポリエチレンテレフタレート・シ
ートを、該光硬化性樹脂側をアウターリード脚に接する
如く載置し、該ポリエチレンテレフタレート・シート上
からボンディングツールによって加圧し、該ボンディン
グツールを介して紫外光を照射して上記光硬化性樹脂を
収縮硬化せしめ、上記アウターリード脚と配線パターン
とを電気的に接続せしめる、ことを特徴とするものであ
る。
In order to solve the above problems, the outer lead bonding method using a photo-curable resin of the present invention mounts an LSI chip package on a substrate on which a wiring pattern of an electric circuit is arranged. Then, the outer lead legs of the package are aligned with the wiring pattern, and a frame-shaped polyethylene terephthalate sheet coated with a photocurable resin corresponding to the outer lead legs of the LSI chip is attached to the photocurable resin side. On the polyethylene terephthalate sheet by pressing with a bonding tool, and irradiating ultraviolet light through the bonding tool to shrink and cure the photocurable resin. And the wiring pattern are electrically connected to each other.

【0007】[0007]

【作用】本発明のアウターリードボンディング法は、L
SIチップのアウターリード脚と基板の配線パターンと
を直視して位置合わせすることができ、またボンディン
グに熱処理を行なわないのでプリント基板に寸法変化を
生じない。
The outer lead bonding method of the present invention is
The outer lead leg of the SI chip and the wiring pattern of the substrate can be directly aligned and aligned with each other, and since heat treatment is not performed for bonding, no dimensional change occurs in the printed circuit board.

【0008】[0008]

【実施例】以下、本発明のアウターリードボンディング
法を図面と共に説明すると、図1はプリント基板上にL
SIチップのパッケージを搭載しボンディング処理する
際の分解斜視図であり、図2は本発明のアウターリード
ボンディング法の工程図であり、図3は本発明のアウタ
ーリードボンディング法の原理図である。
DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The outer lead bonding method of the present invention will be described below with reference to the drawings.
FIG. 3 is an exploded perspective view when mounting an SI chip package and performing a bonding process, FIG. 2 is a process diagram of an outer lead bonding method of the present invention, and FIG. 3 is a principle diagram of the outer lead bonding method of the present invention.

【0009】先ず、図1に示すICまたはLSIチップ
の矩形状パッケージ1は、各辺から複数本のアウターリ
ード脚2,2・・・が所要長さで設けられている。該パ
ッケージ1のリード脚2,2・・・に対応してプリント
基板若しくはフレキシブル基板等の基板3に、配線パタ
ーン4,4・・・を被着形成する。
First, the rectangular package 1 of the IC or LSI chip shown in FIG. 1 is provided with a plurality of outer lead legs 2, 2 ... The wiring patterns 4, 4 ... Are adhered and formed on a substrate 3 such as a printed circuit board or a flexible substrate corresponding to the lead legs 2, 2 of the package 1.

【0010】次に上記パッケージ1のアウターリード脚
2,2・・・に対応する枠状の光硬化性樹脂5を塗布し
たポリエチレンテレフタレート・シート6を設ける。該
シート6の外形寸法は縦方向及び横方向ともに上記パッ
ケージ1の対向する辺からのびたアウターリード脚2,
2の先端から先端までの長さ乃至は少し大き目の長さで
あり、また切込んだ内形寸法は、パッケージ1の縦方向
及び横方向の長さと同等で該パッケージ1に挿入できる
ものとする。
Next, a polyethylene terephthalate sheet 6 coated with a frame-shaped photocurable resin 5 corresponding to the outer lead legs 2, 2, ... Of the package 1 is provided. The outer dimensions of the sheet 6 are the outer lead legs 2 extending from the opposite sides of the package 1 in both the vertical and horizontal directions.
The length from the tip to the tip of 2 is a little longer or slightly longer, and the cut internal dimension is equivalent to the length of the package 1 in the lengthwise direction and the length in the widthwise direction, and can be inserted into the package 1. .

【0011】また透明な石英ガラス等からなる、断面が
上記枠状シート6と同等なボンディングツール7を準備
する。
A bonding tool 7 made of transparent quartz glass and having a cross section equivalent to that of the frame-shaped sheet 6 is prepared.

【0012】叙上のような構成のLSIチップのパッケ
ージ1、基板3、光硬化性樹脂を塗布したポリエチレン
テレフタレート・シート6及びボンディングツール7に
おいて、図2(a)に示すように、例えばプリント基板
3にパッケージ1を搭載する。該パッケージ1を搭載す
るに際して、クアッドフラットパッケージ(QFP)の
場合はそのまま載置し、テープキャリアパッケージ(T
CP)の場合はボンディング部分のポリイミドを取り除
き、アウターリード脚を剥出しの状態にしておく。そし
て、パッケージ1のアウターリード脚2,2・・・と配
線パターン4,4・・・を直視して位置合わせをする。
In the LSI chip package 1, the substrate 3, the photo-curable resin-coated polyethylene terephthalate sheet 6 and the bonding tool 7 having the above-described structure, as shown in FIG. Package 1 is mounted on 3. When mounting the package 1, in the case of a quad flat package (QFP), mount it as it is, and
In the case of CP), the polyimide in the bonding portion is removed and the outer lead legs are left in a peeled state. The outer lead legs 2, 2 ... Of the package 1 and the wiring patterns 4, 4 ...

【0013】次に、図2(b)に示すように、LSIチ
ップのアウターリード脚2,2・・・に対応する枠状
の、光硬化性樹脂5を塗布した透明なポリエチレン・テ
レフタレート・シート6を、該光硬化性樹脂5側をアウ
ターリード脚2,2・・・に接する如く、パッケージ1
に嵌挿して載置する。
Next, as shown in FIG. 2B, a frame-shaped transparent polyethylene terephthalate sheet coated with a photocurable resin 5 corresponding to the outer lead legs 2, 2 ... Of the LSI chip. 6 so that the photocurable resin 5 side is in contact with the outer lead legs 2, 2 ...
Insert into and place.

【0014】次に、図2(c)に示すように、上記シー
ト2上から透明なボンディングツール7によって該シー
ト2を加圧すると同時に、該ボンディングツール7を介
して紫外光(UV)Lを照射してツール7に付着してい
る光硬化性樹脂5を収縮硬化せしめる。
Next, as shown in FIG. 2C, the transparent bonding tool 7 presses the sheet 2 from above the sheet 2, and at the same time, ultraviolet light (UV) L is emitted through the bonding tool 7. Irradiation is performed to shrink and cure the photocurable resin 5 attached to the tool 7.

【0015】上記光硬化性樹脂5及びポリエチレンテレ
フタレート・シート6の収縮力により、図2(d)に示
すように、光硬化性樹脂5がアウターリード脚2,2・
・・間を埋めるように収縮硬化してボンディング処理を
完了する。従って、これにより図3に示すように、所要
箇所のアウターリード脚2と配線パターン4とは物理的
に密着し、電気的に接続され、またアウターリード脚
2,2・・・間は硬化した樹脂5’とポリエチレンテレ
フタレート・シート6で電気絶縁される。
Due to the shrinkage forces of the photocurable resin 5 and the polyethylene terephthalate sheet 6, the photocurable resin 5 causes the outer lead legs 2, 2 ...
.. Shrinkage and cure to fill the gap and complete the bonding process. Therefore, as a result, as shown in FIG. 3, the outer lead legs 2 and the wiring patterns 4 at the required locations are physically closely attached and electrically connected, and the outer lead legs 2, 2 ... Are cured. It is electrically insulated by the resin 5'and the polyethylene terephthalate sheet 6.

【0016】[0016]

【発明の効果】本発明によるアウターリードボンディン
グ法は叙上のような処理を行うものであるから、IC若
しくはLSIや周囲の部品に熱による影響を与えること
なく、また基板の寸法変化もない。
Since the outer lead bonding method according to the present invention performs the above-described processing, it does not affect the IC or LSI or the peripheral components due to heat, and the dimension of the substrate does not change.

【0017】更にボンディング後、リペアの必要が生じ
た場合、溶剤により硬化した樹脂を膨潤させることによ
ってパッケージ1を基板3からはがすことができ、再ボ
ンディングも固定用のシートを取換えるのみで行なえ
る。尚、ボンディングに必要な固定用のシートもポリエ
チレンテレフタレート・テープに光硬化性樹脂を塗布し
ただけのものなので、安価である等の利点を有する。
When repairing is required after bonding, the package 1 can be peeled from the substrate 3 by swelling the resin cured by a solvent, and rebonding can be performed only by replacing the fixing sheet. . Since the fixing sheet required for bonding is also a polyethylene terephthalate tape only coated with a photocurable resin, it has advantages such as being inexpensive.

【図面の簡単な説明】[Brief description of drawings]

【図1】本発明のアウターリードボンディング法により
処理する際の分解斜視図である。
FIG. 1 is an exploded perspective view when processing by an outer lead bonding method of the present invention.

【図2】本発明のアウターリードボンディング法の工程
図である。
FIG. 2 is a process drawing of an outer lead bonding method of the present invention.

【図3】本発明のアウターリードボンディング法の原理
図である。
FIG. 3 is a principle diagram of an outer lead bonding method of the present invention.

【符号の説明】[Explanation of symbols]

1 LSIチップのパッケージ 2 LSIチップのアウターリード脚 3 プリント基板 4 配線パターン 5 光硬化性樹脂 6 ポリエチレンテレフタレート・シート 7 ボンディングツール 1 Package of LSI chip 2 Outer lead leg of LSI chip 3 Printed circuit board 4 Wiring pattern 5 Photocurable resin 6 Polyethylene terephthalate sheet 7 Bonding tool

Claims (1)

【特許請求の範囲】[Claims] 【請求項1】 電気回路の配線パターンを配した基板上
にLSIチップのパッケージを搭載して該配線パターン
に該パッケージのアウターリード脚を位置合わせし、該
LSIチップのアウターリード脚に対応する枠状の、光
硬化性樹脂を塗布したポリエチレンテレフタレート・シ
ートを、該光硬化性樹脂側をアウターリード脚に接する
如く載置し、該ポリエチレンテレフタレート・シート上
からボンディングツールによって加圧し、該ボンディン
グツールを介して紫外光を照射して上記光硬化性樹脂を
収縮硬化せしめ、上記アウターリード脚と配線パターン
とを電気的に接続せしめることを特徴とする光硬化性樹
脂を用いたアウターリードボンディング法。
1. A frame corresponding to an outer lead leg of an LSI chip, wherein a package of an LSI chip is mounted on a substrate on which a wiring pattern of an electric circuit is arranged and an outer lead leg of the package is aligned with the wiring pattern. A polyethylene terephthalate sheet coated with a photo-curable resin is placed so that the photo-curable resin side is in contact with the outer lead leg, and pressure is applied from above the polyethylene terephthalate sheet by a bonding tool, and the bonding tool is attached. An outer lead bonding method using a photo-curable resin, characterized in that the photo-curable resin is shrunk and cured by irradiating ultraviolet light therethrough to electrically connect the outer lead legs and the wiring pattern.
JP16808392A 1992-06-26 1992-06-26 Bonding method for outer lead using photo-curing resin Pending JPH0613429A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP16808392A JPH0613429A (en) 1992-06-26 1992-06-26 Bonding method for outer lead using photo-curing resin

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP16808392A JPH0613429A (en) 1992-06-26 1992-06-26 Bonding method for outer lead using photo-curing resin

Publications (1)

Publication Number Publication Date
JPH0613429A true JPH0613429A (en) 1994-01-21

Family

ID=15861535

Family Applications (1)

Application Number Title Priority Date Filing Date
JP16808392A Pending JPH0613429A (en) 1992-06-26 1992-06-26 Bonding method for outer lead using photo-curing resin

Country Status (1)

Country Link
JP (1) JPH0613429A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6019274A (en) * 1996-09-05 2000-02-01 Oki Electric Industry Co., Ltd. Semiconductor device and mounting method therefor

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6019274A (en) * 1996-09-05 2000-02-01 Oki Electric Industry Co., Ltd. Semiconductor device and mounting method therefor

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