JPH06132576A - Manufacture of superconducting element - Google Patents

Manufacture of superconducting element

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Publication number
JPH06132576A
JPH06132576A JP4280026A JP28002692A JPH06132576A JP H06132576 A JPH06132576 A JP H06132576A JP 4280026 A JP4280026 A JP 4280026A JP 28002692 A JP28002692 A JP 28002692A JP H06132576 A JPH06132576 A JP H06132576A
Authority
JP
Japan
Prior art keywords
film
insulating film
resistance
layer
pattern
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP4280026A
Other languages
Japanese (ja)
Inventor
Yukio Sugaya
幸雄 菅家
Hirosaku Hatanaka
啓作 畑中
Toshinobu Kaneda
俊信 金田
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Ulvac Inc
Original Assignee
Ulvac Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Ulvac Inc filed Critical Ulvac Inc
Priority to JP4280026A priority Critical patent/JPH06132576A/en
Publication of JPH06132576A publication Critical patent/JPH06132576A/en
Pending legal-status Critical Current

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  • Superconductor Devices And Manufacturing Methods Thereof (AREA)

Abstract

PURPOSE:To inhibit a resistance film from being peeled during a process of forming an element and after the element is formed by a method wherein the resistance film is formed not on the surface of a layer insulating film but in the interlayer insulating film in such a way that it is fitted in the insulating film. CONSTITUTION:A layer insulator film 11 is formed on a silicon substrate 10 and a pattern formation resist layer 12 to decide a resistance film pattern is formed on the film 11 in a thickness of about 15000Angstrom . Then, the substrate 10 provided with the film 11 and the layer 12 is put in a reactive ion etching device and the film 11 is dug down to a depth of 400Angstrom . Then, the sample is moved to a deposition device and a Pd film 13 is formed in a thickness of 400Angstrom . Lastly, the layer 12 is lifted-off, whereby the resistance film 13 having a desired pattern is obtained in a state that it is buried in the film 11. Moreover, a second layer insulator film 14 is formed thereon in the same thickness as that of the film 11 and a contact hole and a superconducting film are formed.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【産業上の利用分野】本発明は、超高感度の磁気計測シ
ステム用の超伝導量子干渉素子(SQUID) や低消費電力、
超高速のコンピュータを構成するのに利用される超伝導
デジタル回路素子等の超伝導素子において、超伝導特性
のヒステリシスを消去したり、共振回路の電気的な振動
を抑えるためなどに必要とされる抵抗膜の形成方法の改
良に関するものである。
The present invention relates to a superconducting quantum interference device (SQUID) for an ultrasensitive magnetic measurement system, low power consumption,
In superconducting elements such as superconducting digital circuit elements used to construct ultra-high speed computers, it is required to eliminate hysteresis of superconducting characteristics and to suppress electrical vibration of resonant circuits. The present invention relates to an improved method of forming a resistance film.

【0002】[0002]

【従来の技術】従来、この種の超伝導素子のヒステリシ
スを打ち消すため等に使用される抵抗膜は、SiO などの
層間絶縁膜の表面上に蒸着−リフトオフ工程により形成
されていたが、この方法では一般に製造工程の後になる
ほど抵抗膜の剥離が発生し素子の歩留まりを上げるうえ
で大きな障害となっていた。従来の技術の一例としてSQ
UID における抵抗膜の形成例を図2に示す。図2におい
て、(a) はSiウエハ1上に形成したSiO の層間絶縁膜2
上にレジストを塗布して、フォトマスクのパターンを現
像し、パターン形成レジスト層3を形成した状態を示し
ている。(b) で示す工程では、Pdから成る抵抗膜4を蒸
着により成膜した後、これらをアセトン等の有機溶剤中
に浸し、レジスト層3を剥離(この工程はリフトオフと
呼ばれる)させることにより、上述のレジスト層3のパ
ターンで(c) に示すように抵抗膜4が層間絶縁膜2上に
のみ形成される。その上に(d) に示すように別の層間絶
縁膜5が形成され、そして同様に工程が繰返され、素子
の集積プロセスが継続されていくことになる。
2. Description of the Related Art Conventionally, a resistance film used for canceling the hysteresis of a superconducting device of this type has been formed on the surface of an interlayer insulating film such as SiO by a vapor deposition-lift-off process. In general, however, peeling of the resistance film occurs later in the manufacturing process, which is a major obstacle to increasing the yield of the device. SQ as an example of conventional technology
Figure 2 shows an example of forming a resistive film on a UID. In FIG. 2, (a) is the SiO 2 interlayer insulating film 2 formed on the Si wafer 1.
It shows a state in which a resist is applied on the photomask and the pattern of the photomask is developed to form the patterned resist layer 3. In the step shown in (b), after the resistance film 4 made of Pd is formed by vapor deposition, they are immersed in an organic solvent such as acetone and the resist layer 3 is peeled off (this step is called lift-off). In the pattern of the resist layer 3 described above, the resistance film 4 is formed only on the interlayer insulating film 2 as shown in (c). Another interlayer insulating film 5 is formed thereon as shown in (d), and the process is repeated in the same manner to continue the device integration process.

【0003】図3にはスパッタ法による抵抗膜の形成例
を示し、図3の(a) に示すようにまずSiウエハ1上のSi
O から成る層間絶縁膜6の全面上にスパッタ法でMo膜7
を形成し、さらにフォトリソグラフィー工程によりレジ
ストマスク8を形成する。その後図3の(b) に示すよう
に反応性イオンエッチング装置を用いてパターン以外の
レジストマスク部分を削り取る。(c) 次に図3の(c) に
示すようにレジストパターンの部分をアセトン等の溶剤
中で剥離すると所定のパターンの抵抗膜7が得られる。
さらに図3の(d) に示すように新たな層間絶縁膜9を形
成しながら素子の集積プロセスは継続されていく。
FIG. 3 shows an example of forming a resistance film by the sputtering method. As shown in FIG.
A Mo film 7 is formed on the entire surface of the interlayer insulating film 6 made of O by sputtering.
And a resist mask 8 is formed by a photolithography process. After that, as shown in FIG. 3B, a resist mask portion other than the pattern is removed by using a reactive ion etching device. (c) Next, as shown in FIG. 3 (c), the resist pattern portion is stripped in a solvent such as acetone to obtain a resistive film 7 having a predetermined pattern.
Further, as shown in FIG. 3D, the device integration process is continued while forming a new interlayer insulating film 9.

【0004】[0004]

【発明が解決しようとする課題】ところで、図2に示す
ような従来の蒸着−リフトオフ法で抵抗膜を形成した場
合、蒸着によって形成される抵抗膜の、SiO 等の層間絶
縁膜に対する付着力は十分でないため、この抵抗膜の形
成後に行われる配線、接合作成、層間絶縁膜形成等のプ
ロセスの進展につれて抵抗膜の剥離が発生し、これらの
プロセスの結果として得られる超伝導素子の歩留まりが
著しく悪化したり、素子の信頼性を低下させる等の問題
点があった。蒸着法で形成される抵抗膜がプロセス中で
剥離しやすい理由の一つには、蒸着法の場合、基板に入
射してくる粒子のエネルギーが図3に示すようなスパッ
タ法等と比べて低いために、一般に膜の基板への付着力
が弱いことが挙げられる。また、図2の(a) に示すよう
に形成されたパターン形成レジスト層3のレジストのつ
いていない面(つまり抵抗膜パターンを形成する面)の
表面に薄くレジスト等が残っていて、それが付着性をさ
らに弱めていることも指摘されている。後者の問題を克
服するために、図2の(b) に示す蒸着工程の前に、蒸着
装置内に酸素ガスを導入し、ウエハ1に13.56MHzの高周
波バイアスをかけて酸素プラズマでアッシング(残って
いるレジストを酸素プラズマで燃やす)を行い、成膜す
る界面に残っているレジストを除去する方法が行われる
ことがあるが、この方法ではパターン形成レジスト層そ
のものも同時に削られ、従って成膜する表面を清浄に
し、しかもパターン形成レジスト層の損傷を最小にする
ような条件を見つけることは容易ではない。酸素の代わ
りにアルゴン等の不活性ガスを利用することも広く行な
われているが、この方法でも下地になる膜やパターン形
成レジスト層への物理的なダメージは避けられない。
By the way, when a resistance film is formed by the conventional vapor deposition-lift-off method as shown in FIG. 2, the adhesive force of the resistance film formed by vapor deposition to the interlayer insulating film such as SiO 2 is Since the resistance film is not sufficient, peeling of the resistance film occurs along with the progress of processes such as wiring, junction formation, and interlayer insulating film formation performed after the formation of the resistance film, and the yield of the superconducting element obtained as a result of these processes is remarkable. There are problems such as deterioration and deterioration of reliability of the device. One of the reasons why the resistance film formed by the vapor deposition method is easily peeled off during the process is that the energy of particles incident on the substrate is lower in the vapor deposition method than in the sputtering method as shown in FIG. Therefore, the adhesion of the film to the substrate is generally weak. In addition, a thin resist or the like remains on the surface of the pattern-forming resist layer 3 formed as shown in FIG. 2 (a) on the non-resisted surface (that is, the surface on which the resistive film pattern is formed), and it is attached. It has also been pointed out that it is further weakening sex. In order to overcome the latter problem, oxygen gas was introduced into the vapor deposition apparatus before the vapor deposition step shown in FIG. 2B, and a high frequency bias of 13.56 MHz was applied to the wafer 1 to ash it with oxygen plasma. The existing resist is burned with oxygen plasma) to remove the resist remaining at the interface where the film is formed. In this method, the patterned resist layer itself is also scraped, so the film is formed. It is not easy to find conditions that clean the surface and yet minimize damage to the patterned resist layer. Although it is widely practiced to use an inert gas such as argon instead of oxygen, physical damage to the underlying film and the patterned resist layer is unavoidable even with this method.

【0005】これに対して、図3に示すように抵抗膜と
して剥離しやすい蒸着膜でなく、付着力の強いMo等のス
パッタ膜を使用する試みも行われているが、スパッター
膜は一般にリフトオフによりパターン形成ができず、反
応性イオンエッチング装置を用いた、プロセス的にリフ
トオフ法よりはるかに複雑なエッチング工程が必要とな
る。しかも、一般にスパッタ法において抵抗膜としてよ
く用いられるMo膜のエッチングにおいては超伝導素子の
形成において最もよく使用されるNb膜やSiO 膜用のエッ
チング装置と共用できないので、結局新たにエッチング
装置を用意する必要がある。すなわち、Moをエッチング
した後、同じエッチング装置でNbをエッチングしようと
すると、Nbのエッチングレートが極端に小さくなるため
にそれ以降の工程が非常に困難になることが知られてお
り、そのためMo抵抗膜のエッチング工程では超伝導素子
の主要な部分であるNb超伝導膜やSiO 層間絶縁膜のエッ
チングに利用される装置とは別個のエッチング装置が必
要となる。このことは超伝導素子の製造設備の費用を大
きくするだけでなく、高性能の超伝導素子を作製すると
いう目的のうえで管理すべき工程やパラメータを増大さ
せることになり、結果としてプロセス全体としてみた場
合の素子の歩留まりや信頼性の低下をもたらすことにな
る。
On the other hand, as shown in FIG. 3, an attempt is made to use a sputtered film of Mo or the like, which has a strong adhesive force, as a resistance film instead of a vapor-deposited film which is easily peeled off, but the sputtered film is generally lifted off. As a result, a pattern cannot be formed, and an etching process using a reactive ion etching apparatus, which is far more complicated than the lift-off method, is required. Moreover, in the etching of the Mo film, which is often used as a resistance film in the sputtering method, it cannot be shared with the etching device for Nb film or SiO 2 film that is most often used in the formation of superconducting elements. There is a need to. That is, if it is attempted to etch Nb with the same etching device after etching Mo, it is known that the subsequent steps become extremely difficult because the etching rate of Nb becomes extremely small. The film etching process requires an etching device separate from the device used for etching the Nb superconducting film and the SiO 2 interlayer insulating film, which are the main parts of the superconducting device. This not only increases the cost of the superconducting device manufacturing equipment, but also increases the number of steps and parameters that must be controlled for the purpose of producing a high-performance superconducting device. If this is seen, the yield and reliability of the device will be reduced.

【0006】本発明は、上記のような従来の技術のもつ
問題点を解決して、新たにエッチング装置を導入してプ
ロセスを複雑化することなく、十分な付着力をもつ抵抗
膜を蒸着−リフトオフ法で形成し、高い歩留まりでSQUI
D 等の超伝導素子を作成できる超伝導素子の形成方法を
提供することを目的としている。
The present invention solves the above-mentioned problems of the conventional technique and vapor-deposits a resistance film having sufficient adhesive force without introducing a new etching apparatus and complicating the process. Formed by lift-off method, SQUI with high yield
It is an object of the present invention to provide a method for forming a superconducting device capable of producing a superconducting device such as D.

【0007】[0007]

【課題を解決するための手段】上記の目的を達成するた
めに、本発明による超伝導素子の製造法は、基板上に薄
膜を集積して抵抗膜を形成するに際して、まず基板上に
絶縁体膜を形成し、この絶縁体膜の上に所定のパターン
をもつレジスト層を形成し、レジスト層で画定された絶
縁体膜部分を形成すべき抵抗層の厚さと同程度の深さに
エッチングし、そしてエッチング処理した絶縁体膜上に
上記抵抗膜を蒸着した後レジスト層をリフトオフして所
定のパターンの抵抗膜を絶縁体膜内に形成すること特徴
としている。好ましくは、所定のパターンの抵抗膜は多
層に形成される各絶縁体膜内に繰返し形成され得る。
In order to achieve the above object, a method of manufacturing a superconducting device according to the present invention is designed such that when a thin film is integrated on a substrate to form a resistance film, an insulator is first formed on the substrate. A film is formed, a resist layer having a predetermined pattern is formed on the insulating film, and the insulating film portion defined by the resist layer is etched to a depth approximately equal to the thickness of the resistance layer to be formed. The resist film is lifted off after the resistance film is deposited on the etched insulation film to form a resistance film having a predetermined pattern in the insulation film. Preferably, the resistive film having a predetermined pattern may be repeatedly formed in each insulating film formed in multiple layers.

【0008】[0008]

【作用】本発明の方法では、パターン形成レジスト層の
形成後すぐに抵抗膜を蒸着しないで、エッチング装置で
層間絶縁膜を、形成しようとする抵抗膜と同程度の厚さ
だけ削り、その削り取った部分に抵抗膜を成膜すること
により、抵抗膜は層間絶縁膜の中に埋め込まれ、すなわ
ち層間絶縁膜の表面上でなくその中に嵌合するようにし
て形成されるので、抵抗膜の付着力は飛躍的に増大され
ることになる。またこの場合、エッチングするのは層間
絶縁膜であるSiO 等であるから、従来Nb超伝導膜および
SiO 層間絶縁膜の加工に使っているエッチング装置を問
題なく流用でき、新たにエッチング装置を導入する必要
はない。さらにレジストパターン形成のためのフォトリ
ソグラフィー工程も従来と全く同様に実施され得る。
According to the method of the present invention, the resistance film is not vapor-deposited immediately after the formation of the patterning resist layer, and the interlayer insulating film is removed by an etching apparatus to a thickness of about the same as the resistance film to be formed. By forming the resistance film in the portion where the resistance film is formed, the resistance film is embedded in the interlayer insulation film, that is, formed so as to fit into the interlayer insulation film, not on the surface thereof. Adhesion will be dramatically increased. Further, in this case, since the interlayer insulating film such as SiO 2 is etched, the conventional Nb superconducting film and
The etching apparatus used for processing the SiO 2 interlayer insulating film can be used without any problem, and it is not necessary to introduce a new etching apparatus. Further, the photolithography process for forming the resist pattern can be performed in the same manner as the conventional one.

【0009】[0009]

【実施例】以下本発明の実施例を図1に基づいて説明す
る。なお、図1において工程(a),(c),(d),(e) は、それ
ぞれ、従来法を示す図2における工程(a),(b),(c),(d)
と基本的に同じ工程である。 工程(a) 2インチシリコン基板10上にSiO から成る層間
絶縁体膜11を4000オングストロームの厚さに成膜し、こ
の層間絶縁体膜11上に抵抗膜パターンを決めるパターン
形成レジスト層12を約15000 オングストロームの厚さに
形成する。 工程(b) 工程(a) で層間絶縁体膜11及びパターン形成レ
ジスト層12の設けられたシリコン基板10を反応性イオン
エッチング装置に入れ、CF4 ガスにより、エッチング室
内の圧力を2.67Paに設定して、13.56MHzの高周波プラズ
マにより、投入パワー100W/250mmφで400 オングストロ
ームまで堀り下ろす。このときのエッチングレートは5
オングストローム/sec であった。 工程(c) こうしてエッチング処理したり試料を蒸着装置
に移し、10-5Pa台の圧力まで排気して電子ビーム蒸着に
よりPd膜13を400 オングストロームの厚さに成膜した。 工程(d) 最後に、試料をアセトンに漬け、パターン形成
レジスト層12をリフトオフすることにより、所望のパタ
ーンの抵抗膜13が層間絶縁体膜11に埋め込まれた状態で
得られる。 工程(e) さらにその上に第2の層間絶縁体膜14が第1の
層間絶縁体膜11とほぼ同じ厚さに成膜され、そしてコン
タクトホールの形成、超伝導膜の形成...というよう
に工程を続けて実施していった。 このようにして得られた所望のパターンの抵抗膜は例え
ば図2に示すような従来のものと比べて、抵抗膜13の側
壁部も層間絶縁体膜11により保持されることになり、付
着性は大幅に向上し、SQUID 製造工程でこの方法を適用
した場合にプロセス中に剥離した抵抗膜は全く無かっ
た。しかも積層型の素子を作成する上で重要な平坦化
(つまり新しい層を積層する前に下地の高さを一様にす
る)が同時に行われるという利点がある。また工程(b)
でパターン形成レジスト層12を掘り下げているので、工
程(a) で多少レジストがパターン部以外に残っていたと
しても完全に除去することができ、下地との付着性を向
上させることができるようになる。なお実際のSQUID の
製作においては、図面に示してないが層間絶縁体膜11の
下層及び上層にそれぞれ超伝導膜のパターンが形成され
る。
Embodiment An embodiment of the present invention will be described below with reference to FIG. Note that steps (a), (c), (d), and (e) in FIG. 1 are the steps (a), (b), (c), and (d) in FIG. 2 showing the conventional method, respectively.
Is basically the same process. Step (a) An interlayer insulating film 11 made of SiO 2 is formed to a thickness of 4000 angstroms on a 2-inch silicon substrate 10, and a pattern forming resist layer 12 for determining a resistance film pattern is formed on the interlayer insulating film 11. Formed to a thickness of 15000 angstroms. Step (b) The silicon substrate 10 provided with the inter-layer insulator film 11 and the patterned resist layer 12 in the step (a) is put into a reactive ion etching apparatus, and the pressure in the etching chamber is set to 2.67 Pa by CF 4 gas. Then, with a high-frequency plasma of 13.56 MHz, the power input is 100 W / 250 mmφ, and it is dug down to 400 Å. The etching rate at this time is 5
It was Angstrom / sec. Step (c) In this way, the etching treatment or the sample was transferred to the vapor deposition apparatus, the pressure was evacuated to the order of 10 −5 Pa, and the Pd film 13 was deposited to a thickness of 400 Å by electron beam vapor deposition. Step (d) Finally, the sample is soaked in acetone and the patterned resist layer 12 is lifted off, whereby the resistance film 13 having a desired pattern is obtained in a state of being embedded in the interlayer insulating film 11. Step (e) Further, a second interlayer insulating film 14 is formed thereon to a thickness of about the same as the first interlayer insulating film 11, and a contact hole is formed and a superconducting film is formed. . . And so on, the process was continued. The resistance film having a desired pattern thus obtained has a sidewall portion of the resistance film 13 also held by the interlayer insulating film 11 as compared with the conventional one as shown in FIG. Was significantly improved, and no resistive film was peeled off during the process when this method was applied in the SQUID manufacturing process. Moreover, there is an advantage that planarization, which is important in producing a laminated element, (that is, the height of the base is made uniform before a new layer is laminated) is performed at the same time. Also step (b)
Since the pattern formation resist layer 12 is dug down in, it is possible to completely remove the resist even if it is left in the area other than the pattern part in the step (a), and improve the adhesion to the base. Become. In the actual fabrication of the SQUID, although not shown in the drawings, superconducting film patterns are formed in the lower and upper layers of the interlayer insulating film 11, respectively.

【0010】なお、上記実施例では抵抗膜としてPdが用
いられているが、蒸着法で成膜できる常伝導体であれば
どのような材料を用いてもよい。その結果、図3に示す
ような従来のスパッターエッチング法による場合には抵
抗膜に応じたエッチングガスを選定し、適切なエッチン
グ条件を選定しないと利用できないのに対して、本発明
による方法では、抵抗膜材料に対する適用範囲がはるか
に広くなり有効となることが認められる。また、層間絶
縁体膜はSiO に限らす、SiO2 、MgO など一般に超伝導
素子の製作において用いられる絶縁体であれば、新たに
エッチング装置を導入することなく従来のエッチング装
置で加工できるのでそれらの材料を容易に利用すること
もできる。さらに、超伝導体としてはNbが最も広く用い
られるが、本発明の方法では特にNbに限定する必要はな
く、使用する基板の種類も当然Siウエハに限られるもの
ではない。
Although Pd is used as the resistance film in the above embodiment, any material may be used as long as it is a normal conductor that can be formed by the vapor deposition method. As a result, in the case of the conventional sputter etching method as shown in FIG. 3, it cannot be used unless an etching gas is selected according to the resistance film and an appropriate etching condition is selected. It is recognized that the range of application for resistive film materials becomes much wider and effective. In addition, the interlayer insulating film is not limited to SiO 2 , but if it is an insulator such as SiO 2 or MgO that is generally used in the production of superconducting elements, it can be processed by a conventional etching device without newly introducing an etching device. It is also possible to easily use the above materials. Further, Nb is most widely used as a superconductor, but it is not necessary to limit it to Nb in the method of the present invention, and the type of substrate used is not limited to the Si wafer.

【0011】[0011]

【発明の効果】以上説明してきたように本発明の超伝導
素子の製造法においては、抵抗膜を層間絶縁膜の表面上
でなく、その中に嵌合させて形成しているので、従来用
いられてきた蒸着−リフトオフ法の特長である材料選択
の余地が広く、装置及びプロセスとしても単純であると
いう点を生かしながら、なおかつ、スパッターエッチン
グ法に劣らない付着性に優れ、しかも同時に平坦化され
ているという特徴をもつ抵抗膜を極めて簡易に効果的に
形成することができるようになる。
As described above, in the method for manufacturing a superconducting element of the present invention, the resistance film is formed not by being fitted on the surface of the interlayer insulating film but by being fitted therein. While taking advantage of the wide range of materials that can be selected, which is a feature of the evaporation-lift-off method that has been used, and that it is simple in equipment and process, it has excellent adhesion that is not inferior to that of the sputter etching method, and at the same time planarizes It becomes possible to effectively and easily form a resistance film having the feature that

【図面の簡単な説明】[Brief description of drawings]

【図1】 本発明の一実施例による方法の種々の工程を
示す概略断面図。
FIG. 1 is a schematic cross-sectional view showing various steps of a method according to an embodiment of the present invention.

【図2】 従来の蒸着−リフトオフ法による抵抗膜の形
成方法を示す概略断面図。
FIG. 2 is a schematic cross-sectional view showing a method of forming a resistance film by a conventional vapor deposition-liftoff method.

【図3】 従来のスパッタ−エッチング法による抵抗膜
の形成方法を示す概略断面図。
FIG. 3 is a schematic sectional view showing a method of forming a resistance film by a conventional sputter-etching method.

【符号の説明】[Explanation of symbols]

10:シリコン基板 11:層間絶縁体膜 12:パターン形成レジスト層 13:Pd膜(抵抗膜) 14:第2の層間絶縁体膜 10: Silicon substrate 11: Interlayer insulating film 12: Pattern forming resist layer 13: Pd film (resistive film) 14: Second interlayer insulating film

Claims (2)

【特許請求の範囲】[Claims] 【請求項1】基板上に薄膜を集積して形成される抵抗膜
を備えた超伝導素子の製造法において、基板上に絶縁体
膜を形成し、この絶縁体膜の上に所定のパターンをもつ
パターン形成レジスト層を形成し、レジスト層で画定さ
れた絶縁体膜部分を形成すべき抵抗層の厚さと同程度の
深さにエッチングし、そしてエッチング処理した絶縁体
膜上に上記抵抗膜を蒸着した後レジスト層をリフトオフ
して所定のパターンの抵抗膜を絶縁体膜内に形成するこ
と特徴とする超伝導素子の製造法。
1. A method of manufacturing a superconducting device comprising a resistive film formed by integrating thin films on a substrate, wherein an insulating film is formed on the substrate, and a predetermined pattern is formed on the insulating film. Pattern forming resist layer is formed, the insulating film portion defined by the resist layer is etched to a depth approximately equal to the thickness of the resistive layer to be formed, and the resistive film is formed on the etched insulating film. A method for manufacturing a superconducting device, characterized in that the resist layer is lifted off after vapor deposition to form a resistance film having a predetermined pattern in an insulator film.
【請求項2】所定のパターンの抵抗膜が組合さった絶縁
体膜内に繰返し多層に形成される請求項1に記載の超伝
導素子の製造法。
2. The method for manufacturing a superconducting device according to claim 1, wherein a resistance film having a predetermined pattern is repeatedly formed in multiple layers within an insulating film.
JP4280026A 1992-10-19 1992-10-19 Manufacture of superconducting element Pending JPH06132576A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP4280026A JPH06132576A (en) 1992-10-19 1992-10-19 Manufacture of superconducting element

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP4280026A JPH06132576A (en) 1992-10-19 1992-10-19 Manufacture of superconducting element

Publications (1)

Publication Number Publication Date
JPH06132576A true JPH06132576A (en) 1994-05-13

Family

ID=17619268

Family Applications (1)

Application Number Title Priority Date Filing Date
JP4280026A Pending JPH06132576A (en) 1992-10-19 1992-10-19 Manufacture of superconducting element

Country Status (1)

Country Link
JP (1) JPH06132576A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2020504445A (en) * 2017-01-20 2020-02-06 ノースロップ グラマン システムズ コーポレイションNorthrop Grumman Systems Corporation Method for forming a resistive element in a superconducting wiring structure

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2020504445A (en) * 2017-01-20 2020-02-06 ノースロップ グラマン システムズ コーポレイションNorthrop Grumman Systems Corporation Method for forming a resistive element in a superconducting wiring structure

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