JPH06132400A - Layout method of semiconductor integrated circuit - Google Patents

Abstract

PURPOSE:To lessen a semiconductor integrated circuit in design time by a method wherein an actual wiring is adjusted in area and route so as to make an actual wiring and a virtual wiring equal to each other in capacity when an actual wiring and a virtual wiring are different from each other in length after a layout-wiring operation is finished. CONSTITUTION:If a delay value caused by the virtual wiring length of a route from a terminal A to a terminal B is 3 (=1+2), an actual wiring is adjusted in area (length, width) and route conforming to the delay value caused by a load of the virtual wiring length of a route from a terminal A to a terminal B so as to set a delay time t1+t2 from the terminal A to the terminal B equal to the same delay value of 3 with the virtual wiring. That is, provided that t1 and t2 are 0.6 and 2.7 respectively in an actual wiring, t2 is set to 2.4 (=3-0.6).

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a layout method of a semiconductor integrated circuit in which a temporary wiring length is given between circuit elements whose layout is to be determined, and then the operation is simulated, and more particularly, the layout method of the semiconductor integrated circuit is arranged. A semiconductor integrated circuit capable of shortening the design period by omitting relayout, circuit correction, and simulation after relayout when a difference occurs between the actual wiring length after wiring and the temporary wiring length. It relates to a layout method.

[0002]

2. Description of the Related Art In general, when laying out a semiconductor integrated circuit, as shown in FIG. Simulate. At the time of this tentative wiring length simulation, the simulation is performed with an expected wiring length (temporary wiring length) that becomes an actual wiring length according to a predetermined formula.

By this tentative wiring length simulation, it is confirmed that the circuit operates normally, and then the placement and wiring are performed.

Then, the actual wiring length (0.
8) Since there is a difference between (1.9) and the tentative wiring lengths (1) and (2), timing errors (setup, hold time) not present during the tentative wiring simulation may occur.

[0005]

Therefore, conventionally, it is necessary to reconfirm that the circuit operates normally by performing an actual wiring length simulation with the actual wiring length (0.8) (1.9). It was In particular, if the actual wiring length simulation does not operate normally, it is necessary to re-arrange the layout and wiring, and if it is severe, it is necessary to return to the circuit diagram correction and perform the work again.

The present invention has been made to solve the above-mentioned conventional problems, and the logical confirmation can be completed only by the tentative wiring length simulation performed before the placement / wiring, thus shortening the design period. It is an object of the present invention to provide a layout method of a semiconductor integrated circuit capable of performing the above.

[0007]

SUMMARY OF THE INVENTION The present invention provides a layout method of a semiconductor integrated circuit in which a temporary wiring length is given between circuit elements whose layout is to be determined, and then the operation is simulated. When there is a difference between the actual wiring length afterwards and the temporary wiring length, the area and the route of the actual wiring are adjusted so that the capacitances of the two become the same, thereby achieving the above object. .

[0008]

In the present invention, when there is a difference between the actual wiring length after placement / wiring and the tentative wiring length during the tentative wiring length simulation, the electrostatic capacitances (ie, wiring capacitances) of both are matched. The area and route of the actual wiring are adjusted.
Therefore, it is not necessary to re-execute the simulation after the placement / wiring, and it is not necessary to re-execute the placement / wiring or to modify the circuit, and the design period can be shortened.

[0009]

Embodiments of the present invention will now be described in detail with reference to the drawings.

In the layout according to this embodiment, for example, as shown in FIG. 2, when the delay value due to the tentative wiring length of the route from the terminal A to the terminal B is (1 + 2 = 3),
The area (length, width) and the route of the actual wiring are adjusted according to the delay value of the load of the tentative wiring length from the terminal A to the terminal B, and the delay value (t ₁ + t from the terminal A to the terminal B is adjusted. ₂ ) so that the delay value (3) is the same as in the temporary wiring.

That is, for example, with real wiring, t ₁ is 0.6,
When t ₂ is 2.7, for example, t ₂ is 2.4.
(= 3-0.6).

FIG. 3 shows the area of the actual wiring and the delay values t ₁ and t _2.
As shown in FIG. 4, the sum of the delay values from terminal A to terminal B (t ₁ + t ₂ ) is the delay value of the load of the tentative wiring length (3 in the figure). The wiring area and route between the circuit elements P1 and P2 and between the circuit elements P2 and P3 are adjusted so that

In this embodiment, the delay value from the terminal A to the terminal B is a problem, and the circuit elements P1 and P2 and P2 are connected to each other.
Since each delay value between −P3 was not a problem, the delay value t ₁ + t ₂ from the terminal A to the terminal B was made to match the delay value of the load of the tentative wiring length.
When the delay values between 1-P2 and between P2-P3 also pose a problem, the delay values between the respective circuit elements should match the delay values (1) and (2) of the load of the tentative wiring length. In addition, the area and route of each actual wiring can be adjusted.

[0014]

According to the present invention, the wiring capacitance after the placement / wiring is adapted to the wiring capacitance expected before the placement / wiring. Therefore, only the tentative wiring length simulation performed before the placement / wiring is performed. The logic check ends. Therefore, operation simulation after placement / wiring, re-execution of placement / wiring,
No circuit modification is required, and the design period can be shortened.

[Brief description of drawings]

FIG. 1 is a diagram for explaining a conventional layout method.

FIG. 2 is a diagram showing an example of a layout method according to the present invention.

FIG. 3 is a diagram showing an example of a relationship between an area of actual wiring and a delay value in the embodiment.

FIG. 4 is a diagram showing an example of a relationship between a total delay value between terminals A and B and a delay value between circuit elements P1 and P2 and between P2 and P3.

[Explanation of symbols]

A, B ... terminal P1, P2, P3 ... circuit elements t _1, t ₂ ... delay value

Claims (1)

[Claims] 1. A method of laying out a semiconductor integrated circuit, wherein a temporary wiring length is given between circuit elements whose layout is to be determined, and then an operation is simulated. A layout method of a semiconductor integrated circuit, wherein when a difference occurs between wiring lengths, the area and route of the actual wiring are adjusted so that the capacitances of the two match.