JP3185892B2 - Timing simulation method - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a monolithic IC, relates verification method in designing a semiconductor integrated circuit such as a hybrid IC, in particular its timing simulation side
Method (hereinafter also referred to as “timing simulation method”)
U) .

[0002]

2. Description of the Related Art An IC is designed in various stages. FIG. 1 shows from the functional design to the layout design in the design flow. In the design process of the functional design a, the logic design b, the circuit design c, and the layout design d, usually, software for verification is prepared, respectively, which contributes to improvement of reliability of each design process and reduction of man-hours. ing. The functional design a is a process of determining a functional component, creating a functional block diagram, determining a control method, and the like based on the functional specification, and performs a functional simulation e to confirm a functional operation. The logic design b is a step of implementing a logic configuration and defining a connection relationship between gates so as to satisfy the logic specification determined by the function design a. Logic simulation f performed by the logic simulator
Implements on the simulator a netlist of logic gates according to the rules of the logic simulator, and confirms by software processing whether an output signal as expected is obtained for an input signal given as appropriate. . After the completion of the logic design b, the layout design d may be performed via the circuit design c, or the layout design d may be performed immediately from the logic gate level. The circuit design c is a so-called transistor-level design, and is a step of combining elements such as resistors and capacitors and determining the parameters and connection relations of those elements. There is a circuit simulation g as a software for verifying a circuit design.
This is a program that performs AC and transient analysis. The layout design d is a process of deciding the arrangement of elements such as transistors or blocks composed of them according to the result of the logical design b or the circuit design c, and performing wiring between them. There are various types of verification programs h in the layout design d, but a typical one is a DRC (Design Rule Check) for verifying geometric design rules such as a minimum line width and a minimum interval of a pattern due to manufacturing restrictions.
(Electrical Rule Ch) that verifies electrical rules such as short circuit, disconnection of power supply, and opening of input gate.
eck).

In the design flow described above, for example,
It is assumed that the layout design d is performed after the completion of the logical design b. At this time, there is no problem in the logic design, and even if the layout design is performed using the result, a parasitic element may be generated depending on the layout, that is, the layout position of the logic gates and the length of the wiring therebetween. That is, the wiring resistance,
These are wiring capacitance and wiring inductance. It is good if the delay time due to these parasitic elements is short and there is no problem in circuit operation. However, if a malfunction occurs due to the delay time caused by the parasitic elements, the layout design d must be redone.

[0004] In such a case, verification is performed in consideration of the delay time, and it is confirmed whether or not there is a defect due to the delay time. Verification taking this delay time into account is timing simulation. FIG. 2 is a flowchart showing a conventional timing simulation method. In step # 105, the above function design a
Perform Based on the result of the functional design, a netlist (e) for a functional simulation e is created in step # 110. The net list (e) represents the connection relationship (net) of the functional blocks, and receives this as an input to execute a functional simulation e in step # 115. If the result of the function simulation e is not as expected, the function design a and the function simulation e are repeated until the function is satisfied. Subsequently, in step # 120, a logical design b is performed based on the results of the functional design a and the functional simulation e. From this result, a net list (f) for the logic simulation f is created in step # 125. The netlist (f) represents the connection relationship of the logic gate. With this as an input, a logic simulation f is executed in step # 130. Here, similarly to the function design process, if the result of the logic simulation f is not as expected, the logic design b and the logic simulation f are repeated until the function is satisfied.
Thereafter, based on the results of the logical design b and the logical simulation e, a layout design d is performed in step # 135. After finishing the layout design d, in step # 140, a parasitic element such as a wiring resistance is extracted. In step # 145,
A netlist (g) for a circuit simulation g in which the parasitic element is replaced with an equivalent circuit and included in the input information is created. With this as an input, a circuit simulation g is executed in step # 150. Based on the result of the circuit simulation g, it is determined whether or not the delay time due to the parasitic element is a problem in step # 155.
Return to 35 and re-design the layout. If there is no problem, end the design.

[0005] As a conventional timing verification method, as shown in FIG. 2, (1) wiring capacitance, wiring resistance, etc. are returned to a transistor-level netlist, and a circuit simulator (analog simulator or analog simulator) corresponding to a large-scale circuit is used. Analysis is performed by a switching simulator to verify the timing. For example, there are the following two methods. (2) The CR time constant is determined from the wiring capacitance and the output impedance of the drive gate, and the delay time of each gate is determined. This is fed back to the logic simulator to verify the timing. (3) A maximum allowable delay time of each wiring is determined before the layout design, and the layout design is performed in consideration of the wiring length so that a delay longer than that time is not generated.
Although the delay time is taken into consideration, the timing simulation is not actually performed.

[0006]

Problems of the conventional system will be described according to the above-mentioned numbers. First, in the case of (1), a large-scale IC needs to collectively analyze a large amount of netlist information at a transistor level, so that a large-capacity storage device and a computer having a large arithmetic capability are required.
Also, the interface with the simulation performed at the time of functional design and logic design did not match, and it was difficult to compare the respective results. In the method (2), the delay times of the gates on the same wiring are all the same, and a difference in arrangement cannot be expressed. Furthermore, in the method of (3),
In addition to the same problems as (2), there are the following disadvantages. That is, the wiring length is restricted during the layout design, and it is difficult to create a mask pattern that satisfies the restriction. In some cases, it is necessary to increase each gate capability to cope with this limitation. An object of the present invention is to solve such a problem and to provide a timing simulation method capable of calculating a delay time that causes a difference in arrangement position even for gates on the same wiring, and shortening the verification time. .

[0007]

To achieve the above object, the present invention provides a semiconductor integrated circuit having a large number of repetitive parts.
Design using functional design, logical design, and layout design.
Design delay in consideration of delay time due to parasitic elements
This is a timing simulation method to calculate the rising and falling waveforms of the voltage for each node in the wiring from the preceding gate to the succeeding gate, with respect to the delay time caused by the parasitic element caused by the layout design of the semiconductor integrated circuit. Te calculated, determined delay time until each node from the previous gate time to those waveforms off threshold voltage of the next stage gate as a delay time
I am trying to do it. Then, the delay time information obtained as described above is fed back as input information of the function simulator or the logic simulator.

[0008]

In this way, since the delay time is calculated for each gate, the difference in the arrangement position is reflected in the delay time even for gates on the same wiring. Therefore, accurate timing simulation can be performed, and the layout design can be corrected with high accuracy. In addition, since the delay time information can be fed back as an input to the function simulator or logic simulator to perform function or logic simulation, the execution time can be greatly reduced compared to the case of performing circuit simulation, and the results can be analyzed. Easy to do.

[0009]

Embodiments of the present invention will be described below with reference to the drawings.
explain. FIG. 3 shows a method for calculating a delay time according to the present invention. Inverters INV1, INV2, INV3
And calculating the delay time for the circuit (a) composed of the resistors R1, R2 and the capacitors C1, C2, C3, the rising and falling waveforms of the voltages VN1, VN2, VN3 at the nodes N1, N2, N3 are Calculate, the time to cut the threshold voltage of the next stage gate as delay time, said resistance,
An equivalent circuit as shown in FIG. More specifically, the inverter (gate) I
For example, since a pulse is output from the NV1, it is necessary to calculate how much the rise and fall of the pulse are delayed at the nodes N1, N2 and N3. Now, in the case of the rise, FIG. This will be described with reference to c). Since the output voltage of the inverter INV1 charges the capacitor C1, the voltage of the node N1 becomes like α in FIG. In addition, the voltage generated at the node N2 is delayed by the resistance R1 and the capacitance C2 in addition to the capacitance C, and thus increases with a delay like β. Similarly, the voltage generated at the node N3 is delayed by γ because it is delayed by the capacitors C1, C2, C3 and the resistors R1, R2, R3. By the way, the above α,
In the characteristics of β and γ, which point is the delay time
It is determined based on the threshold voltage E _O of the succeeding inverters INV2 and INV3. Accordingly, the times T1, T2, and T3 at which the threshold voltage E _O is cut off correspond to the nodes N1,
This is the delay time when the voltage rises at N2 and N3.
Since the threshold voltages of the inverters INV2 and INV3 are the same elements formed in the same IC,
The threshold voltage is the same. Ru is determined in the same manner also for the fall of the voltage. By performing the above calculation for each wiring and feeding back to the term describing the delay time of the input description language of the functional simulator or the theoretical simulator, the function incorporating the delay time information and the theoretical simulation, that is, the timing simulation can be performed. I can do it.

FIG. 4 shows a flow chart of a design for performing a timing simulation according to the present invention. The process up to the extraction of the parasitic element after the layout design is almost the same as the flowchart of FIG. In step # 205, function design a is performed. Based on this result, a netlist (e) for functional simulation e is created in step # 210,
With this as an input, function simulation e is executed in step # 215. Subsequently, in step # 220, a logical design b is performed based on the results of the functional design a and the functional simulation e. Based on this result, a net list (f) for the logic simulation f is created in step # 225, and the logic list f is executed in step # 230 by using this as an input. Then, based on the results of the logic design b and the logic simulation e, a layout design is performed in step # 235. After the layout design, in step # 240, parasitic elements such as wiring resistance are extracted. Step # 245
Then, the delay time is calculated as shown in FIG. 3 from the information of the netlists (e) and (f) and the extracted information of the parasitic element. In step # 250, it is determined whether or not to perform the function simulation. If the function simulation is to be performed, the process returns to step # 210, and a netlist (e) incorporating delay time information is created. Execute If functional simulation is not performed in step # 250, it is determined in step # 255 whether a logical simulation is performed. If logic simulation is to be performed, return to step # 225
A netlist (f) incorporating the delay time information is created, and step # 230 and subsequent steps are executed. If the delay time obtained in step # 245 does not cause a problem on the circuit, there is no need to re-design the layout and no timing simulation or the like is necessary, so the design is ended in step # 260.

The timing simulation method of the present invention can be applied not only to semiconductor integrated circuits but also to the design of printed circuit boards and the design of various electronic devices.

[0012]

As described above, according to the present invention,
The delay time due to parasitic elements such as wiring resistance and wiring capacitance caused by the layout design is calculated by calculating the rising and falling waveforms of the voltage for each node in the wiring from the preceding gate to the succeeding subsequent gate. seeking slow <br/> length of time from the preceding gate to the respective nodes as the delay time the time until off threshold voltage of the next stage gate, because the timing verification is possible to better verify accurate it can. In this way, the Repetitive <br/> Ri returns pattern often layout can significantly reduce the computation time. Further, since calculations can be performed individually for each wiring unit, parallel processing can be easily performed, and the time can be further reduced. Further, since the delay time information is input information of the function simulator and the logic simulator, the settings used for the simulator at the time of function design and logic design can be used as they are in the timing simulation, which is efficient.
Furthermore, there is an advantage that the analysis of the result can be easily performed.

[Brief description of the drawings]

FIG. 1 is a diagram showing a flow of IC design.

FIG. 2 is a diagram showing a conventional timing simulation method.

FIG. 3 is a diagram showing a method for calculating a delay time according to the present invention.

FIG. 4 is a diagram showing a timing simulation method embodying the present invention.

[Explanation of symbols]

 a Functional design b Logical design c Circuit design d Layout design f Functional simulation e Logical simulation f Circuit simulation g Layout verification INV1 transistor INV2 transistor INV3 transistor R1 resistance R2 resistance C1 capacitance C2 capacitance C3 capacitance N1 node N2 node N3 node PS power supply

Claims (2)

(57) [Claims] 1. A semiconductor integrated circuit having a large number of repetitive parts.
Design using functional design, logical design, and layout design.
Design delay in consideration of delay time due to parasitic elements
This is a timing simulation method that calculates the rising and falling waveforms of the voltage for each node in the wiring from the previous gate to the subsequent gate, for the delay time due to the parasitic element that occurs with the layout design of the semiconductor integrated circuit. From the previous gate as the delay time until those waveforms cross the threshold voltage of the next gate.
Timing simulation method characterized by determining a delay time to each node. 2. The timing simulation method according to claim 1, wherein the delay time obtained as described above is fed back as input information of a function simulator or a logic simulator.