JPH0612623Y2 - Chippujiyanpa - Google Patents
ChippujiyanpaInfo
- Publication number
- JPH0612623Y2 JPH0612623Y2 JP6129390U JP6129390U JPH0612623Y2 JP H0612623 Y2 JPH0612623 Y2 JP H0612623Y2 JP 6129390 U JP6129390 U JP 6129390U JP 6129390 U JP6129390 U JP 6129390U JP H0612623 Y2 JPH0612623 Y2 JP H0612623Y2
- Authority
- JP
- Japan
- Prior art keywords
- ceramic substrate
- plating layer
- top surface
- solder
- silver
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
Landscapes
- Multi-Conductor Connections (AREA)
Description
【考案の詳細な説明】 [産業上の利用分野] 本考案は、短絡用のチツプ状電子部品であるチツプジヤ
ンパに関する。DETAILED DESCRIPTION OF THE INVENTION [Industrial field of application] The present invention relates to a chip jimper which is a chip-shaped electronic component for short circuit.
[従来の技術] 従来のチツプジヤンパは、第4図およびそのA−A線断
面図である第5図に示すように、直方体形状のセラミツ
ク基板1と、このセラミツク基板1の天面および両端面
を抱き込んで略C字形状に延設した銀下地層2と、この
銀下地層2に被着せしめたニツケルメツキ層3と、この
ニツケルメツキ層3に被着せしめたはんだメツキ層4と
から構成されており、上記銀下地層2は、銀ペースト
(または銀・パラジウムペースト)とガラスペーストと
を混合してなるメタルグレーズを印刷技術等を用いてセ
ラミツク基板1にコーテイングした後、これを乾燥・焼
成することによつて得られている。また、銀下地層2中
の銀くわれを防止するための上記ニツケルメツキ層3
と、はんだ濡れ性を確保するための上記はんだメツキ層
4はいずれも、生産性を高めるため、公知のバレルメツ
キ法によつて形成されている。[Prior Art] As shown in Fig. 4 and Fig. 5 which is a sectional view taken along the line AA of the conventional chip jumper, a ceramic board 1 having a rectangular parallelepiped shape and a top surface and both end surfaces of the ceramic board 1 are provided. It is composed of a silver underlayer 2 which is held and extended in a substantially C-shape, a nickel plating layer 3 applied to the silver underlayer 2, and a solder plating layer 4 applied to the nickel plating layer 3. The silver underlayer 2 is formed by coating the ceramic substrate 1 with a metal glaze prepared by mixing a silver paste (or a silver / palladium paste) and a glass paste on the ceramic substrate 1 using a printing technique or the like, and then drying and firing the same. It has been obtained. In addition, the above nickel plating layer 3 for preventing silver cracks in the silver underlayer 2
All of the solder plating layers 4 for ensuring solder wettability are formed by a known barrel plating method in order to improve productivity.
そして、かかるチツプジヤンパは、セラミツク基板1の
底面側を下に向けてプリント配線板上の所定位置に搭載
され、デイツプはんだ法によりはんだメツキ層4を回路
パターンにはんだ付けして実装される。The chip jumper is mounted at a predetermined position on the printed wiring board with the bottom surface side of the ceramic substrate 1 facing downward, and the solder plating layer 4 is soldered to the circuit pattern by the dip soldering method.
[考案が解決しようとする課題] しかしながら、上述した従来のチツプジヤンパは、バレ
ルメツキ法ではんだメツキ層4を形成する際に、比較的
軟らかいはんだメツキ層4の天面どうしがくつつき合つ
て、第6図に示す如き不良品が発生することがあり、こ
のメツキ不良が歩留りを低下させる要因となつていた。[Problems to be Solved by the Invention] However, in the above-mentioned conventional chip jig jumper, when the solder plating layer 4 is formed by the barrel plating method, the top surfaces of the relatively soft solder plating layers 4 are struck to each other. In some cases, defective products such as those shown in (3) may occur, and this defective plating is a factor that reduces the yield.
また、実装後のチツプジヤンパのインピーダンスを低く
抑えるためには、デイツプはんだ時にはんだメツキ層4
に付着する溶融はんだが導通経路全体でひと続きになつ
ていること、つまり溶融はんだがはんだメツキ層4を抱
持するように付着することが望ましいが、上述した従来
のチツプジヤンパは、はんだメツキ層4の天面で溶融は
んだが短手方向に流れ落ちやすく、そのため溶融はんだ
がひと続きにならずにインピーダンスが高まつてしまう
虞れがあつた。Also, in order to keep the impedance of the chip jumper after mounting low, the solder plating layer 4 should be used during the dip soldering.
It is desirable that the molten solder that adheres to the whole of the conduction path be continuous, that is, the molten solder should adhere so as to hold the solder plating layer 4. On the top surface of the, the molten solder is likely to flow down in the lateral direction, so that there is a possibility that the molten solder may not be continuous and the impedance may become high.
したがつて本考案の目的とするところは、はんだメツキ
工程時の不良発生が防止できるとともにインピーダンス
特性が良好なチツプジヤンパを提供することにある。Therefore, it is an object of the present invention to provide a chip jumper which can prevent the occurrence of defects during the solder plating process and has good impedance characteristics.
[課題を解決するための手段] 上記目的を達成するために、本考案は、セラミツク基板
と、このセラミツク基板の天面および両端面を抱き込ん
で延設した銀下地層と、この銀下地層を被覆するはんだ
メツキ層とを備え、デイツプはんだ法により実装される
チツプジヤンパにおいて、上記セラミツク基板の天面側
に、上記銀下地層に沿つて延び、かつ上記はんだメツキ
層の天面よりも突出するに足る厚みを有する絶縁性の突
条を設けることによつて達成される。[Means for Solving the Problems] In order to achieve the above-mentioned object, the present invention provides a ceramic substrate, a silver underlayer extending by holding the top surface and both end surfaces of the ceramic substrate, and the silver underlayer. In a chip jumper that is equipped with a solder plating layer that covers, and is mounted by a deep soldering method, on the top surface side of the ceramic substrate, extends along the silver underlayer, and projects from the top surface of the solder plating layer. This is achieved by providing an insulating ridge having a sufficient thickness.
[作用] 上記手段によれば、予め絶縁性の突条を形成しておき、
しかる後バレルメツキ法にてはんだメツキを行うと、こ
のメツキ工程時に突条がスペーサ機能を果たしてはんだ
メツキ層の天面どうしは密着不能となるのでメツキ不良
が回避でき、また、この突条はデイツプはんだ時の溶融
はんだの流れをガイドする機能を果たすので、はんだメ
ツキ層の天面で溶融はんだがひと続きになりやすく、よ
つてインピーダンス特性の向上が図れる。[Operation] According to the above means, the insulating ridge is formed in advance,
Then, when solder plating is performed by the barrel plating method, the protrusions serve as spacers during the plating process and the top surfaces of the solder plating layers cannot adhere to each other, so that defective plating can be avoided. Since the function of guiding the flow of molten solder at that time is fulfilled, the molten solder is likely to be contiguous on the top surface of the solder plating layer, thus improving the impedance characteristics.
[実施例] 以下、本考案の一実施例を第1図ないし第3図に基づい
て説明する。[Embodiment] An embodiment of the present invention will be described below with reference to FIGS. 1 to 3.
第1図は本実施例に係るチツプジヤンパの斜視図、第2
図は第1図のB−B線断面図、第3図は第1図のC−C
線断面図であつて、第4,5図と対応する部分には同一
符号が付してある。FIG. 1 is a perspective view of the chip jumper according to this embodiment, and FIG.
The drawing is a cross-sectional view taken along the line BB in FIG. 1, and FIG. 3 is the CC taken in FIG.
In the line sectional view, the portions corresponding to those in FIGS. 4 and 5 are denoted by the same reference numerals.
第1〜3図に示すチツプジヤンパは、セラミツク基板1
を抱き込んで延設した銀下地層2の天面の両側部にそれ
ぞれ、ガラスコート材からなり銀下地層2に沿つて長手
方向に延びる突条5が付設してあり、製造工程として
は、セラミツク基板1にメタルグレーズをコーテイング
して乾燥・焼成することにより銀下地層2を形成した
後、ガラスペーストをスクリーン印刷して乾燥・焼成す
ることにより一対の突条5を形成し、しかる後、ニツケ
ルメツキ層3とはんだメツキ層4とを順次、バレルメツ
キ法にて形成する。ただし、各突条5の厚みは、ニツケ
ルメツキ層3およびはんだメツキ層4の厚みの合計より
大きくなるように設定してあり、そのため第2,3図に
明らかなように、各突条5ははんだメツキ層4の天面よ
りも突出している。The chip jumper shown in FIGS. 1 to 3 is a ceramic substrate 1.
A ridge 5 made of a glass coating material and extending in the longitudinal direction along the silver base layer 2 is attached to each of both sides of the top surface of the silver base layer 2 that holds and extends. After forming the silver underlayer 2 by coating the ceramic substrate 1 with metal glaze and drying and firing, a pair of ridges 5 are formed by screen-printing glass paste and drying and firing. The nickel plating layer 3 and the solder plating layer 4 are sequentially formed by the barrel plating method. However, the thickness of each ridge 5 is set so as to be larger than the total thickness of the nickel plating layer 3 and the solder plating layer 4, and therefore each ridge 5 is soldered as shown in FIGS. It protrudes from the top surface of the metal layer 4.
かかるチツプジヤンパは、バレル内で一括して行われる
メツキ工程時に、突条5がスペーサ機能を果たして天面
どうしの密着が不能となるので、比較的軟らかいはんだ
メツキ層4も、天面どうしがくつつき合うというメツキ
不良を発生することなく確実に形成でき、歩留りを大幅
に向上させることができる。In such a chip jig jumper, the protrusions 5 serve as spacers to prevent the top surfaces from adhering to each other during the plating process performed collectively in the barrel, so that the relatively soft solder plating layer 4 is also stuck to the top surface. It is possible to surely form without causing the defective plating, and it is possible to greatly improve the yield.
また、かかるチツプジヤンパはデイツプはんだ法により
プリント配線板上に実装されるが、このデイツプはんだ
時に突条5は溶融はんだの流れをガイドする機能を果た
し、はんだメツキ層4の天面で溶融はんだを長手方向に
導くので、はんだメツキ層4に付着する溶融はんだはお
のずから導通経路全体でひと続きとなり、インピーダン
スが低く抑えられるようになつている。The chip jumper is mounted on the printed wiring board by the deep soldering method. At the time of the deep soldering, the ridges 5 function to guide the flow of the molten solder, and the molten solder is extended on the top surface of the solder plating layer 4. Since it is guided in the direction, the molten solder that adheres to the solder plating layer 4 naturally continues for the entire conduction path, and the impedance can be suppressed low.
なお、上記実施例ではガラスコート材からなる突条を設
けているが、他の絶縁性材料にて突条を形成しても良
い。また、突条は上記実施例の如くセラミツク基板の天
面側の両側部に設けることが好ましいが、その形成位置
や形状、個数等は上記実施例に限定されるものではな
い。Although the ridges made of the glass coating material are provided in the above embodiment, the ridges may be made of other insulating material. Further, it is preferable that the ridges are provided on both side portions on the top surface side of the ceramic substrate as in the above embodiment, but the formation position, shape, number and the like are not limited to those in the above embodiment.
[考案の効果] 以上説明したように、本考案によれば、セラミツク基板
の天面側に絶縁性の突条が設けてあるので、はんだメツ
キ工程時にはんだメツキ層の天面どうしがくつつき合う
というメツキ不良が発生しなくなつて歩留りが向上し、
しかもデイツプはんだ時の溶融はんだがこの突条にガイ
ドされて導通経路全体でひと続きになりやすいことから
インピーダンスを低く抑えることができ、その結果、高
品質のチツプジヤンパを低コストにて提供することがで
きる。[Advantages of the Invention] As described above, according to the present invention, since the insulating ridges are provided on the top surface side of the ceramic substrate, the top surfaces of the solder plating layers are stuck to each other during the solder plating process. Yield is improved by eliminating defective plating.
In addition, since the molten solder during the deep soldering is guided by these ridges and tends to be continuous in the entire conduction path, the impedance can be suppressed to a low level, and as a result, it is possible to provide a high-quality chip zipper at a low cost. it can.
第1図ないし第3図は本考案の一実施例に係り、第1図
はチツプジヤンパの斜視図、第2図は第1図のB−B線
断面図、第3図は第1図のC−C線断面図、第4図は従
来例に係るチツプジヤンパの斜視図、第5図は第4図の
A−A線断面図、第6図ははんだメツキ工程時のメツキ
不良を示す説明図である。 1……セラミツク基板、2……銀下地層、3……ニツケ
ルメツキ層、4……はんだメツキ層、5……突条。1 to 3 relate to an embodiment of the present invention. FIG. 1 is a perspective view of a chip jumper, FIG. 2 is a sectional view taken along line BB of FIG. 1, and FIG. 3 is C of FIG. -C line cross-sectional view, FIG. 4 is a perspective view of a chip jumper according to a conventional example, FIG. 5 is a cross-sectional view taken along the line A-A of FIG. 4, and FIG. 6 is an explanatory view showing defective plating during a soldering process. is there. 1 ... Ceramic substrate, 2 ... Silver base layer, 3 ... Nickel plating layer, 4 ... Solder plating layer, 5 ... Ribs.
Claims (1)
天面および両端面を抱き込んで延設した銀下地層と、こ
の銀下地層を被覆するはんだメツキ層とを備え、デイツ
プはんだ法により実装されるチツプジヤンパにおいて、
上記セラミツク基板の天面側に、上記銀下地層に沿つて
延び、かつ上記はんだメツキ層の天面よりも突出するに
足る厚みを有する絶縁性の突条を設けたことを特徴とす
るチツプジヤンパ。1. A ceramic substrate, a silver underlayer extending so as to hold the top surface and both end faces of the ceramic substrate, and a solder plating layer for covering the silver underlayer. The ceramic substrate is mounted by a dip soldering method. In the Chippujiyanpa,
A chip jihamper, characterized in that an insulating ridge extending along the silver base layer and having a thickness sufficient to project from the top surface of the solder plating layer is provided on the top surface side of the ceramic substrate.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP6129390U JPH0612623Y2 (en) | 1990-06-12 | 1990-06-12 | Chippujiyanpa |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP6129390U JPH0612623Y2 (en) | 1990-06-12 | 1990-06-12 | Chippujiyanpa |
Publications (2)
Publication Number | Publication Date |
---|---|
JPH0421069U JPH0421069U (en) | 1992-02-21 |
JPH0612623Y2 true JPH0612623Y2 (en) | 1994-03-30 |
Family
ID=31589416
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP6129390U Expired - Lifetime JPH0612623Y2 (en) | 1990-06-12 | 1990-06-12 | Chippujiyanpa |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPH0612623Y2 (en) |
-
1990
- 1990-06-12 JP JP6129390U patent/JPH0612623Y2/en not_active Expired - Lifetime
Also Published As
Publication number | Publication date |
---|---|
JPH0421069U (en) | 1992-02-21 |
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Legal Events
Date | Code | Title | Description |
---|---|---|---|
EXPY | Cancellation because of completion of term |