JPH06125267A - Exclusive or circuit - Google Patents

Abstract

PURPOSE:To make the time until output is determined constant in spite of the states of two input, to shorten delay time from input to output, and to reduce the number of composing elements. CONSTITUTION:This circuit is provided with first and second input terminals A1, B1, first and second inverters 11, 12, first and second field-effect transistors 13, 14, and an output terminal X1, and the first input terminal A1 is connected to the input of the first inverter 11 and the gate electrode of the second field- effect transistor 14, and the second input terminal B1 to the input of the second inverter 12 and the drain electrode of the first field-effect transistor 13, and the output of the first inverter 11 to the gate electrode of the first field-effect transistor 13, and the output of the second inverter 12 to the drain electrode of the second field-effect transistor 14, and the source electrodes of the first field-effect transistor 13 and the second field-effect transistor 14 to the output terminal X1, respectively.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an exclusive OR circuit suitable for a semiconductor digital integrated circuit.

[0002]

2. Description of the Related Art Conventionally, as a technique in such a field,
For example, "Practical Electronic Circuit Handbook 2 P.52 C"
Q Publishing Co., Ltd. October 20, 1975 First edition issued December 1, 1978 8th edition ". FIG. 2 is a circuit diagram showing a configuration example of such a conventional exclusive OR circuit, which is configured by using a NAND circuit.

As shown in the figure, this circuit has inputs A and B
When both are "H", the output of the NAND circuit 1 becomes "L", so that the outputs of the NAND circuits 2 and 3 both become "H". Therefore, the output of the NAND circuit 4 becomes "L". Further, even when the inputs A and B are both "L", the outputs of the NAND circuits 2 and 3 are both "H",
The output of the NAND circuit 4 becomes "L".

On the other hand, when the input A is "H" and the input B is "L", the output of the NAND circuit 1 is "H", NAN.
The output of the D circuit 2 becomes "L" and the output of the NAND circuit 3 becomes "H". Therefore, the output of the NAND circuit 4 becomes "H". When the input A is "L" and the input B is "H", the output of the NAND circuit 1 is "H",
The output of the NAND circuit 2 becomes "H", and the NAND circuit 3
Output becomes "L". Therefore, the output of the NAND circuit 4 becomes "H".

As described above, this circuit operates as an exclusive OR circuit which outputs "H" to the output when the inputs A and B do not match.

[0006]

However, the exclusive OR circuit having the above configuration has the following three problems. The delay time from the determination of the inputs A and B to the output X differs depending on the state of the inputs A and B. That is, when the inputs A and B are both "L", the NAND circuit 2
And 4 or the output of the NAND circuits 3 and 4 is delayed by two gates, while the inputs A and B are both at "H", the NAND circuits 1, 2, 4 or NAN.
When the input A is “H” and the input B is “L” for the three gates of the D circuits 1, 3, and 4, the gate A of the NAND circuits 1, 2, and 4 is the input A is “L”. When the input B is "H", the output is fixed after delaying three gates of the NAND circuits 1, 3, and 4. That is, this circuit is a circuit in which the delay time from the inputs A and B to the output is mixed for two stages of gates and three stages of gates depending on the states of the inputs A and B. Therefore, when using this circuit, two types of delay must be taken into consideration when designing the timing.

The operating speed of this circuit is determined by the delay time from the input to the output, but as described in this case, the delay time is as long as three stages of gates. This is disadvantageous when an integrated circuit is made because four 2-input NAND gates are used and the number of elements is large. The present invention eliminates the three problems described above by
Regardless of the state of one input, the time until the output is determined is constant, the delay time from input to output is shortened, and the exclusive OR using a semiconductor integrated circuit with a reduced number of elements is configured. The purpose is to provide a circuit.

[0008]

In order to achieve the above object, the present invention provides an exclusive OR circuit using a semiconductor integrated circuit, which has a first input terminal, a second input terminal, and the first input terminal. A first inverter connected to the first input terminal, and a first field effect transistor in which the output of the first inverter is connected to the control electrode and the second input terminal is connected to the first electrode A second inverter connected to the second input terminal, a second inverter connected to the first electrode at the output of the second inverter, and a second electrode connected to the control electrode at the first input terminal. Field effect transistor of
The second electrode of the first field effect transistor and the second electrode
And an output terminal connected to the second electrode of the field effect transistor.

[0009]

According to the present invention, as described above, in the exclusive OR circuit using the semiconductor integrated circuit, the first and second input terminals, the first and second inverters, and the first and second inverters are provided. 2 field effect transistor and an output terminal, the first input terminal is connected to the input of the first inverter and the control electrode (gate electrode) of the second field effect transistor, and the second input terminal Is connected to the input of the second inverter and the first electrode (drain electrode or source electrode) of the first field effect transistor, and the output of the first inverter is the control electrode (gate electrode of the first field effect transistor). ), The output of the second inverter is connected to the first electrode (drain electrode or source electrode) of the second field-effect transistor, and the second electrode of each of the first and second field-effect transistors ( Source Since it is configured to connect the pole or drain electrode) to the output terminal, the delay time from input to output is constant regardless of the state of input to the input terminal, making it easy to set timing. .

Further, the delay time of the conventional circuit is 3 stages of gates, whereas the present invention is small as 2 stages, and the speed can be increased by about 1.5 times as compared with the conventional circuit. Further, when compared with the DCFL circuit using GaAs MESFETs, the number of elements is 12 elements in the conventional circuit, but the present invention requires only half as many as 6 elements, and double integration is possible.

[0011]

Embodiments of the present invention will be described in detail below with reference to the drawings. FIG. 1 is an exclusive OR circuit diagram for a semiconductor integrated circuit showing an embodiment of the present invention. Input terminal A
When both 1 (first input terminal) and input terminal B1 (second input terminal) are input "H", the output of the inverter 11 (first inverter) becomes "L". Therefore, the field effect transistor 13 (first field effect transistor)
Becomes non-conductive.

On the other hand, when the input terminal A1 is the input "H", the field effect transistor 14 (second field effect transistor) becomes conductive and the output of the inverter 12 (second inverter), that is, the input of the input terminal B1 is input. Since it is "H", "L" is output to the output terminal X1 in this case. When both the input terminals A1 and B1 are input "L", the field effect transistor 14 is non-conductive due to "L" of the input terminal A1.

On the other hand, the output of the inverter 11 is "H". Therefore, the field effect transistor 13 becomes conductive, and the input of the input terminal B1, that is, "L" is output terminal X1.
Is output to. When the input terminal A1 is the input "H" and the input terminal B1 is the input "L", the output of the inverter 11 is "L". Therefore, the field effect transistor 13
Becomes non-conductive, and the field effect transistor 14 becomes conductive due to the input "H" at the input terminal A1. Since the input terminal B1 has the input "L", the output "H" of the inverter 12 is output to the output terminal X1.

Further, when the input of the input terminal A1 is "L" and the input of the input terminal B1 is "H", the input "L" of the input terminal A1 causes the field effect transistor 14 to become non-conductive and the inverter 11 of the inverter 11 to operate. The output becomes "H". Therefore, the field effect transistor 13 becomes conductive, and the input of the input terminal B1, that is, "H" is output to the output terminal X1.

As described above, the circuit of the present invention has two circuits.
It operates as an exclusive OR circuit that outputs "H" when two inputs do not match. In the circuit of the present invention, as can be seen from the above description of the operation, the delay from the input to the output is constant in one stage of the inverter and one stage of the field effect transistor regardless of the input state of the input terminals A1 and B1. There is.

Further, the delay time is one stage of the inverter and one field effect transistor, which is smaller than that of the three stages of gates as in the conventional circuit. Further, the constituent elements are two inverters and two field effect transistors, and the number of elements is smaller than that of the conventional circuit. For example, when the conventional circuit and the circuit of the present invention are configured by a DCFL circuit using GaAs MESFETs, the number of elements of the conventional circuit is 12 and this circuit is 6
It becomes an element.

The present invention is not limited to the above embodiments, and various modifications can be made within the scope of the present invention, and these modifications are not excluded from the scope of the present invention.

[0018]

As described above in detail, according to the present invention, the delay time from the input to the output is constant without depending on the input signal level to the input terminal, so that the timing can be set. Cheap. Further, the delay time of the conventional circuit is as small as 2 stages as compared with 3 stages of gates, and the speed can be increased by about 1.5 times compared with the conventional circuit.

Further, when the number of elements is compared with the DCFL circuit using GaAs MESFET, the present invention can be integrated with 6 elements, which is half, that is, twice as many as the conventional circuit with 12 elements.

[Brief description of drawings]

FIG. 1 is an exclusive OR circuit diagram for a semiconductor integrated circuit showing an embodiment of the present invention.

FIG. 2 is a circuit diagram showing a configuration example of a conventional exclusive OR circuit.

[Explanation of symbols]

 A1, B1 input terminal X1 output terminal 11,12 inverter 13,14 field effect transistor

Claims (1)

[Claims] 1. An exclusive OR circuit formed by a semiconductor integrated circuit, comprising: (a) a first input terminal; and (b) a second input terminal.
An input terminal of (c) a first inverter connected to the first input terminal, (d) an output of the first inverter is connected to a control electrode, and the second input terminal is A first field effect transistor connected to the first electrode; (e) a second inverter connected to the second input terminal; and (f) an output of the second inverter connected to the first electrode. And a second field effect transistor having the first input terminal connected to a control electrode, and (g) a second electrode of the first field effect transistor and a second field effect transistor of the second field effect transistor. An exclusive OR circuit having an output terminal connected to an electrode.