JPH04274612A - Semiconductor latch circuit - Google Patents

Abstract

PURPOSE:To reduce the number of transistors(TRs) for an edge trigger latch composed of semiconductor devices. CONSTITUTION:A current path composed of MOSFETs 14, 15 and 17, 18 controlled by an input signal is provided on internal nodes 22, 23 in order to decide which of outputs of two inverters each composed of MOSFETs 5, 16 (6, 19) in cross connection is inverted. The output of the two inverters is an input signal to a flip-flop 24.

Description

[Detailed description of the invention]

0001

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit, and more particularly to a semiconductor latch circuit that latches data in response to a timing signal.

0002

2. Description of the Related Art A conventional semiconductor latch circuit is comprised of an inverter 45, an ANDAND 46, 47, and an ANDON 48, 49, as shown in FIG.

This semiconductor latch circuit has a function of latching the data of the input signal 41 at the rising edge of the timing signal 42 to obtain an output signal 43 and an output auxiliary signal 44.

Examples of transistor circuit diagrams of ORANDs 46, 47 and ANDORs 48, 49 in a conventional semiconductor latch circuit are shown in FIGS. 5 and 6.

As shown in FIG.
7, and outputs an output O1 for inputs A to C. Also shown in FIG. 5 are a power terminal 51 and a ground terminal 58. The logical content of this oranand is expressed by the following formula 1 in positive logic.

[0006]

[Equation 1] Also, as shown in FIG.
FET62-64 and N-channel MOSFET65-
67, and outputs an output O2 for inputs D to F. A power terminal 61 and a ground terminal 68 are also shown in FIG. The logical content of this oranand is expressed by the following formula 2 in positive logic.

[0007]

##EQU00002## In FIG. 4, orands 46 and 47 are cross-connected. Therefore, when the timing signal 42 is at a low level, the outputs of the OANDs 46 and 47 change in accordance with the level of the input signal 41, and when the timing signal 42 is at a high level, the timing signal 42 changes from a low level to a high level. The output level corresponding to the input signal 41 at the moment when

[0008] Furthermore, the ANDONORs 48 and 49 are cross-connected. Therefore, when the timing signal 42 is at a high level, the outputs 43 and 44 of the ANDORs 48 and 49 change in response to the input signal, that is, the outputs of the OANANDs 46 and 47, and when the timing signal 42 is at a low level, the timing signal changes. The output level corresponding to the instantaneous input signal (output of OAND 46 and 47) changing from high level to low level is held.

Therefore, in this circuit as a whole, only when the timing signal 42 rises, the input signal 4 at that moment is
The output signals 43 and 44 are set to the level corresponding to the input data of 1.
changes, and at other timings, the output signal 4
3 and 44 do not change and remain in the holding state. Such a circuit is generally called a positive edge trigger flip-flop or a positive edge trigger latch, and is one of the circuits frequently used in semiconductor integrated circuits.

0010

In such a conventional semiconductor latch circuit, as can be seen from FIGS. Usually consists of two elements, so a total of 26 elements are required. As described above, the conventional semiconductor latch circuit has a problem in that the large number of elements causes a deterioration in the degree of integration of the semiconductor integrated circuit.

The present invention has been made in view of the above problems, and an object of the present invention is to provide a semiconductor latch circuit that requires a small number of constituent elements and can contribute to an improvement in the degree of integration.

0012

[Means for Solving the Problems] A semiconductor latch circuit according to the present invention includes first and second complementary MOSFETs each having a first conductivity type MOSFET and a second conductivity type MOSFET connected in series. The input terminals and output terminals of the two complementary inverters are cross-connected, the source electrodes of the second conductivity type MOSFETs of the two complementary inverters are connected to a common connection point, and the common connection point and the first a second conductivity type MOS in which a timing signal is input to the gate electrode between the voltage source and the voltage source;
FETs are connected, and two MOSFETs of the first conductivity type to which the timing signal is input to the gate electrodes are respectively connected to a second voltage source and the output terminals of the two complementary inverters, and Connect the output terminals of the complementary inverter to
connected to the input terminal of the flip-flop, and connected to one or both output terminals of the complementary inverter;
A current path controlled by an input data signal is provided between the voltage source or the common connection point.

[0013]

[Operation] In the semiconductor latch circuit of the present invention, for two symmetrically constructed inverters, one inverter is provided with a current path to make it unbalanced, and the inverter that is inverted according to the input signal is selected. to achieve latching operation.

[0014]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, embodiments of the present invention will be described with reference to the accompanying drawings.

FIG. 1 shows the structure of a semiconductor latch circuit according to a first embodiment of the present invention.

P-channel and N-channel MOSFETs
An inverter consisting of MOSFETs 5 and 16 and an inverter consisting of P-channel and N-channel MOSFETs 6 and 19 are cross-connected. The sources of N-channel MOSFETs 16 and 19 are both connected to a common connection point 25. This common connection point 25 is an N-channel MOSFET 2
0 to ground G. Furthermore, a timing signal CK is input to the gate of the N-channel MOSFET 20. Output points 22 and 2 of the two said inverters
3 is a P-channel MO input to the flip-flop 24, and the timing signal CK is input to each gate.
It is connected to voltage source V by SFETs 7 and 8.

A series circuit consisting of N-channel MOSFETs 14 and 15 and N-channel MOSFETs 17 and 18
The series circuit consisting of the output point 2 of the inverter and
2 and 23 and a common connection point 25. The input signals of the respective inverters are applied to the gates of N-channel MOSFETs 14 and 17, and the input signal I is applied to the gates of N-channel MOSFETs 15 and 18, respectively.
, input supplementary signal IB are input. flip flop 24
are P-channel MOSFETs 1 to 4 and N-channel MOS
It is composed of FETs 10 to 13. P channel and N
Channel MOSFETs 9 and 21 constitute an inverter for inverting input signal I to generate complementary input signal IB.

Next, the operation of this embodiment will be explained with reference to the timing chart shown in FIG.

In the initial state, when the timing signal CK is at a low level, the P-channel MOSFETs 7 and 8 are turned on and the N-channel MOSFET 20 is turned off, so that the internal nodes 22 and 23 are at a high level.

Next, when the timing signal CK becomes high level, the P-channel MOSFETs 7 and 8 are turned off, and at the same time, the N-channel MOSFET 20 is turned on. At this time, in the series circuit of MOSFETs 14 and 15 and the series circuit of MOSFETs 17 and 18, the input signal I is at low level and the input complementary signal IB is at high level, so the series circuit of MOSFETs 17 and 18 is turned off. ing. Therefore, among internal nodes 22 and 23, internal node 23 is discharged faster. When the level of internal node 23 falls below the logic threshold of the other inverter, internal node 22 is driven high. Flip-flop 24 is inverted in response to the levels of these internal nodes 22 and 23. In this way, the input signal data at the moment of the rising edge of the timing signal CK can be latched.

That is, the main point of the present invention is to provide two symmetrical inverters with a current path in one inverter to make it unbalanced, and to select an inverter that inverts according to the input signal. be.

In this way, by configuring a completely new latch circuit, the conventional latch circuit (26 M
This makes it possible to reduce the number of MOSFETs to 21 while performing the same function as the conventional MOSFET (which required an OSFET).

FIG. 3 shows the structure of a semiconductor latch circuit according to a second embodiment of the present invention.

The feature of this embodiment is that the current path controlled by the input signal is connected to only one inverter, and the current path to the high side or the current path to the low side is turned on depending on the input signal. The point is that it is structured as follows. In FIG. 3, P-channel MOSFETs 31-34, N-channel MOSFETs 35-39, and a common connection point 40 are the parts that are different from FIG.

Since the operation is almost the same as that of the first embodiment, a detailed explanation will be omitted, but the differences in operation from the first embodiment are as follows.

In the first embodiment described above, which of the two symmetrically constructed inverters is to be inverted is determined by which inverter's current path is turned on. On the other hand, in this second embodiment, by turning on one of the two current paths provided in one of the inverters, the direction of the current flowing into the inverter is changed and the inverter to be inverted is determined.

The semiconductor latch circuit of this second embodiment is as follows:
Since it can be configured with 19 MOSFETs, the number of transistors can be significantly reduced compared to the conventional latch circuit which required 26 MOSFETs.

Furthermore, in FIG. 3, MOSFET 33,
34 is omitted, and when the input signal I is low level, that is,
The sizes of the two inverters are made unbalanced in advance so that the node 23 is at a low level when the current path consisting of MOSFETs 35 and 36 is off, and when the input signal I is at a high level, the node 23 is at a low level. 2
It is also possible to obtain the same effect as in the case of FIG. 3 by determining the size of the current path so that 2 is inverted to a low level. At this time, the number of MOSFETs is 17, and the number of transistors can be further reduced.

[0029]

[Effects of the Invention] As described above, according to the present invention, with a completely new configuration, it is possible to reduce the number of MOSFETs while performing the same functions as conventional ones, and the number of constituent elements is small. Therefore, it is possible to provide a semiconductor latch circuit that is easy to use and can also contribute to an improvement in the degree of integration.

[Brief explanation of the drawing]

FIG. 1 is a circuit configuration diagram showing the configuration of a first embodiment of the present invention.

FIG. 2 is a timing chart diagram for explaining the operation of the embodiment in FIG. 1;

FIG. 3 is a circuit configuration diagram showing the configuration of a second embodiment of the present invention.

FIG. 4 is a circuit configuration diagram showing an example of the configuration of a conventional latch circuit.

FIG. 5 is a circuit configuration diagram showing in detail a part (ORAND) of a conventional latch circuit.

FIG. 6 is a circuit configuration diagram showing in detail another part (ANDOR) of the conventional latch circuit.

[Explanation of symbols]

1-9, 31-34; P channel MOSFET10-2
1, 35-39; N-channel MOSFET 24; Flip-flop V; Voltage source O; Output signal OB; Output auxiliary signal I; Input signal CK; Timing signal

Claims (2)

[Claims] 1. Each input terminal and each output terminal of first and second complementary inverters are each formed by connecting a first conductivity type MOSFET and a second conductivity type MOSFET in series, respectively. cross-connecting, each source electrode of the second conductivity type MOSFET of the two complementary inverters is connected to a common connection point, and a timing signal is applied to the gate electrode between the common connection point and the first voltage source. The input MOSFETs of the second conductivity type are connected, and the two MOSFETs of the first conductivity type whose gate electrodes are input with the timing signal are connected to a second voltage source and the output terminals of the two complementary inverters. and connecting the output terminals of the two complementary inverters to the input terminal of the flip-flop,
A semiconductor latch circuit characterized in that a current path controlled by an input data signal is provided between one or both output terminals of the complementary inverter and the second voltage source or the common connection point. 2. The current path is a series circuit of two MOSFETs of either a first conductivity type or a second conductivity type, and an input data signal and an input signal are connected to the gate electrode of one MOSFET of the series circuit. 2. The semiconductor latch circuit according to claim 1, wherein one of the complementary data signals is connected to the gate electrode of the other MOSFET of the series circuit, and one input signal of the complementary inverter is commonly input to the gate electrode of the other MOSFET of the series circuit. .