JPH06120363A - Semiconductor device holding package - Google Patents

Semiconductor device holding package

Info

Publication number
JPH06120363A
JPH06120363A JP4268470A JP26847092A JPH06120363A JP H06120363 A JPH06120363 A JP H06120363A JP 4268470 A JP4268470 A JP 4268470A JP 26847092 A JP26847092 A JP 26847092A JP H06120363 A JPH06120363 A JP H06120363A
Authority
JP
Japan
Prior art keywords
metal
insulating substrate
semiconductor element
metal frame
sintered body
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP4268470A
Other languages
Japanese (ja)
Other versions
JP2783735B2 (en
Inventor
Tetsuo Hirakawa
哲生 平川
Ryuichi Imura
隆一 井村
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Kyocera Corp
Original Assignee
Kyocera Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Kyocera Corp filed Critical Kyocera Corp
Priority to JP4268470A priority Critical patent/JP2783735B2/en
Publication of JPH06120363A publication Critical patent/JPH06120363A/en
Application granted granted Critical
Publication of JP2783735B2 publication Critical patent/JP2783735B2/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805Shape
    • H01L2224/4809Loop shape
    • H01L2224/48091Arched
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/161Cap
    • H01L2924/1615Shape
    • H01L2924/16195Flat cap [not enclosing an internal cavity]

Landscapes

  • Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)
  • Lead Frames For Integrated Circuits (AREA)

Abstract

PURPOSE:To make a semiconductor device operate normally and stably over a long period of time by brazing a metal frame firmly to a metallized metal layer attached to an insulating substrate made of an aluminum nitride sintered body or glass ceramic sintered body, sealing the container hermetically completely, and making it hold the semiconductor device inside. CONSTITUTION:This semiconductor device holding package is one made by brazing a metal frame 8 to a metallized layer 7 provided on the surface of an insulating substrate 1, and fitting a metal lid 2 to the metal frame 8 to hold a semiconductor device 3 inside hermetically. And, the insulating substrate 1 is made of an aluminum nitride sintered body or glass ceramic sintered body, and the Vickers hardness (Hv) of soldering material 9 for soldering the metal frame 8 to the metallized layer 7 satisfies Hv <=40.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【産業上の利用分野】本発明は半導体素子を収容するた
めの半導体素子収納用パッケージの改良に関するもので
ある。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an improvement of a semiconductor element housing package for housing a semiconductor element.

【0002】[0002]

【従来の技術】従来、半導体素子を収容するための半導
体素子収納用パッケージは、通常、酸化アルミニウム質
焼結体等の電気絶縁材料から成り、その上面の略中央部
に半導体素子を収容するための凹部及び該凹部周辺から
周縁部にかけて導出されたタングステン、モリブデン、
マンガン等の高融点金属粉末から成るメタライズ配線層
を有する絶縁基体と、半導体素子を外部電気回路に電気
的に接続するために前記メタライズ配線層に銀ロウ等の
ロウ材を介してロウ付けされた外部リード端子と、コバ
ール金属や42アロイ等の金属から成る蓋体とから構成
されており、絶縁基体の凹部底面に半導体素子を取着固
定するとともに該半導体素子の各電極をボンディングワ
イヤを介してメタライズ配線層に接続し、しかる後、絶
縁基体上面に金属製蓋体を溶接し、絶縁基体と金属製蓋
体とから成る容器内部に半導体素子を気密に封止するこ
とによって最終製品としての半導体装置となる。
2. Description of the Related Art Conventionally, a semiconductor element housing package for housing a semiconductor element is usually made of an electrically insulating material such as an aluminum oxide sintered body, and the semiconductor element is housed in a substantially central portion of its upper surface. Of the concave portion and tungsten, molybdenum led from the periphery of the concave portion to the peripheral portion,
An insulating substrate having a metallized wiring layer made of a refractory metal powder such as manganese was brazed to the metallized wiring layer via a brazing material such as silver brazing in order to electrically connect the semiconductor element to an external electric circuit. An external lead terminal and a lid body made of metal such as Kovar metal or 42 alloy are used. The semiconductor element is attached and fixed to the bottom surface of the recess of the insulating base, and each electrode of the semiconductor element is bonded via a bonding wire. After connecting to the metallized wiring layer, a metal lid is then welded to the upper surface of the insulating base, and the semiconductor element is hermetically sealed inside the container consisting of the insulating base and the metal lid to form a semiconductor as a final product. It becomes a device.

【0003】尚、前記従来の半導体素子収納用パッケー
ジは通常、絶縁基体の上面にコバール金属や42アロイ
等の金属材料から成る金属枠体を予めロウ付けしておく
とともに該金属枠体に金属製蓋体をシームウエルド法等
により溶接させることによって金属製蓋体は絶縁基体の
上面に取着され、これによって絶縁基体と金属製蓋体と
から成る容器が気密に封止される。
In the conventional package for accommodating semiconductor elements, a metal frame made of a metal material such as Kovar metal or 42 alloy is usually brazed on the upper surface of an insulating base, and the metal frame is made of metal. By welding the lid by the seam weld method or the like, the metallic lid is attached to the upper surface of the insulating base, thereby hermetically sealing the container including the insulating base and the metallic lid.

【0004】また前記絶縁基体への金属枠体のロウ付け
はまず絶縁基体の上面に金属枠体より若干大きめの面積
にタングステン、モリブデン、マンガン等の高融点金属
粉末から成るメタライズ金属層を従来周知のスクリーン
印刷法等の厚膜手法を採用することによって被着形成
し、次に前記メタライズ金属層上に銀ロウ等のロウ材と
金属枠体とを順次載置させ、最後に前記ロウ材に約80
0℃の温度を印加し、ロウ材を加熱溶融させることによ
って行われる。
For brazing a metal frame to the insulating base, a metallized metal layer made of a refractory metal powder such as tungsten, molybdenum, or manganese is formed on the upper surface of the insulating base in a slightly larger area than the metal frame. The film is formed by applying a thick film technique such as the screen printing method, and then a brazing material such as a silver brazing material and a metal frame are sequentially placed on the metallized metal layer, and finally the brazing material is formed. About 80
It is performed by applying a temperature of 0 ° C. and heating and melting the brazing material.

【0005】しかしながら、近時、半導体素子は高密度
化、高速化が急激に進み、該半導体素子を上記従来の半
導体素子収納用パッケージに収容した場合、以下に述べ
る欠点を有したものとなる。
However, in recent years, the density and speed of semiconductor devices have rapidly increased, and when the semiconductor devices are housed in the conventional semiconductor device housing package described above, the semiconductor devices have the following drawbacks.

【0006】即ち、 (1) 半導体素子を構成するシリコンと半導体素子収納用
パッケージの絶縁基体を構成する酸化アルミニウム質焼
結体の熱膨張係数がそれぞれ3.0 〜3.5 ×10-6/℃、7.5
×10-6/ ℃であり、大きく相違することから両者に半
導体素子を作動させた際等に発生する熱が印加されると
両者間に大きな熱応力が発生し、該熱応力によって半導
体素子が破損したり、半導体素子が絶縁基体より剥離し
て半導体装置としての機能を喪失させてしまう。
(1) The coefficient of thermal expansion of silicon constituting a semiconductor element and the coefficient of thermal expansion of an aluminum oxide sintered body constituting an insulating substrate of a package for accommodating a semiconductor element are 3.0 to 3.5 × 10 −6 / ° C. and 7.5, respectively.
Since it is × 10 -6 / ° C., it is greatly different, and when heat generated when the semiconductor element is operated is applied to both, a large thermal stress occurs between the two, and the semiconductor element is caused by the thermal stress. It may be damaged or the semiconductor element may be peeled off from the insulating substrate and the function as a semiconductor device may be lost.

【0007】(2) 半導体素子収納用パッケージの絶縁基
体を構成する酸化アルミニウム質焼結体の熱伝導率が約
20W/m ・K と低いため、絶縁基体が半導体素子の作動時
に発生する熱を大気中に良好に放散させることができ
ず、半導体素子が該半導体素子の発する熱によって高温
となり、半導体素子に熱破壊を起こさせたり、特性に熱
変化を与え、誤動作を生じさせたりする。
(2) The thermal conductivity of the aluminum oxide sintered body that constitutes the insulating substrate of the semiconductor element housing package is about
Since it is as low as 20 W / mK, the insulating substrate cannot dissipate the heat generated during the operation of the semiconductor element into the atmosphere well, and the semiconductor element becomes high temperature due to the heat generated by the semiconductor element, and the semiconductor element is not heated. It may cause damage or change the characteristics due to heat, resulting in malfunction.

【0008】(3) 半導体素子収納用パッケージの絶縁基
体を構成する酸化アルミニウム質焼結体はその誘電率が
9 〜10( 室温1MHz) と高いため、絶縁基体に設けたメタ
ライズ配線層を伝わる電気信号の伝播速度が遅く、その
ため信号の高速伝播を要求する半導体素子はその収容が
不可となる。
(3) The dielectric constant of the aluminum oxide sintered body that constitutes the insulating substrate of the package for storing semiconductor elements is
Since it is as high as 9 to 10 (room temperature 1 MHz), the propagation speed of the electric signal transmitted through the metallized wiring layer provided on the insulating substrate is slow, and therefore the semiconductor element that requires high-speed signal propagation cannot be accommodated.

【0009】等の欠点を有していた。It has the drawbacks such as

【0010】そこで上記欠点を解消するために半導体素
子収納用パッケージの絶縁基体を熱伝導率が半導体素子
を構成するシリコンと近似し、低誘電率で、且つ熱伝導
率が高い窒化アルミニウム質焼結体やガラス成分を多量
に含有したガラスセラミックス焼結体で形成することが
検討されている。
Therefore, in order to solve the above-mentioned drawbacks, the insulating base of the package for housing a semiconductor element is made of aluminum nitride having a low thermal conductivity and a high thermal conductivity similar to that of silicon constituting the semiconductor element. It has been studied to form a body or a glass ceramics sintered body containing a large amount of glass components.

【0011】[0011]

【発明が解決しようとする課題】しかしながら、この窒
化アルミニウム質焼結体やガラスセラミックス焼結体を
絶縁基体に使用した半導体素子収納用パッケージは、窒
化アルミニウム質焼結体やガラスセラミックス焼結体の
熱膨張係数が5.0 ×10-6/ ℃以下であるのに対し、金属
枠体を構成するコバール金属や42アロイ等の熱膨張係数
が7.0 ×10-6/ ℃程度であり、両者相違するため、絶縁
基体に被着させたメタライズ金属層に金属枠体をロウ付
けする際、絶縁基体のメタライズ金属層と金属枠体との
接合部に絶縁基体と金属枠体の熱膨張係数の相違に起因
する大きな熱応力が内在し、その結果、金属枠体に金属
製蓋体を溶接により取着する時、金属枠体に外力が印加
されると該外力が前記内在応力と相俊って大きくなり、
金属枠体を絶縁基体より剥離させて容器の気密封止を破
り、内部に収容する半導体素子を長期間にわたり正常、
且つ安定に作動させることができないという欠点を有し
ていた。
However, a package for storing a semiconductor element, which uses the aluminum nitride sintered body or the glass ceramics sintered body as an insulating substrate, is not suitable for the aluminum nitride sintered body or the glass ceramics sintered body. The coefficient of thermal expansion is 5.0 × 10 -6 / ° C or less, whereas the coefficient of thermal expansion of Kovar metal or 42 alloy, which composes the metal frame, is about 7.0 × 10 -6 / ° C, and both are different. , When the metal frame is brazed to the metallized metal layer adhered to the insulating substrate, due to the difference in thermal expansion coefficient between the insulating substrate and the metal frame at the joint between the metallized metal layer of the insulating substrate and the metal frame. There is a large internal thermal stress, and as a result, when a metal lid is attached to the metal frame by welding, if an external force is applied to the metal frame, the external force will increase in proportion to the internal stress. ,
The metal frame is peeled off from the insulating base to break the hermetic seal of the container, and the semiconductor element housed inside is kept normal for a long period of time.
In addition, it has a drawback that it cannot be operated stably.

【0012】[0012]

【発明の目的】本発明は上記欠点に鑑み案出されたもの
で、その目的は窒化アルミニウム質焼結体もしくはガラ
スセラミックス焼結体から成る絶縁基体に被着させたメ
タライズ金属層に金属枠体を強固にロウ付けし、容器の
気密封止を完全として内部に収容する半導体素子を長期
間にわたり正常、且つ安定に作動させることができる半
導体素子収納用パッケージを提供することにある。
SUMMARY OF THE INVENTION The present invention has been devised in view of the above drawbacks, and its object is to provide a metal frame on a metallized metal layer adhered to an insulating substrate made of an aluminum nitride sintered body or a glass ceramic sintered body. It is an object of the present invention to provide a package for storing a semiconductor element in which a semiconductor element which is tightly brazed and the container is completely hermetically sealed and can be normally and stably operated for a long period of time.

【0013】[0013]

【課題を解決するための手段】本発明は絶縁基体の表面
に設けたメタライズ金属層に金属枠体をロウ付けすると
ともに該金属枠体に金属製蓋体を取着し、内部に半導体
素子を気密に収容するようになした半導体素子収納用パ
ッケージであって、前記絶縁基体を窒化アルミニウム質
焼結体もしくはガラスセラミックス焼結体で形成し、且
つメタライズ金属層に金属枠体をロウ付けするロウ材の
ビッカース硬度(Hv)をHv≦40としたことを特徴
とするものである。
According to the present invention, a metal frame is brazed to a metallized metal layer provided on the surface of an insulating substrate, a metal lid is attached to the metal frame, and a semiconductor element is provided inside. A package for housing a semiconductor element, which is hermetically housed, wherein the insulating substrate is formed of an aluminum nitride sintered body or a glass ceramic sintered body, and a metal frame is brazed to a metallized metal layer. The Vickers hardness (Hv) of the material is Hv ≦ 40.

【0014】[0014]

【作用】本発明の半導体素子収納用パッケージによれ
ば、窒化アルミニウム質焼結体もしくはガラスセラミッ
クス焼結体から成る絶縁基体と金属枠体の熱膨張係数の
相違により発生する熱応力は両者の間に介在するロウ材
で吸収され、これによって絶縁基体に被着させたメタラ
イズ金属層に金属枠体を強固にロウ付けすることが可能
となる。
According to the package for accommodating semiconductor elements of the present invention, the thermal stress generated by the difference in the thermal expansion coefficient between the insulating base made of the aluminum nitride sintered body or the glass ceramic sintered body and the metal frame is between the two. It is absorbed by the brazing material interposed between the metal base and the metallized metal layer adhered to the insulating substrate, so that the metal frame can be firmly brazed.

【0015】[0015]

【実施例】次に本発明を添付図面に基づき詳細に説明す
る。図1 及び図2 は本発明の半導体素子収納用パッケー
ジの一実施例を示し、図中、1 は絶縁基体、2 は金属製
蓋体である。この絶縁基体1 と金属製蓋体2 とで半導体
素子3 を収容する容器が構成される。
The present invention will now be described in detail with reference to the accompanying drawings. 1 and 2 show an embodiment of a package for housing a semiconductor element of the present invention, in which 1 is an insulating base and 2 is a metallic lid. The insulating base 1 and the metallic lid 2 constitute a container that houses the semiconductor element 3.

【0016】前記絶縁基体1 は窒化アルミニウム質焼結
体やガラスセラミックス焼結体から成り、その上面中央
部に半導体素子3 を収容するための空所を形成する凹部
1aが設けてあり、該凹部1a底面には半導体素子3 がロウ
材、ガラス、樹脂等の接着剤を介して取着される。
The insulating base 1 is made of an aluminum nitride sintered body or a glass ceramics sintered body, and has a concave portion for forming a space for accommodating the semiconductor element 3 in the central portion of the upper surface thereof.
1a is provided, and the semiconductor element 3 is attached to the bottom surface of the recess 1a via an adhesive such as a brazing material, glass, or resin.

【0017】前記絶縁基体1 を構成する窒化アルミニウ
ム質焼結体やガラスセラミックス焼結体はその熱膨張係
数が5.0 ×10-6/ ℃以下であり、半導体素子3 を構成す
るシリコンの熱膨張係数(3.0〜3.5 ×10-6/ ℃) に近似
することから絶縁基体1 の凹部1a底面に半導体素子3 を
取着した後、絶縁基体1 と半導体素子3 の間に、例えば
半導体素子3 の作動時に発生する熱が印加されたとして
も両者間には大きな熱応力が発生することはなく、該熱
応力によって半導体素子3 を破損させたり、半導体素子
3 を絶縁基体1 より剥離させて半導体装置としての機能
を喪失させることは皆無となる。
The thermal expansion coefficient of the aluminum nitride-based sintered body or the glass-ceramics sintered body forming the insulating substrate 1 is 5.0 × 10 −6 / ° C. or less, and the thermal expansion coefficient of silicon forming the semiconductor element 3 is Since it is close to (3.0 to 3.5 × 10 -6 / ° C), after mounting the semiconductor element 3 on the bottom surface of the concave portion 1a of the insulating substrate 1, between the insulating substrate 1 and the semiconductor element 3, for example, the operation of the semiconductor element 3 Even if heat generated at times is applied, a large thermal stress does not occur between them, and the thermal stress may damage the semiconductor element 3 or cause the semiconductor element 3 to be damaged.
There is no loss of the function as a semiconductor device by peeling 3 from the insulating substrate 1.

【0018】また前記絶縁基体1 は凹部1a底面に取着さ
れる半導体素子3 が多量の熱を発生するタイプのもので
あれば、熱伝導率が80W/m ・K 以上の窒化アルミニウム
質焼結体で形成しておけば絶縁基体1 が半導体素子3 の
発する熱を大気中に良好に放散し、半導体素子3 を常に
低温として長期間にわたり正常に作動させることが可能
となる。
If the semiconductor element 3 attached to the bottom surface of the recess 1a is of a type that generates a large amount of heat, the insulating substrate 1 is an aluminum nitride sintered material having a thermal conductivity of 80 W / m.K or more. If formed in a body, the insulating substrate 1 can satisfactorily dissipate the heat generated by the semiconductor element 3 into the atmosphere, and the semiconductor element 3 can be normally operated at a low temperature for a long period of time to operate normally.

【0019】尚、前記絶縁基体1 は例えば、窒化アルミ
ニウム質焼結体から成る場合、主原料としての窒化アル
ミニウム(AlN) に焼結助剤としてのイットリアやカルシ
ア及び適当な有機溶剤、溶媒を添加混合して泥漿状とな
すとともにこれを従来周知のドクターブレード法やカレ
ンダーロール法を採用することによってグリーンシート
( 生シート) を形成し、しかる後、前記グリーンシート
に適当な打ち抜き加工を施すとともに複数枚積層し、高
温( 約1800℃) で焼成することによって製作される。
When the insulating substrate 1 is made of, for example, an aluminum nitride sintered body, yttria or calcia as a sintering aid and an appropriate organic solvent or solvent are added to aluminum nitride (AlN) as a main raw material. By mixing them to form a sludge and adopting the conventionally known doctor blade method and calender roll method, the green sheet
(Green sheet) is formed, and thereafter, the green sheet is appropriately punched, laminated with a plurality of sheets, and fired at a high temperature (about 1800 ° C.).

【0020】また前記絶縁基体1 には凹部1a周辺から外
周縁にかけて複数個のメタライズ配線層4 が被着形成さ
れており、該メタライズ配線層4 の凹部1a周辺部には半
導体素子3 の電極がボンディングワイヤ5 を介して電気
的に接続され、また絶縁基体1 の外周縁に導出する部位
には外部リード端子6 がロウ材を介してロウ付けされ
る。
A plurality of metallized wiring layers 4 are formed on the insulating substrate 1 from the periphery of the recess 1a to the outer peripheral edge thereof, and the electrodes of the semiconductor element 3 are formed on the periphery of the recess 1a of the metallized wiring layer 4. An external lead terminal 6 is brazed via a brazing material to a portion that is electrically connected via a bonding wire 5 and is led to the outer peripheral edge of the insulating base 1.

【0021】前記絶縁基体1 に設けたメタライズ配線層
4 はタングステン、モリブデン、マンガン等の金属粉末
から成り、該メタライズ配線層4 は外部電気回路に接続
される外部リード端子6 に半導体素子3 の各電極を電気
的に導通させる作用を為す。
Metallized wiring layer provided on the insulating substrate 1
4 is made of metal powder such as tungsten, molybdenum and manganese, and the metallized wiring layer 4 has a function of electrically connecting each electrode of the semiconductor element 3 to an external lead terminal 6 connected to an external electric circuit.

【0022】前記メタライズ配線層4 は例えば、タング
ステン等の金属粉末に有機溶剤、溶媒を添加混合して得
た金属ペーストを絶縁基体1 となるグリーンシートに予
め従来周知のスクリーン印刷法により所定パターンに印
刷塗布しておくことによって絶縁基体1 の所定位置に被
着形成される。
For the metallized wiring layer 4, for example, a metal paste obtained by adding and mixing an organic solvent and a solvent to a metal powder such as tungsten is formed in a predetermined pattern in advance on a green sheet to be the insulating substrate 1 by a conventionally known screen printing method. By printing and coating, the insulating substrate 1 is adhered and formed at a predetermined position.

【0023】尚、前記メタライズ配線層4 はその露出す
る外表面にニッケル、金等の耐蝕性に優れ、且つロウ材
と濡れ性の良い金属をメッキ法により1.0 乃至20.0μm
の厚みに層着させておくとメタライズ配線層4 の酸化腐
食を有効に防止することができるとともにメタライズ配
線層4 とボンディングワイヤ5 及び外部リード端子6と
のロウ付け接合を強固なものとなすことができる。従っ
て、前記メタライズ配線層4 の表面にはニッケル、金等
の耐蝕性に優れ、且つロウ材と濡れ性の良い金属をメッ
キ法により1.0 乃至20.0μm の厚みに層着させておくこ
とが好ましい。
The metallized wiring layer 4 is formed on its exposed outer surface with a metal such as nickel and gold which has excellent corrosion resistance and has a good wettability with the brazing material by 1.0 to 20.0 μm by plating.
The thickness of the metallized wiring layer 4 can effectively prevent oxidative corrosion of the metallized wiring layer 4, and the brazed joint between the metallized wiring layer 4 and the bonding wires 5 and the external lead terminals 6 can be strengthened. You can Therefore, it is preferable to deposit a metal such as nickel or gold having excellent corrosion resistance and good wettability with the brazing material to a thickness of 1.0 to 20.0 μm on the surface of the metallized wiring layer 4 by a plating method.

【0024】また前記絶縁基体1 に設けたメタライズ配
線層4 は、絶縁基体1 を誘電率が6.3 程度と低いガラス
セラミックス焼結体で形成しておけばメタライズ配線層
4 を伝わる電気信号の伝播速度が極めて速いものとな
り、絶縁基体1 の凹部1a底面に取着される半導体素子3
が高速で電気信号の出し入れをする高速駆動タイプのも
のであれば、メタライズ配線層4 が被着形成される絶縁
基体1 は誘電率の低いガラスセラミックス焼結体で形成
しておくことが好ましい。
The metallized wiring layer 4 provided on the insulating base 1 is a metallized wiring layer if the insulating base 1 is formed of a glass ceramic sintered body having a low dielectric constant of about 6.3.
The propagation speed of the electric signal transmitted through 4 becomes extremely high, and the semiconductor element 3 attached to the bottom surface of the recess 1a of the insulating substrate 1
In the case of a high-speed drive type in which electric signals are input and output at high speed, it is preferable that the insulating substrate 1 on which the metallized wiring layer 4 is formed is formed of a glass ceramic sintered body having a low dielectric constant.

【0025】更に前記絶縁基体1 に被着したメタライズ
配線層4 にロウ付けされる外部リード端子6 はコバール
金属( 鉄ーニッケルーコバルト合金) や42アロイ( 鉄ー
ニッケル合金) 等の金属材料から成り、半導体素子3 の
各電極を外部電気回路に電気的に接続する作用を為す。
Further, the external lead terminals 6 brazed to the metallized wiring layer 4 deposited on the insulating substrate 1 are made of a metal material such as Kovar metal (iron-nickel-cobalt alloy) or 42 alloy (iron-nickel alloy). , To electrically connect each electrode of the semiconductor element 3 to an external electric circuit.

【0026】前記外部リード端子6 はコバール金属等の
インゴット( 塊) を圧延加工法や打ち抜き加工法等、従
来周知の金属加工法を採用し、所定の棒状に形成するこ
とによって製作される。
The external lead terminal 6 is manufactured by forming an ingot (lump) of Kovar metal or the like into a predetermined rod shape by using a conventionally known metal processing method such as a rolling processing method or a punching processing method.

【0027】また前記外部リード端子6 と絶縁基体1 に
設けたメタライズ配線層4 とをロウ付けするロウ材は例
えば、金ー銀合金等のビッカース硬度(Hv)がHv≦40の軟
質なものが好適に使用され、ロウ材としてビッカース硬
度(Hv)がHv≦40のものを使用すると絶縁基体1 に設けた
メタライズ配線層4 に外部リード端子6 をロウ付け取着
する際、絶縁基体1 と外部リード端子6 との熱膨張係数
が相違し、両者間に大きな熱応力を発生したとしても該
応力はロウ材を変形させることによって吸収され、両者
のロウ付け部に大きな応力が内在するのが皆無となって
外部リード端子6 をメタライズ配線層4 に強固に取着さ
せることができる。従って、絶縁基体1のメタライズ配
線層4 に外部リード端子6 をロウ付けするロウ材として
は金ー銀合金等のビッカース硬度(Hv)がHv≦40の軟質な
ものを使用することが好ましい。
The brazing material for brazing the external lead terminal 6 and the metallized wiring layer 4 provided on the insulating substrate 1 is, for example, a soft material having a Vickers hardness (Hv) of Hv ≦ 40 such as a gold-silver alloy. When the Vickers hardness (Hv) is Hv ≤ 40 as the brazing material, it is suitable to braze and attach the external lead terminal 6 to the metallized wiring layer 4 provided on the insulating substrate 1. Even if the thermal expansion coefficient differs from that of the lead terminal 6 and a large thermal stress is generated between the two, the stress is absorbed by deforming the brazing material, and there is no large internal stress in the brazing part of both. Thus, the external lead terminal 6 can be firmly attached to the metallized wiring layer 4. Therefore, as the brazing material for brazing the external lead terminals 6 to the metallized wiring layer 4 of the insulating substrate 1, it is preferable to use a soft material having a Vickers hardness (Hv) of Hv ≦ 40 such as gold-silver alloy.

【0028】また一方、前記絶縁基体1 はその上面にメ
タライズ金属層7 が被着形成されており、該メタライズ
金属層7 には金属枠体8 がロウ材9 を介してロウ付けさ
れている。
On the other hand, a metallized metal layer 7 is deposited on the upper surface of the insulating substrate 1, and a metal frame 8 is brazed to the metallized metal layer 7 via a brazing material 9.

【0029】前記絶縁基体1 上面のメタライズ金属層7
はタングステン、モリブデン、マンガン等の高融点金属
粉末から成り、該メタライズ金属層7 は金属枠体8 を絶
縁基体1 にロウ付けする際の下地金属層として作用す
る。
Metallized metal layer 7 on the upper surface of the insulating substrate 1
Is made of a refractory metal powder such as tungsten, molybdenum, or manganese, and the metallized metal layer 7 acts as a base metal layer when the metal frame 8 is brazed to the insulating base 1.

【0030】前記メタライズ金属層7 はタングステン等
の金属粉末に適当な有機溶剤、溶媒を添加混合して得た
金属ペーストを絶縁基体1 と成るグリーンシート上に従
来周知のスリーン印刷法等により予め所定厚みに印刷塗
布しておくことによって絶縁基体1 の上面に被着形成さ
れる。
The metallized metal layer 7 is preliminarily predetermined by a well-known screen printing method or the like on a green sheet serving as the insulating substrate 1 with a metal paste obtained by adding and mixing an appropriate organic solvent and a solvent to a metal powder such as tungsten. It is adhered and formed on the upper surface of the insulating substrate 1 by printing and coating it to a thickness.

【0031】また前記メタライズ金属層7 にロウ材9 を
介してロウ付けされる金属枠体8 はコバール金属や42
アロイ等の金属材料から成る金属製蓋体2 を絶縁基体1
に取着する際の下地金属部材として作用し、金属枠体8
に金属製蓋体2 をシームウエド法等により溶接すること
によって金属製蓋体2 は絶縁基体1 上に取着される。
The metal frame 8 brazed to the metallized metal layer 7 via the brazing material 9 is made of Kovar metal or 42
Insulate base 1 with metal lid 2 made of metal material such as alloy
Acts as a base metal member when attaching to the metal frame 8
The metallic lid body 2 is attached to the insulating base 1 by welding the metallic lid body 2 to it by a seam wet method or the like.

【0032】前記金属枠体8 はコバール金属や42アロイ
等の金属材料から成り、該コバール金属等のインゴット
( 塊) を圧延加工法や打ち抜き加工法等、従来周知の金
属加工法を採用することによって所定の枠状に形成され
る。
The metal frame 8 is made of a metal material such as Kovar metal or 42 alloy, and the ingot of Kovar metal or the like is used.
The (lump) is formed into a predetermined frame shape by adopting a conventionally known metal processing method such as a rolling processing method or a punching processing method.

【0033】前記金属枠体8 はまた絶縁基体1 に設けた
メタライズ金属層7 にロウ材9 を介してロウ付けされ、
該ロウ材9 としては例えば、金ー銀合金等のビッカース
硬度(Hv)がHv≦40の軟質なものが使用される。
The metal frame body 8 is also brazed to the metallized metal layer 7 provided on the insulating substrate 1 via the brazing material 9.
As the brazing material 9, for example, a soft material such as a gold-silver alloy having a Vickers hardness (Hv) of Hv ≦ 40 is used.

【0034】前記ロウ材9 はそのビッカース硬度(Hv)が
Hv≦40で軟質なものであることから絶縁基体1 に設けた
メタライズ金属層7 に金属枠体8 をロウ付け取着する
際、絶縁基体1 と金属枠体8 との熱膨張係数が相違し、
両者間に大きな熱応力を発生したとしても該応力はロウ
材9 を変形させることによって吸収され、両者のロウ付
け部に大きな応力が内在することは一切ない。従って、
ロウ付け後、金属枠体8に外力が印加されたとしても該
外力がロウ付け部に内在する応力と相俊って大となり、
金属枠体8 を剥離させることもない。
The brazing material 9 has a Vickers hardness (Hv)
Since Hv ≤ 40 is soft, when the metal frame 8 is brazed and attached to the metallized metal layer 7 provided on the insulating substrate 1, the insulating substrate 1 and the metal frame 8 have different thermal expansion coefficients. ,
Even if a large thermal stress is generated between the two, the stress is absorbed by deforming the brazing material 9, and no large stress is present in the brazing portion of both. Therefore,
After brazing, even if an external force is applied to the metal frame body 8, the external force becomes large in proportion to the stress inherent in the brazing portion,
The metal frame 8 is not peeled off either.

【0035】尚、前記ロウ材9 はそのビッカース硬度(H
v)がHv≧40となると絶縁基体1 に設けたメタライズ金属
層7 に金属枠体8 をロウ付け取着する際、絶縁基体1 と
金属枠体8 との接合部に大きな応力が内在し、該内在応
力によって金属枠体8 が絶縁基体1 より剥離し易くな
る。従って、前記ロウ材9 はそのビッカース硬度(Hv)が
Hv≦40の軟質なものに特定される。
The brazing material 9 has a Vickers hardness (H
When v) is Hv ≧ 40, when the metal frame body 8 is brazed and attached to the metallized metal layer 7 provided on the insulating base body 1, large stress is internally present in the joint portion between the insulating base body 1 and the metal frame body 8, Due to the internal stress, the metal frame body 8 is easily separated from the insulating substrate 1. Therefore, the brazing material 9 has a Vickers hardness (Hv) of
Specified as soft with Hv ≤ 40.

【0036】かくして上述の半導体素子収納用パッケー
ジによれば絶縁基体1 の凹部1a底面に半導体素子3 をロ
ウ材、ガラス、樹脂等の接着剤を介して取着するととも
に該半導体素子3 の各電極をボンディングワイヤ5 を介
してメタライズ配線層4 に電気的に接続し、しかる後、
絶縁基体1 の上面にロウ付けした金属枠体9 に金属製蓋
体2 をシームウエルド法等により溶接し、絶縁基体1 と
金属製蓋体2 とから成る容器内部に半導体素子3 を気密
に封止することによって最終製品としての半導体装置と
なる。
Thus, according to the above-mentioned package for accommodating semiconductor elements, the semiconductor element 3 is attached to the bottom surface of the recess 1a of the insulating substrate 1 via an adhesive such as a brazing material, glass or resin, and each electrode of the semiconductor element 3 is attached. Is electrically connected to the metallized wiring layer 4 via the bonding wire 5, and then,
The metal lid body 2 is welded to the metal frame body 9 brazed to the upper surface of the insulating base body 1 by the seam weld method or the like, and the semiconductor element 3 is hermetically sealed inside the container composed of the insulating base body 1 and the metal lid body 2. When stopped, the final semiconductor device is obtained.

【0037】尚、本発明は上述した半導体素子収納用パ
ッケージに限定されるものではなく、本発明の要旨を逸
脱しない範囲であれば種々の変更は可能である。
The present invention is not limited to the above-mentioned package for accommodating semiconductor elements, and various modifications can be made without departing from the scope of the present invention.

【0038】[0038]

【発明の効果】本発明の半導体素子収納用パッケージに
よれば、窒化アルミニウム質焼結体もしくはガラスセラ
ミックス焼結体から成る絶縁基体にメタライズ金属層を
被着させるとともに該メタライズ金属層に金属枠体をビ
ッカース硬度(Hv)がHv≦40であるロウ材を介し
てロウ付け取着したことから絶縁基体に設けたメタライ
ズ金属層に金属枠体をロウ付け取着する際、絶縁基体と
金属枠体との熱膨張係数が相違し、両者間に大きな熱応
力を発生したとしても該応力はロウ材を変形させること
によって吸収され、両者のロウ付け部に大きな応力が内
在することは一切ない。従って、ロウ付け後、金属枠体
に外力が印加されたとしても該外力がロウ付け部に内在
する応力と相俊って大となり、金属枠体を絶縁基体より
剥離させることが皆無になるとともに容器の気密封止を
完全として内部に収容する半導体素子を長期間にわたり
正常、且つ安定に作動させることが可能となる。
According to the package for accommodating semiconductor elements of the present invention, a metallized metal layer is adhered to an insulating substrate made of an aluminum nitride sintered body or a glass ceramic sintered body, and a metal frame body is formed on the metallized metal layer. When the metal frame body is brazed and attached to the metallized metal layer provided on the insulating substrate, the insulating base body and the metal frame body are attached by brazing through a brazing material having a Vickers hardness (Hv) of Hv ≦ 40. Even if a large thermal stress is generated between the two and the two have different thermal expansion coefficients, the stress is absorbed by deforming the brazing material, and no large stress is inherently present in the brazing portion of both. Therefore, even if an external force is applied to the metal frame body after brazing, the external force becomes large in proportion to the internal stress of the brazing portion, and the metal frame body is never peeled off from the insulating substrate. It becomes possible to operate the semiconductor element housed inside completely and hermetically sealing the container normally and stably for a long period of time.

【0039】また絶縁基体を窒化アルミニウム質焼結体
やガラスセラミックス焼結体で形成したことから絶縁基
体の熱膨張係数を半導体素子の熱膨張係数に近似させる
ことができ、その結果、絶縁基体に半導体素子を取着し
た後、絶縁基体と半導体素子との間に熱が印加されたと
しても両者間には大きな熱応力が発生することはなく、
該熱応力によって半導体素子を破損させたり、半導体素
子を絶縁基体より剥離させて半導体装置としての機能を
喪失させることも皆無となる。
Further, since the insulating base is made of an aluminum nitride sintered body or a glass ceramic sintered body, the thermal expansion coefficient of the insulating base can be approximated to the thermal expansion coefficient of the semiconductor element. After attaching the semiconductor element, even if heat is applied between the insulating substrate and the semiconductor element, a large thermal stress does not occur between them,
There is no possibility of damaging the semiconductor element by the thermal stress or peeling the semiconductor element from the insulating substrate to lose its function as a semiconductor device.

【0040】更に絶縁基体を窒化アルミニウム質焼結体
で形成すれば絶縁基体の熱伝導率が80W/m ・K 以上とな
り、その結果、内部に収容する半導体素子が作動時に多
量の熱を発生したとしてもその熱は大気中に良好に放散
され、半導体素子を常に低温として長期間にわたり正常
に作動させることも可能となる。
Further, if the insulating substrate is made of an aluminum nitride sintered body, the thermal conductivity of the insulating substrate becomes 80 W / mK or more, and as a result, the semiconductor element housed inside generates a large amount of heat during operation. However, the heat is well dissipated in the atmosphere, and it becomes possible to keep the semiconductor element at a low temperature and operate it normally for a long time.

【0041】また更に絶縁基体を誘電率が低いガラスセ
ラミックス焼結体で形成すれば絶縁基体に設けたメタラ
イズ配線層を伝わる電気信号の伝播速度を極めて速いも
のとなすことができ、その結果、絶縁基体と蓋体とから
成る容器内部に高速で電気信号の出し入れをする高速駆
動タイプの半導体素子も収容することが可能となる。
Further, if the insulating substrate is made of a glass ceramic sintered body having a low dielectric constant, the propagation speed of the electric signal transmitted through the metallized wiring layer provided on the insulating substrate can be made extremely high, resulting in insulation. It is also possible to house a high-speed drive type semiconductor element that inputs and outputs electrical signals at high speed inside a container composed of a base body and a lid.

【図面の簡単な説明】[Brief description of drawings]

【図1】本発明の半導体素子収納用パッケージの一実施
例を示す断面図ある。
FIG. 1 is a sectional view showing an embodiment of a package for housing a semiconductor device of the present invention.

【図2】図1に示す半導体素子収納用パッケージの要部
拡大断面図である。
FIG. 2 is an enlarged cross-sectional view of a main part of the semiconductor element storage package shown in FIG.

【符号の説明】[Explanation of symbols]

1・・・・・絶縁基体 2・・・・・蓋体 3・・・・・半導体素子 4・・・・・メタライズ配線層 6・・・・・外部リード端子 7・・・・・メタライズ金属層 8・・・・・金属枠体 9・・・・・ロウ材 1 ... Insulating substrate 2 ... Lid 3 ... Semiconductor element 4 ... Metallized wiring layer 6 ... External lead terminal 7 ... Metallized metal Layer 8: Metal frame 9: Brazing material

Claims (1)

【特許請求の範囲】[Claims] 【請求項1】絶縁基体の表面に設けたメタライズ金属層
に金属枠体をロウ付けするとともに該金属枠体に金属製
蓋体を取着し、内部に半導体素子を気密に収容するよう
になした半導体素子収納用パッケージであって、前記絶
縁基体を窒化アルミニウム質焼結体もしくはガラスセラ
ミックス焼結体で形成し、且つメタライズ金属層に金属
枠体をロウ付けするロウ材のビッカース硬度(Hv)を
Hv≦40としたことを特徴とする半導体素子収納用パ
ッケージ。
1. A metal frame is brazed to a metallized metal layer provided on the surface of an insulating substrate, a metal lid is attached to the metal frame, and a semiconductor element is hermetically housed therein. Vickers hardness (Hv) of a brazing material in which the insulating substrate is formed of an aluminum nitride sintered body or a glass ceramics sintered body and a metal frame is brazed to a metallized metal layer. Is Hv ≦ 40.
JP4268470A 1992-10-07 1992-10-07 Package for storing semiconductor elements Expired - Lifetime JP2783735B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP4268470A JP2783735B2 (en) 1992-10-07 1992-10-07 Package for storing semiconductor elements

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP4268470A JP2783735B2 (en) 1992-10-07 1992-10-07 Package for storing semiconductor elements

Publications (2)

Publication Number Publication Date
JPH06120363A true JPH06120363A (en) 1994-04-28
JP2783735B2 JP2783735B2 (en) 1998-08-06

Family

ID=17458953

Family Applications (1)

Application Number Title Priority Date Filing Date
JP4268470A Expired - Lifetime JP2783735B2 (en) 1992-10-07 1992-10-07 Package for storing semiconductor elements

Country Status (1)

Country Link
JP (1) JP2783735B2 (en)

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0442739U (en) * 1990-08-07 1992-04-10

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0442739U (en) * 1990-08-07 1992-04-10

Also Published As

Publication number Publication date
JP2783735B2 (en) 1998-08-06

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