JPH06120242A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To prevent decrease of dielectric strength or hot carrier resistance of a gate oxide film of an MOS FET having LDD structure. CONSTITUTION:After a polycrystalline silicon film 7 is formed on the whole surface after a thermal oxide film on the surface of an N<-> layer 6 as an LDD region is eliminated, a thermal oxide film 8 is formed by thermally oxidizing the whole polycrystalline silicon film. At the same time, the LDD region surface is oxidized. A side wall 9A composed of silicon oxide is formed. The thickness of the polycrystalline silicon film is set equal to or smaller than 10nm. The thickness of the thermal oxide film which is formed as the result of that the LDD region surface is oxidized is set equal to or smaller than 5nm. Thereby the step-difference of the silicon substrate 1 surface at the end portion of a gate electrode 4 can be eliminated.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a semiconductor device, and more particularly to a method of manufacturing a semiconductor device having an LDD structure with enhanced hot carrier resistance.

[0002]

2. Description of the Related Art In recent years, the structure of MOS type semiconductor devices (FETs) has been miniaturized, and on the other hand, the operating voltage of transistors has not changed.
The electric field strength in the depletion layer region near the drain region inside the FET tends to continue to increase. Therefore, in a special case where the lateral electric field at the silicon substrate / gate oxide film interface becomes sufficiently large, the accelerated carriers in the region near the drain, where the electric field is particularly high, ionize and collide with the crystal lattice of the substrate, resulting in electron-hole Generate a pair. Usually, when the temperature (electron temperature, hole temperature) of a charged particle system accelerated in a high electric field region exceeds the lattice temperature, this charge is specially called a hot carrier. It will be injected into the gate oxide film over the barrier between the silicon / gate oxide film.

That is, electrons are injected in the N-channel transistor and holes are injected in the p-channel transistor. The injected carriers form an interface state at the silicon / oxide film interface or are trapped by charge traps in the oxide film to cause fixed charge accumulation, resulting in fluctuation of the threshold voltage of the transistor or reduction of carrier mobility. The reliability of the semiconductor device is impaired.

Conventionally, in order to prevent a decrease in reliability due to the miniaturization of such an element, LDD (Lightl) is added to the MOSFET.
Introducing a y-doped-drain) structure has been carried out.

A method of manufacturing a MOSFET having an LDD structure will be described below with reference to the drawings. FIG. 5 (a)-
(C) is sectional drawing of the semiconductor chip shown in order of process for demonstrating an example of the manufacturing method of the conventional MOS type FET.

First, as shown in FIG. 5A, a field oxide film 3 for element isolation and a channel stopper 5 made of a P ⁺ layer are formed on a P-type silicon substrate 1 by using a known technique. Then, subsequently, the gate oxide film 2 is formed on the silicon substrate 1 in the element region. Next, a gate electrode 4 is formed by forming a conductive film made of a single layer of polycrystalline silicon containing phosphorus or the like or a composite film of polycrystalline silicon and a silicide of a refractory metal and then patterning. RIE with high anisotropy when forming a fine element for etching
(Reactive Ion Etching) method or the like is used.

Next, as shown in FIG. 5B, N-type impurities are implanted in a self-aligned manner using the gate electrode 4 as a mask,
Form the N ⁻ layer 6. After forming the N ⁻ layer 6, the sidewall 19 is formed, but before that, there are three possible methods for treating the gate oxide film on the N ⁻ layer 6. The first is a method of forming a sidewall after removing the gate oxide film by using an etchant such as hydrofluoric acid. In the second method,
After removing the gate oxide film in the same manner as in the first method, a thermal oxide film is formed on the N ⁻ layer 6 by using a thermal oxidation method, and then a sidewall is formed. The third method is to leave the gate oxide film as it is and form sidewalls thereon.

In the third method in which the gate oxide film is not removed, after the ion implantation, a silicon oxide film is deposited on the entire surface of the element by the CVD method, and further, the chemical oxide etching method having anisotropy is used to form the silicon oxide film. By etching and leaving it on the side surface of the gate electrode 4,
9 is formed.

Next, as shown in FIG. 5C, in order to prevent the exposed surface of the silicon substrate from being damaged by the energy of ion implantation, a thin silicon oxide film 11 is formed on the entire surface of the device by a thermal oxidation method or It is formed by the CVD method.
Next, using the gate electrode 4 and the sidewall 19 as a mask, ions of a high-concentration N-type impurity such as arsenic or phosphorus are implanted in a self-aligning manner to form the N ⁺ layer 10. By heating in a higher temperature nitrogen atmosphere, the N ⁻ layer 6
And activate the N ⁺ layer 10 to complete the LDD structure.

[0010]

In the method of forming the MOSFET having the LDD structure, the gate oxidation on the N ⁻ layer 6 is performed after the formation of the N ⁻ layer 6 which is the LDD layer and before the formation of the sidewall. Three methods of treating the membrane are shown. The necessity of treating the oxide film on the N ⁻ layer 6 is based on the following reason.

In the above LDD structure forming method, when the electrode material is completely etched when forming the gate electrode,
Since the gate oxide film on the surface of the region where the N ⁻ layer is formed is exposed to etching plasma, an interface state occurs at the oxide film / silicon substrate interface, and damage such as charge trap occurs in the gate oxide film. Further, similar damage is applied to this region by the energy of ion implantation for forming the N ⁻ layer. The charge trap in the film is considered to be caused by trivalent silicon (O≡Si.) In the oxide film. The interface state is an unpaired bond in which the atomic bond between the oxide film and silicon is broken, and reduces the mobility of channel conduction carriers, and further acts as a charge trap.

To these damages, hydrogen mixed in the processing apparatus is bonded to Si-Hi in the subsequent heat treatment step.
Make a bond. Such a coupling cannot be detected electrically when it is completed as a device. However, when charges such as hot carriers are injected, they are easily broken and serve as interface states or charge traps. Therefore L
Although suppressed by using the DD structure,
When a large amount of generated hot carriers are injected, the carrier mobility is lowered by the generation of interface states, and the threshold voltage is changed by the trapping of charges. For the above reason, it is necessary to take some measures on the damaged gate oxide film on the N ⁻ layer to avoid the influence of the damage. When the third method shown in "Prior Art" is used,
Since the damaged oxide film remains, the reliability of the device is significantly impaired.

As one means for removing the above damage, after the step of implanting the impurity ions for forming the N ⁻ layer, the gate oxide film exposed on the surface is removed by the etching method, and then the sidewall is formed. It is conceivable and this is the first method mentioned in the prior art. When using this method, on the silicon substrate surface exposed by etching,
The CVD film, which is the raw material of the sidewall, is directly deposited. However, when the oxide film is formed on the silicon substrate by the CVD method, unpaired electrons of silicon are easily generated at the interface between the silicon and the oxide film. Since unpaired electrons trap hot carriers like traps in the oxide film, the resistance to hot carriers is lowered. As a countermeasure, N ^- after removing the oxide film on the layer 6, N by thermal oxidation ^- it is conceivable to form a thermal oxide film on the layer 6. This is the second method.

However, when this method is used, as shown in FIG. 6, the surface of the N ⁻ layer 6 is oxidized and a thick thermal oxide film 12 is formed, so that a step is formed at the end of the gate electrode 4 on the surface of the silicon substrate. Occurs, and the convex portion 13 is formed. When operating a transistor having such a convex portion 13, an electric field between the drain and the gate electrode is concentrated on the convex portion 13,
In this region, the breakdown voltage of the gate oxide film is lowered, or hot carriers are injected, which significantly impairs the reliability of the semiconductor device.

It is an object of the present invention to propose a method of manufacturing a semiconductor device, which eliminates the formation of convex portions caused by the oxidation of the surface of the silicon substrate after forming the LDD layer and improves the reliability of the semiconductor device. And

[0016]

A method of manufacturing a semiconductor device according to the present invention comprises a step of forming a gate electrode on a semiconductor substrate through a gate oxide film, and introducing impurities into the substrate by using the gate electrode as a mask. A step of forming a source / drain diffusion layer having a low impurity concentration; a step of removing the gate oxide film on the source / drain diffusion layer by a wet etching method and then forming a polycrystalline silicon film over the entire surface; And a step of thermally oxidizing the surface of the source / drain layer after oxidizing the silicon film to form an oxide film.

Since the polycrystalline silicon film cannot be completely oxidized, L
When the polycrystalline silicon remains on the surface of the DD layer, the remaining polycrystalline silicon becomes the outermost surface of the silicon region, and a current flows there during the transistor operation. However, since polycrystalline silicon has a low electric conductivity, the driving force of the transistor is lowered in this case. Therefore, it is necessary to oxidize the entire polycrystalline silicon film so that current flows on the surface of the LDD layer. It is difficult to oxidize only the polycrystalline silicon film and not the LDD layer at all, and the surface of the LDD layer is actually oxidized. When a polycrystalline silicon film is grown on the LDD layer, an interfacial structure is formed between both layers. Therefore, when only the polycrystalline silicon film is oxidized, this interfacial structure remains, and conduction electron scattering occurs during transistor operation. And cause deterioration of transistor characteristics. But LD
When the surface of the D layer is oxidized, this interface structure disappears, so that the above characteristic deterioration does not occur. However, if the thickness of the oxide film formed by oxidizing the surface of the LDD layer is too large, a protrusion is formed on the surface of the silicon substrate at the end of the gate electrode as in the conventional example. Therefore, it is necessary to reduce this thickness. There is. In this case, the thickness is preferably 5 nm or less.

By using this method, even if thermal oxidation is performed after removing the gate oxide film on the LDD layer including damage, the generation of the convex portion on the silicon surface at the end of the gate electrode is eliminated. In addition, it is possible to suppress a decrease in withstand voltage of the gate oxide film and a decrease in hot carrier resistance.

[0019]

Embodiments of the present invention will be described below with reference to the drawings.

FIGS. 1A to 1D are sectional views of a semiconductor chip shown in the order of steps for explaining the first embodiment.

First, as shown in FIG. 1A, similarly to the conventional example, a field oxide film 3 for element isolation and a channel stopper 5 from a P ⁺ layer are formed on a P-type silicon substrate 1, and subsequently, About 15 thick on the silicon substrate 1 in the device area
A gate oxide film 2 having a thickness of nm is formed. Next, a conductive film made of a single layer of polycrystalline silicon containing phosphorus or the like or a composite film of polycrystalline silicon and silicide of a refractory metal is formed and then patterned to form the gate electrode 4. For the etching, a highly anisotropic RIE method or the like is used. Next, using the gate electrode 4 as a mask, ions of N-type impurities such as phosphorus are implanted to form the N ⁻ layer 6 of the LDD structure in a self-aligned manner.

Then, the gate oxide film on the surface of the N ⁻ layer 6 is removed by using hydrofluoric acid, and then a polycrystalline silicon film 7 is deposited on the entire surface of the device by a known CVD method, for example, to a thickness of 10 nm.

Next, as shown in FIG. 1B, the deposited polycrystalline silicon film 7 is entirely oxidized by the thermal oxidation method to form a thermal oxide film 8. Further, the surface of the N ⁻ layer 6 is thermally oxidized to form a thermal oxide film of about 3 nm.

Next, a silicon oxide film 9 on the entire surface of the device is formed by CVD.
Method is used to deposit about 400 nm. Thereafter, the same operation as in the conventional example is performed.

That is, next, as shown in FIG. 1C, the silicon oxide film 9 is etched by using a chemical ion etching method having anisotropy to form a sidewall 9A on the side surface of the gate electrode 4. Next, as shown in FIG. 1D, a thin silicon oxide film 11 is formed on the entire surface by a thermal oxidation method or a CV method.
After the formation by the D method, using the gate electrode 4 and the sidewall 9A as a mask, highly concentrated ions of N-type impurities such as arsenic or phosphorus are implanted in a self-aligned manner, and further heated in a high-temperature nitrogen atmosphere. To activate the ion implantation layer to form the N ⁻ layer 6 and the N ⁺ layer 10,
Complete the DD structure.

A comparison was made between the MOSFET having the LDD structure manufactured by using the first embodiment and the conventional example. 2 and 3 are MOs created using this embodiment and the conventional example.
It is a figure which shows the relationship between the withstand voltage and frequency of SFET. Here, when the source / drain and the substrate are grounded and a step voltage is applied to the gate electrode, the gate current density is 1
A voltage value that exceeded 00 mA · cm ² was determined. The electric field strength in the gate oxide film is obtained from this voltage value, and this is defined as the breakdown voltage electric field strength. The sample had an array structure in which 10,000 transistors each having a gate length of 5 μm and a gate width of 20 μm were connected in parallel as one unit, and evaluation was performed using 50 of this array.

A product having a withstand voltage electric field strength of more than 8 MV / cm is a good product, and a product having a withstand voltage electric field strength of 8 MV / cm or less is a defective product.
The number of good products in each sample was defined as the good product rate. As a result, when this embodiment is applied, the yield rate is 90%.
However, when the conventional technology is used, the yield rate is 6
It was below 0%.

FIG. 4 shows the variation Δ in the mutual conductance g _m after the stress is applied under the condition that the gate current is maximum.
It shows the time change of g _m . The change in transconductance reflects the decrease in carrier mobility due to the generation of interface states due to hot carrier injection. It can be seen that Δg _{m of} the transistor using the first embodiment is smaller than that of the transistor using the conventional manufacturing method.
From this fact, it is understood that the hot carrier resistance of the transistor according to the present embodiment is significantly improved.

In the above embodiment, the N-channel transistor is taken as an example, but the same effect can be obtained also with the P-channel transistor.

Next, a second embodiment of the present invention will be described. In the second embodiment, the thermal oxidation performed after the removal of the gate oxide film on the LDD layer and the formation of the polycrystalline silicon film is performed by rapid oxidation using a lamp annealer.

The use of the lamp annealer has an advantage that it is easier to form a thin oxide film, as compared with the case of using the core tube type oxidizer. Furthermore, since an oxide film having a desired film thickness can be formed by heat treatment in a shorter time than in the case of using a core tube, impurities in the substrate are less likely to diffuse during heating. LD in a fine transistor structure
When an impurity such as D diffuses, a depletion layer near the source and the drain is connected to cause a punch-through phenomenon in which the operation of the transistor cannot be controlled. Therefore, it is necessary to suppress the heat treatment as much as possible. Therefore, forming an oxide film in a short time using a lamp anneal has an advantage that it meets the requirements of the process for punch-through prevention.

[0032]

As described in detail above, according to the present invention, after the formation of the impurity diffusion layer having the LDD structure, the gate oxide film on the surface of the impurity diffusion layer is removed by using an etchant such as hydrofluoric acid to make it thin. A polycrystalline silicon film is formed, and then all the polycrystalline silicon films are oxidized by a thermal oxidation method. At the same time, a thermal oxide film of 5 nm or less is formed on the surface of the impurity diffusion layer, and then a sidewall is formed on the side wall of the gate electrode. By forming it, a convex portion is not formed on the surface of the silicon substrate at the end portion of the gate electrode, so that a good thermal oxide film can be formed on the impurity diffusion layer of the LDD. Therefore MOSF
Without impairing the dielectric strength characteristics of the ET gate oxide film,
There is an effect that the hot carrier resistance can be improved.

[Brief description of drawings]

FIG. 1 is a sectional view of a semiconductor chip for explaining a first embodiment of the present invention.

FIG. 2 is a diagram showing a withstand voltage characteristic of an example.

FIG. 3 is a diagram showing a withstand voltage characteristic of a conventional example.

FIG. 4 is a diagram showing a relationship between stress application time and Δgm.

FIG. 5 is a cross-sectional view of a semiconductor chip for explaining a conventional example.

FIG. 6 is a cross-sectional view of a semiconductor chip for explaining a conventional example.

[Explanation of symbols]

1 Silicon Substrate 2 Gate Oxide Film 3 Field Oxide Film 4 Gate Electrode 5 Channel Stopper 6 N ^- Layer 7 Polycrystalline Silicon Film 8 Thermal Oxide Film 9,19 Silicon Oxide Film 10 N ⁺ Layer 11 Silicon Oxide Film 12 Thermal Oxide Film 13 Convex Department

Claims (1)

[Claims] 1. A step of forming a gate electrode on a semiconductor substrate through a gate oxide film, and a step of introducing impurities with the gate electrode as a mask to form a source / drain diffusion layer having a low impurity concentration on the substrate. A step of removing the gate oxide film on the source / drain diffusion layer by a wet etching method and then forming a polycrystalline silicon film on the entire surface, and oxidizing the polycrystalline silicon film to form an oxide film, and then forming the source / drain And a step of thermally oxidizing the surface of the layer.