JPH06119245A - Cache memory - Google Patents

Abstract

PURPOSE:To relieve an error caused by a temporary factor by resuming access even in the case an error is detected at the time of accessing a cache memory provided with an error check function. CONSTITUTION:When data to be accessed exists and a hit signal 7 becomes active by a comparator 5, in the case one of a parity error signal 6 or 10 outputted from a parity circuit 4 for a tag memory 3 or a parity circuit 9 for a data memory becomes active and an error is detected, a re-execution request means 11 makes a re-execution request signal 12 active and requests a reaccrss to the same address of a cache memory, and in this case, an effective bit 3c provided in the tag memory 3 is maintained in an effective state, and unless an error is generated at the time of resuming access, a cache hit operation is executed.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a cache memory having a data error check function such as a parity check.

[0002]

2. Description of the Related Art FIG. 4 is a block diagram showing the configuration of a conventional associative memory circuit with an error check function disclosed in Japanese Patent Laid-Open No. 63-121947, which is an associative memory circuit and a data memory for storing data. In a cache memory having a combination of and, a directory of data in the data memory is stored in a tag memory including an associative memory circuit. In the figure, 1 is the address of the access target data given from the outside, the upper part of the address 1 is the tag address 1a which is a directory of the data, the lower part is the direct mapping type tag memory 3 and the entry in the data memory not shown Entry address 1b.

The parity circuit 4 generates a parity bit from the tag address 1a, and the parity bit generated by the parity circuit 4 is stored in association with the tag address 3b stored in the tag memory 3. The decoder 2 decodes the entry address 1b and designates an entry in the tag memory 3 and the data memory.

The comparator 5 has a tag address 1a given from the outside and a parity bit 4a generated from the tag address 1a by the parity generation circuit 4 at the time of access from the outside.
The tag address 3b read from the tag memory 3 and the parity bit 3a are compared, and the hit signal 7 is activated when the comparison results match.

Next, an operation at the time of read access of the cache memory incorporating the associative memory circuit with an error check function as described above will be described. The decoder 2 decodes the entry address 1b out of the address 1 given from the outside and designates the entry of the tag memory 3. The tag address 3b and the corresponding parity bit 3a read from the tag memory 3 of the specified entry,
The comparator 5 compares the tag address 1a from the outside and the parity bit 4a generated at the time of access from this tag address 1a.
Are compared, and if the comparison results are in agreement, the hit signal 7 is activated and the cache hit operation is performed. That is, the data in the data memory of the entry corresponding to the tag address 3b is transferred to the outside.

If the comparison result by the comparator 5 does not match, the cache miss operation is performed without activating the hit signal 7. That is, correct data is fetched from the main memory to the data memory, and the data from the main memory is transferred to the outside.

[0007]

Since the conventional cache memory having the tag memory with an error check function has the above-mentioned configuration, the detected error is temporary and an error that is recovered by re-reading. Even in the case, the cache hit operation always causes the hit rate to decrease, but there is no means for determining whether the error is due to a temporary cause or a fixed cause.

The present invention has been made in order to solve such a problem, and when an error is detected, it is reaccessed to determine whether the error is temporary and In the case of a large error, the cache hit operation is performed to provide a cache memory with a high hit rate.

[0009]

A cache memory according to a first aspect of the present invention re-creates an error detected when an error is detected, while maintaining a valid bit indicating whether or not correct contents are stored in data as a valid value. It is characterized in that a cache hit operation is performed if it is possible to determine that the error is temporary without making an error detection at the time of access and re-access.

The cache memory according to the second invention re-accesses when an error is detected, and if the error is detected at the time of re-access and it can be determined that the error is fixed, the data is made inaccessible. It is characterized by

The cache memory according to the third aspect of the present invention stores whether or not an error has occurred in the past of data,
When an error is detected, if the error has occurred in the past and it can be determined that the error is fixed, the data is made inaccessible. If no error has occurred in the past, the error occurrence is memorized and re-accessed. However, if the error is detected continuously at the time of re-access and it is determined that the error is fixed, the data becomes inaccessible,
A feature is that a cache hit operation is performed if an error is not detected at the time of re-access and it can be determined that the error is temporary.

[0012]

In the cache memory according to the first aspect of the present invention, when an error is detected in the data at the time of a cache hit in which the data to be accessed exists, the same data is regenerated while keeping the valid bit of this data at a value indicating validity. Access,
If no error is detected during reaccess and it can be determined that the error is temporary, a cache hit operation is performed.

In the cache memory according to the second aspect of the present invention, when an error is detected in the data at the time of a cache hit in which the data to be accessed exists, the same data is re-accessed and the errors are continuously detected at the time of the re-access. If the error is determined to be fixed, this data is made inaccessible.

In the cache memory according to the third aspect of the present invention, when an error is detected in the data at the time of a cache hit in which the data to be accessed exists, it is determined that an error has occurred in the past and the error is fixed. If this happens, this data will be inaccessible, but if no error has occurred in the past, the same data will be re-accessed, and when re-accessing, errors will occur continuously and if the error is determined to be fixed. While making this data inaccessible, if no error is detected during re-access and it can be determined that the error is temporary, a cache hit operation is performed.

[0015]

DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be described below with reference to the drawings showing its embodiments. FIG. 1 is a block diagram showing the configuration of a direct mapping type cache memory according to the present invention. The same or corresponding parts as those of the conventional example shown in FIG.

The parity circuit 4 performs a parity check on the tag address 3b read from the tag memory 3 in addition to generating the parity bit 3a from the tag address 1a of the addresses given from the outside, and as a result of the parity check, an error is detected. If it is detected, the re-execution request means 11 described later
The parity error signal 6 output to is activated. Further, the comparator 5 compares the tag address 1a of the addresses 1 given from the outside with the tag address 3b read from the tag memory 3, and if they match, activates the hit signal 7.

In the figure, 8 is a data memory, 9 is a parity circuit for generating a parity bit 8b from data 8a fetched from a main memory (not shown).
The entry of the data 8a and the parity bit 8b stored therein corresponds to the tag address 3b in the tag memory 3.

Further, the parity circuit 9 performs the parity check of the data 8a in the data memory 8 in addition to the generation of the parity bit for the data memory 8 described above, and if an error is detected as a result of the parity check, the re-execution will be described later. The parity error signal 10 output to the request means 11 is activated. Further, the tag memory 3 is provided with a valid bit 3c indicating whether or not correct data is stored, in addition to the parity bit 3a for error detection.

The re-execution request means 11 comprises an OR gate, and when either of the parity error signals 6 or 10 output from the parity circuit 4 or 9 becomes active, a re-access request is issued to request re-access to the cache memory to the outside. Activate signal 12.

Next, the operation at the time of read access from the outside will be described. The decoder 2 decodes the entry address 1b of the address 1 given from the outside to specify the entry of the tag memory 3 and the data memory 8. The comparator 5 compares the tag address 3b read from the tag memory 3 of the designated entry with the external tag address 1b.

When the comparison result of the comparator 5 does not match, or when the valid bit 3c is in the invalid state, the hit signal 7 does not become active and the cache miss operation is performed. That is, the data is fetched from the external main memory, the data is stored in the entry of the data memory 8 corresponding to the tag address 3b of the tag memory 3, and the corresponding valid bit 3c in the tag memory 3 is set to a value indicating validity. To do.

On the other hand, when the comparison results of the comparator 5 match and the valid bit 3c has a value indicating valid, the hit signal 7 is activated and the cache hit operation is performed.

However, at the time of this cache hit, if the parity circuit 4 or 9 detects a parity error, the parity error signal 6 or 10 becomes active, and the re-execution request signal 12 output from the re-execution request means 11 becomes active. become. When the re-execution request signal 12 becomes active, the cache memory is read-accessed again from the outside at the same address. At this time, the valid bit 3c of the tag memory 3 at the position designated by the tag address 1a holds a value indicating validity and is not invalidated.

When the parity circuit 4 or 9 detects a parity error as a result of the re-execution, the re-execution request means 11 is activated by activating the parity error signal 6 or 10.
Sets the valid bit 3c to a value indicating invalidity and performs a cache miss operation.

If no parity error is detected as a result of the re-execution, the valid bit 3c indicates valid, so the cache hit operation is performed. That is, the data 8a of the entry of the data memory 8 corresponding to the tag address 3b is output to the outside.

FIG. 2 is a block diagram showing the configuration of another embodiment of the cache memory according to the present invention. The same or corresponding parts as those of the conventional cache memory and the first embodiment described above are designated by the same reference numerals and the description thereof is omitted. In this embodiment, in addition to the parity bit 3a and the valid bit 3c, the inaccessibility of the entry is at the L level and the accessible is at the H level.
An inaccessible bit 3d indicated by the level is provided in the tag memory 3.

Further, the re-execution request means 20 receives the parity error signals 6 and 10 as its two inputs, and when any one of the parity error signals 6 or 10 becomes active, the re-execution request signal 21 becomes active. The gate 204, the D latch 203 that holds the re-execution request signal 21 from the OR gate 204 until the next input, and the output of the OR gate 204 and the delayed output 202 of the D latch 203 as its two inputs are inaccessible bit 3d And a NAND gate 201 that determines the level of

Next, the operation at the time of read access from the outside will be described. The operation at the time of a cache miss is similar to that of the first embodiment shown in FIG. The operation when no error is detected at cache hit is as follows.
This is the same as the first embodiment shown in FIG. 1 except that the cache memory becomes inaccessible when the inaccessible bit 3d is at the L level.

When the read access is started with the inaccessible bit 3d being at the H level, the parity circuit 4 or 9
If an error is detected in step 1, the re-execution request signal 21 from the re-execution request means 20 becomes active, and the D latch 203 holds that the re-execution request signal 21 becomes active (H level). After that, the cache memory is read-accessed again from the outside with the same address.

When no error is detected in the parity circuit 4 or 9 when the read access is performed again, the re-execution request signal 21 from the re-execution request means 20 does not become active,
The NAND gate 201 is provided with two inputs of the delay output 202 (H level) and the re-execution request signal 21 (L level) of the D latch 203.
Output becomes H level, the inaccessible bit of the entry is maintained accessible (H level), and the cache hit operation is performed. That is, the data 8a of the entry of the data memory 8 corresponding to the tag address 3b is output to the outside.

On the other hand, when an error is detected again by the parity circuit 4 or 9 when the read access is made again, the re-execution request signal 21 from the re-execution request means 20 becomes active, and the delayed output 202 of the D latch 203. And re-execution request signal
By the two inputs of 21, the output of the NAND gate 201 becomes L level, the inaccessible bit of the entry is set inaccessible (L level), and the entry remains inaccessible until it is reset. A cache miss operation is performed each time it is specified. Therefore, when an error is continuously detected in the same entry, the entry is not accessed thereafter, and it is not necessary to perform unnecessary error processing.

FIG. 3 is a block diagram showing the configuration of still another embodiment of the cache memory according to the present invention. In addition,
The same or corresponding portions as those of the conventional cache memory shown in FIG. 4 and the first and second embodiments shown in FIGS. 1 and 2 are designated by the same reference numerals and their description is omitted.

In this embodiment, the error occurrence storage bit 3e is set in the tag memory 3 so as to be set to the L level when no error has occurred in the past and to the H level when the error has occurred in the past. Further provided. After the reset, the error occurrence storage bit 3e is set to the L level, and the error is not generated. Further, in the present embodiment, instead of the re-execution requesting means 11 or 20, the OR gate 30 which receives the parity error signals 6 and 10 from the parity circuits 4 and 9 as two inputs, the output of the OR gate 30 and the error occurrence. A NAND gate 31 having the memory bit 3e as two inputs is provided.

Next, the operation at the time of read access from the outside will be described. The operation at the time of a cache miss and the operation when an error is not detected at the time of a cache hit are the same as those in the first embodiment, and the inaccessible bit 3d.
Has the same function as in the second embodiment. When an error is detected in the parity circuit 4 or 9 when the read access is made to the entry in which the inaccessible bit 3d is at the H level, the error occurrence storage bit 3e of the entry designated by the entry address 1b is at the H level. When an error has occurred in the past, a cache miss operation is performed and the inaccessible bit 3d is set to inaccessible (L level).

On the other hand, in the same state as described above, when the error occurrence storage bit 3e is L level and no error has occurred in the past, the error occurrence storage bit 3e is set to H level and the same address is read-accessed again. .

When an error is detected in the parity circuit 4 or 9 at the time of re-access, since the error occurrence storage bit 3e is set to the H level, a cache miss operation is performed and the inaccessibility bit 3d is inaccessible (L level). Set to. That is, when an error is detected twice in succession in the same entry, the entry is not accessed thereafter, so that it is not necessary to perform unnecessary error processing. If no error is detected during reaccess, cache hit operation is performed.

In this embodiment, the error detection of the data is performed by the parity error detection, but the error detection is not limited to this, and another error detection method may be used, like the present embodiment. The effect of is obtained.

Further, although the memory cell configurations of the tag memory and the data memory are not mentioned in the present embodiment, the same effect as the present embodiment can be obtained regardless of the configuration of these memory cells.

In this embodiment, the cache memory of the direct mapping system has been described as an example, but the same effect as that of this embodiment can be obtained even if the cache memory of another mapping system such as full associative mapping and set associative mapping is used. can get.

[0040]

As described above, in the cache memory according to the first invention, even when an error is detected in the data to be accessed, the same data is re-accessed while maintaining the valid bit of the data at the valid value. As a result, no error is detected at the time of re-access, and if there is an error due to a temporary cause, the cache hit operation is enabled, and the excellent effect of improving the hit rate is achieved.

Further, the cache memory according to the second aspect of the present invention re-accesses the same data when an error is detected in the data to be accessed, and when the re-access is performed, an error occurs continuously and the error is fixed. When it is determined to be due to the cause, it makes the data inaccessible and disables access to that data thereafter, thereby eliminating the need to perform unnecessary error processing and improving the memory processing efficiency. Play.

Furthermore, since the cache memory according to the third aspect of the present invention is an access target, if an error is detected in the data, if an error has occurred in the past, it is determined as a fixed error and the data is made inaccessible. On the other hand, if no error has occurred in the past, the error occurrence is memorized and re-accessed, and if errors are continuously detected during re-access, it is judged as a fixed error and the data becomes inaccessible. If an error is not detected at the time of access, it is judged as a temporary error and the cache hit operation is enabled to improve the hit rate, and it is also possible to improve the memory processing efficiency by eliminating the need for unnecessary error processing. Produce an effect.

[Brief description of drawings]

FIG. 1 is a block diagram showing the configuration of a first embodiment of a cache memory according to the present invention.

FIG. 2 is a block diagram showing a second embodiment configuration of a cache memory according to the present invention.

FIG. 3 is a block diagram showing a configuration of a cache memory according to a third embodiment of the present invention.

FIG. 4 is a block diagram showing a configuration of a conventional cache memory.

[Explanation of symbols]

 1 address 1a tag address 1b entry address 2 decoder 3 tag memory 3a parity bit 3b tag address 3c valid bit 3d inaccessible bit 3e error occurrence memory bit 4,9 parity circuit 5 comparator 6,10 parity error signal 7 hit signal 8 data Memory 8a Data 8b Parity bit 11,20 Re-execution request means 12,21 Re-execution request signal 30 OR gate 31 NAND gate 201 NAND gate 202 Delay output 203 D-latch 204 OR gate

Claims (3)

[Claims] 1. Data is stored together with error detection data capable of detecting an error in the data, and when a cache hit in which data to be accessed exists, the data error is checked by the error detection data and then transferred to the outside. In a cache memory with an error check function, a valid bit that indicates whether or not the correct contents are stored in the data and that the data is valid, and a valid bit that is valid when an error is detected in the data to be accessed And a means for re-accessing the data while maintaining the value indicating. 2. Data is stored together with error detection data capable of detecting an error in the data, and the data error is checked by the error detection data at the time of a cache hit where the data to be accessed exists, and then transferred to the outside. In a cache memory with an error check function, a means for making predetermined data inaccessible, a means for re-accessing the data to be accessed when an error is detected, and a case where an error is detected at the time of re-access And a means for making the data inaccessible, the cache memory. 3. Data is stored together with error detection data capable of detecting an error in the data, and when a cache hit exists where the data to be accessed exists, the data error is checked by the error detection data and then transferred to the outside. In a cache memory with an error check function, means for making certain data inaccessible, means for storing the presence or absence of an error in past data, and if an error is detected in the data to be accessed, the data is past If there is an error in the data, the data is made inaccessible, and if no error has occurred in the past, the error occurrence of the data is stored and the data is re-accessed. A cache memory characterized by.