JP2011107888A - Arithmetic processor and method for controlling arithmetic processor - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To speed up load operation concerning an arithmetic processor and a method for controlling the arithmetic processor. <P>SOLUTION: The arithmetic processor includes: a first storage part that stores data; an error detection part that detects an occurrence of error in data read out from the first storage part; a second storage part that stores data read out from the first storage part based on a load request; a rerun request generation part that generates a rerun request of a load request to the first storage part in the same cycle as the cycle in which error of data is detected when the error detection part detects the occurrence of error in data read out from the first storage part by the load request; and an instruction execution part that retransmits the load request to the first storage part when data in which error is detected and a rerun request are given. <P>COPYRIGHT: (C)2011,JPO&INPIT

Description

  The present invention relates to an arithmetic processing device and a control method for the arithmetic processing device.

  In recent years, a processor using a pipeline system has been used to increase the processing speed of a processor as an arithmetic processing unit. In the pipeline system, the processor has a plurality of pipelines (an instruction control pipeline, an arithmetic pipeline, a branch control pipeline, etc.) that realize the function. Each pipeline is divided into a plurality of stages. Each stage includes a circuit unit that realizes a predetermined process, and operates so as to end the predetermined process assigned to each stage within a period called a cycle time that is the reciprocal of the operating frequency. The output signal of the stage related to the previous process is used as the input signal of the stage related to the subsequent process, for example.

  As a technique for increasing the processing speed of a processor using a pipeline system, a tag RAM (Random Access Memory) and a cache memory that operates to access a data RAM in one cycle have been proposed.

JP 2004-171177 A

  The process of checking the data read from the data RAM for error and the process of determining whether or not to permit the use of the data read to the processor according to the error check result are processes that are continuous with each other. These two processes cannot be completed. Therefore, the above two processes take at least two cycles in total.

  An object of the disclosed arithmetic processing device is to speed up the load operation from the data RAM.

  The disclosed arithmetic processing device includes a first storage unit that stores data, an error detection unit that detects occurrence of an error for data read from the first storage unit, and data read from the first storage unit, When the second storage unit that stores data based on the load request and the error detection unit detect the occurrence of an error in the data read from the first storage unit by the load request, the load request to the first storage unit A retransmission request generation unit that generates the retransmission request in the same cycle as the cycle in which the data error is detected, and when the error detected data and the retransmission request are given, the load request is retransmitted to the first storage unit An instruction execution unit.

  The disclosed arithmetic processing device has the effect of speeding up the load operation from the data RAM.

It is a figure which shows an example of a structure of an arithmetic processing unit. It is a figure which shows an example of a command part and L1 cache. It is a figure which shows an example of the transition of the data request | requirement to a pipeline. It is a figure which shows an example of the truth table which prescribes | regulates priority control. It is a figure which shows an example of the execution procedure of the address control process in L1 cache. It is a figure which shows an example of the execution procedure of the address control process in L1 cache. It is a figure which shows an example of the execution procedure of the address control process in L1 cache. It is a figure which shows an example of the execution procedure of the flag control process in L1 cache. It is a figure which shows an example of the flag signal used for pipeline control. It is a figure which shows an example of the truth table which prescribes | regulates the priority of the flag signal selection hold | maintained at a holding circuit. It is a figure which shows an example of TLB. It is a figure which shows an example of tag RAM. It is a figure which shows an example of data RAM. It is a figure which shows an example of a clock control part. It is a figure which shows an example of an error check circuit. It is a figure which shows an example of a resending request production | generation part. It is a figure which shows an example of a control signal generation part. It is a figure which shows an example of the VALID signal processing of a pipeline. It is a figure which shows an example of circuit arrangement | positioning of an arithmetic processing unit. It is a time chart which shows an example of the pipeline process when a resending request | requirement is issued. It is a time chart which shows an example of the pipeline process when a resending request | requirement is issued. It is a time chart which shows an example of the pipeline process when a resending request | requirement is issued.

  Hereinafter, an embodiment of a processor as an arithmetic processing device will be described with reference to the drawings. FIG. 1 is a diagram illustrating an example of a configuration of an arithmetic processing device. The arithmetic processing apparatus 10 illustrated in FIG. 1 includes an instruction execution unit 4 and an L1 cache 20. The instruction execution unit 4 includes a decoding unit 2 and an execution unit 3. An example of the L1 cache 20 will be described later with reference to FIG.

  The decoding unit 2 supplies the “data request signal” to the L1 cache 20 and reads the “instruction”. The decoding unit 2 decodes (decodes) the “instruction (opcode)” read from the L1 cache 20 and stores the operand (operand) such as the instruction decoding result and the number of operands to be executed by the instruction. The registered address is supplied to the execution unit 3 as an “operation control signal”. Examples of instructions to be decoded include a load instruction to the L1 cache 20 and a store instruction.

  The execution unit 3 extracts data as an operand from a register specified by a register address in a register file inside the execution unit 3, and calculates data according to the decoded instruction. The execution unit 3 supplies the L1 cache 20 as a “data request signal” by executing the decoded instruction. The “data request signal” is hereinafter referred to as “EXT request”. The “EXT request” includes a load instruction, a store instruction, a prefetch instruction, and the like.

  For example, the L1 cache 20 supplies the requested data to the execution unit 3 in accordance with a load instruction. When the execution unit 3 finishes executing the instruction, the execution unit 3 supplies an “operation completion signal” to the decoding unit 2 in order to receive the next operation control signal.

  The L1 cache 20 is an upper layer memory of the L2 cache 400 and caches a part of the data held by the L2 cache 400. That is, the L2 cache 400 includes and holds data cached by the L1 cache 20. The L2 cache 400 is a higher-level memory of the main storage device 500 and caches a part of data held by the main storage device 500. That is, the main storage device 500 includes and holds data cached by both the L2 cache 200 and the L1 cache 20.

  The case where the instruction or data accessed by the decoding unit 2 or the execution unit 3 in the memory exists in the L1 cache 20 is hereinafter referred to as “cache hit”. Hereinafter, the case where the instruction or data accessed by the decoding unit 2 or the execution unit 3 does not exist in the L1 cache 20 is referred to as “cache miss”. When a cache miss occurs, control is performed to read the cache-missed data from the L2 cache 400 or the main storage device 500 in the lower hierarchy of the L1 cache 20 to the L1 cache 20.

  FIG. 2 is a diagram illustrating an example of the L1 cache. The instruction execution unit 4 has a data buffer 5. The data buffer 5 is a buffer that holds an instruction read from the L1 cache 20.

  The L1 cache 20 includes a cache controller 200, a clock control unit 110, a data RAM 120, an error check circuit 130, a selection circuit 140, a retransmission request generation unit 150, a control unit 180, an L2 order holding unit 190, and an L2 request holding unit 195. The cache controller 200 includes a pipeline 100 and a control unit 180.

  The pipeline 100 includes a translation look-aside buffer (TLB) 35, a tag RAM 30, a comparison circuit 40, and a control signal generation unit 50.

  The instruction execution unit 4 has a data buffer 5. The data buffer 5 holds the data supplied from the selection circuit 140.

  The pipeline 100 includes a priority circuit 25, a tag RAM 30, a TLB 35, and a comparison circuit 40. The above-described components included in the pipeline 100 are assigned to a plurality of stages, respectively. For example, the priority circuit 25 is assigned to the “P (Priority) stage”, the tag RAM 30 and the TLB 35 are assigned to the “T (Tag) stage”, and the comparison circuit 40 is assigned to the “M (Match) stage”. . An example of the pipeline 100 will be described later with reference to FIGS. 5, 7, and 8.

  The clock control unit 110 supplies a clock to the data RAM 120 when it is necessary to supply a clock to the data RAM 120 such as when there is an access request for data held by the data RAM 120. Details of the clock control unit 110 will be described later with reference to FIG.

  Details of the TLB 35, the tag RAM 30, the data RAM 120, and the error check circuit 130 will be described later with reference to FIGS. 11, 12, 13, and 15, respectively.

  The comparison circuit 40 is a circuit that compares the absolute address supplied from the TLB 35 with the absolute address supplied from the tag RAM 30 and determines whether the two tags match. When the tag supplied from the TLB 35 and the tag supplied from the tag RAM 30 match, the comparison circuit 40 supplies the selection circuit 140 with a tag hit way signal that identifies the way in which the cache hit has occurred.

  The L2 request holding unit 195 holds a request used when loading data from the L2 cache 400.

  The L2 order holding unit 190 holds a request to delete a corresponding cache line entry in the L1 cache 20 when a process of deleting a cache line from the L2 cache 400 is performed. Hereinafter, this deletion request is referred to as “L2 order”. The L2 order dequeued from the L2 order holding unit 190 is held in a P (Priority) cycle order address register (PSXR) described later.

  The retransmission request generation unit 150 and the control signal generation unit 50 will be described later with reference to FIGS. 16 and 17, respectively. When a cache error occurs, the control unit 180 loads data into the L2 cache 400 and stores the loaded data into the L1 cache.

  FIG. 3 is a diagram illustrating an example of a transition of a data request to the pipeline. A state S101 indicates a state in which the priority circuit 25 is accepting a request signal. A state S103 indicates a state in which the priority circuit 25 waits for a request to be input to the TLB 35, the tag RAM 30, and the clock control unit 110 in the next stage.

  When the priority circuit 25 receives the above four types of requests (T102) and enters the request input waiting state (S103), the priority circuit 25 selects a request to be supplied to the next stage according to the truth table shown in FIG. . The states S101 and S103 shown in FIG. 3 are implemented by a latch circuit prepared for each request type. The transition T102 from the state S101 to the state S103 occurs when a request is set in the priority circuit 25. Transition T104 from state S103 to state S101 occurs by supplying a request to the next stage.

  The priority circuit 25 shown in FIG. 2 receives an EXT request, a BIS request, an MI request, and an INT request, selects those requests based on a predetermined priority order, and selects the selected request as a TLB 35, a tag RAM 30, This is supplied to the clock controller 110.

  The EXT request is a request given from the instruction execution unit 4. Memory access requests such as load requests, store requests, and prefetch requests are included.

  The BIS request is a request for deleting the line of the L1 cache 20 given from the L2 cache 400. The BIS request is requested when an error is detected in the data RAM 120 and a line related to the error is deleted.

  The MI request is a request for writing the data loaded from the L2 cache 400 to the data RAM, which is given from the cache controller 200. The MI request is made to the target line after the BIS request is made.

  The INT request is a request given from the pipeline 100 in order to execute a predetermined process using the data before the stop after the EXT request stops the pipeline 100.

  FIG. 4 is a diagram illustrating an example of a priority truth table. “0” in the truth table 1000 indicates that the request is in the request accepting state (S101). “1” in the truth table 1000 indicates that the request is in a request input waiting state. “*” In the truth table 1000 indicates that the don't care is not related to the priority determination regardless of the state of the body request.

  The column R101 shown in FIG. 4 indicates that if the MI request is in the request input waiting state (S103), the MI request is input to the next stage regardless of other requests.

  A row R102 shown in FIG. 4 indicates that when the BIS request is in the request input waiting state (S103) and the MI request is in the request accepting state (S101), the BIS request is input to the next stage.

  The row R103 shown in FIG. 4 indicates that the INT request is input to the next stage when the INT request is in the request input waiting state (S103) and the MI request and BIS request are in the request accepting state (S101). Indicates.

  A row R104 illustrated in FIG. 4 indicates that when the MI request, the BIS request, and the INT request are in the request accepting state (S101), the EXT request is input to the next stage. In this way, the priority circuit 25 inputs the request to the next stage in accordance with the priority of MI request> MIS request> INT request> EXT request (indicating that the priority of the larger request indicated by the inequality sign is higher).

  FIG. 5 is a diagram showing an example of pipeline address control, that is, an address control pipeline s. In FIG. 5, the components of the L1 cache 20 shown in FIG. 2 are pipeline stages “P (Priority)”, “T (Tag)”, “M (Match)”, “B (Branch)”, “ R (Result) "and" R1 ". The clock cycle is set based on the longest time among the processing times required for each stage of the pipeline. Thereby, all the stages operate in the same cycle time in synchronization with the clock.

  Each stage of “P (Priority)”, “T (Tag)”, “M (Match)”, “B (Branch)”, “R (Register)”, and “R1” is a staging latch. Logical address registers, PLR (Priority Stage Logical Register), TLR (Tag stage Logical Register), MLR (Match stage Logical Register), BLR (Branch stage Logical Register), BLR (Batch stage Logic Register). stage Logic Reigster). These staging latches, which are logical address registers, synchronize with a clock supplied from the outside, hold the logical address for a certain period, and then supply the logical address to the pipeline address register of the next stage.

  The port register holds an EXT request. The EXT request held in the port register is used as an INT request after the pipeline is stopped.

  MILAR (Move In Logical Address Register) is a register that holds a logical address of data to be written to the tag RAM 30. MIAAR (Move In Absolute Address Register) is a register that holds a physical address of data to be written to the tag RAM 30 when a cache miss occurs. The cache controller 200 sends an MI (Move In) request for requesting the data of the physical address held in the MIAAR to the L2 cache 400 via the L2 request holding unit 195. Data acquired from the L2 cache 400 is written into the tag RAM 30 in response to an MI request.

  A BAAR (Branch Cycle Absolute Address Register) is a register that holds a physical address input to the MIAAR.

  ERAR (Error Address Register) is a register that holds a virtual address when an error occurs in memory access. When a cache miss occurs in the comparison circuit 40, the cache controller 200 reports an error to the L2 cache 400. When an error is reported, the L2 cache 400 issues a request to delete the entry of the cache line in which the error has occurred. This request is called “L2 order”. When the L1 cache 20 receives the L2 order via the L2 order holding unit 190, the L1 cache 20 erases the line in response to the BIS request. The control unit 180 notifies the L2 cache 400 that the line has been erased.

  The T stage includes a TLB 35 and a tag RAM 30. The clock control unit 110 is not included in the pipeline 100, but performs processing in a P or T stage cycle.

  The M stage includes a selection circuit 140. The data RAM 120 is not included in the pipeline 100, but operates in an M stage cycle. The B stage includes an error check circuit 130, a priority circuit 25, and a retransmission request generation unit 150. The R stage includes a circuit that supplies a request to the data buffer 5.

  At the P stage, the priority circuit 25 supplies one of the EXT, BIS, INT, and MI requests selected at the P stage to the TLB 35 and the tag RAM 30 in accordance with the priority order of the truth table shown in FIG.

  FIG. 6 is a diagram illustrating an example of address control by a pipeline when an STV (Store Valid) signal that is a use permission signal is generated using an error check circuit. FIG. 6 does not show the clock control unit 110 and the retransmission request generation unit 150 among the components of the L1 cache 20 shown in FIG.

  When the control signal generation unit 50 is configured to receive the error detection signal from the error check circuit 130 and output the STV signal, the control signal generation unit 50 is disposed at the subsequent stage of the error check circuit 130. As will be described later with reference to FIG. 19, the control signal generation unit 50 is disposed in the pipeline 100 and is not disposed in the vicinity of the data RAM 120. Therefore, since the transmission path between the data RAM 120 and the control signal generation unit 50 is long, the control signal generation unit 50 is arranged not at the M stage but at the B stage. Further, the error check circuit 130 is arranged at the M stage.

  Therefore, the data RAM 120 arranged in the previous stage of the error check circuit 130 is arranged in the T stage, not in the M stage as shown in FIG. As a result, the clock control unit 110 cannot be disposed between the priority circuit 25 and the data RAM 120.

  As described above, the arithmetic processing device 10 includes the retransmission request generation unit 150 instead of the control signal generation unit 50 in the subsequent stage of the error check circuit 130, thereby allowing the clock control unit 110 that performs clock control to the data RAM 120 to be performed. Can be provided. Since the clock control unit 110 does not supply a clock to the data RAM when there is no access to the data held in the data RAM 120, the arithmetic processing unit 10 can reduce the power consumption by providing the clock control unit 110.

  FIG. 7 is a diagram illustrating an example of pipeline address control excluding the clock control unit illustrated in FIG. 5. By removing the clock controller shown in FIG. 5 from the T stage, the data RAM 120 operates at the T stage. The error detected from the error check circuit 130 is received by the retransmission request generation unit 150 outside the pipeline 100, and the retransmission request generation unit 150 can be placed in the M stage by generating a retransmission request. . Therefore, the error check circuit 130 and the retransmission request generation unit 150 in the subsequent stage of the data RAM 120 can be arranged in the M stage, and the STV signal and the RERUN signal can be transmitted in the B stage. Therefore, the R stage for transmitting the STV signal or RERUN signal as shown in FIGS. 5 and 6 can be eliminated.

  In this way, unlike the pipeline control shown in FIG. 6, the pipeline control shown in FIG. 7 enables a data load operation in a shorter cycle time. That is, when the data loading operation in the pipeline control shown in FIG. 6 is a bottleneck for improving the cycle time (operating frequency), the arithmetic processing unit 10 changes to the pipeline control shown in FIG. Cycle time (operating frequency) can be improved.

  FIG. 8 is a diagram illustrating an example of flag control in the pipeline. A pipeline 100b shown in FIG. 8 shows a circuit in the pipeline related to flag signal control. The pipeline 100 b includes an INVERTER 101, a flag signal latch TFLAG (Tag FLAG), MFLAG (Match FLAG), BFLAG (Branch FLAG), RFFLAG (Register FLAG), and a priority circuit 102.

  “P”, “T”, “M”, “B”, “R”, and “R1” stages are staging latches that hold flag signals, flag signal latches TFLAG, MFLAG, BFLAG, and RFLAG Respectively. The flag signal is a control signal indicating status information such as attribute information and identification information generated based on the result of processing the request by the pipeline. The flag signal will be described later with reference to FIG. The flag signal latch has a data input terminal D (Data) terminal to which a flag signal is input, and a control terminal IH (In Hibit) terminal to which a WAIT signal is input. When the WAIT signal input to the IH terminal is at the signal level “low”, the flag signal input from the D terminal of the flag signal latch is written, and the WAIT signal input to the IH terminal is at the signal level “high”. In this case, writing of the flag signal input from the D terminal of the flag signal latch is prohibited.

  In the following, the signal level “low” is referred to as “L”, and the signal level “high” is referred to as “H”.

  The input signal at the IH terminal is a WAIT signal inverted by INVERTER 101 which is a negative circuit. The WAIT signal is a signal for stopping the operation of the pipeline 100, and is generated by the control signal generation unit 50 shown in FIG. Therefore, when the WAIT signal for stopping the pipeline operation becomes “H”, the flag signal is written to the flag signal latch. The conditions for generating the WAIT signal by the control signal generator 50 will be described later with reference to FIG.

  When the priority circuit 25 inputs one of the received requests to the pipeline 100, the flag signal moves in the order of TFLAG, MFLAG, BFLAG, and RFFLAG along with the input of the clock signal. However, when a WAIT signal, which is a pipeline processing stop signal, is supplied to the INVERTER 101, each flag signal latch outputs the flag signal to the holding circuit TW, MW, BW, RW corresponding to each stage together with the input of the clock signal To store.

  Once the pipeline is stopped, when the pipeline is resumed, flag signals are output from the holding circuits TW, MW, BW, and RW, and are again input to the pipeline as an INT request. Since the input is input from the oldest request, it is input in the order of RW, BW, MW, and TW.

  FIG. 9 is a diagram illustrating an example of a flag signal used for pipeline control. The flag signal 1101 is a signal held in TFLAG, MFLAG, BFLAG, and RFFLAG. The flag signal 1101 includes a “VALID” signal, a “port ID” signal, a “pipe ID” signal, a “command part ID” signal, a “retransmission request instruction” signal, and a “retransmission request second time” signal.

  A “VALID” signal of “H” indicates that a valid request is flowing through the pipeline stage. The “port ID (port register-ID)” signal is a signal for specifying the port register shown in FIG. As will be described later with reference to FIG. 17, when the WAIT signal for stopping the pipeline operation becomes “H”, the “VALID” signal of “H” flows through the pipeline.

  The “pipe ID (PIPE-ID)” signal indicates the type of request. For example, a “pipe ID” signal indicating “0x3”, “0x5”, “0xD”, and “0xF” in hexadecimal indicates an MI request, a BIS request, an INT request, and an EXT request, respectively. The “instruction ID (IBR-ID)” signal indicates the number of the instruction execution unit 4 to which the request is returned. The “instruction ID” signal is attached to the EXT request when the instruction execution unit 4 supplies the EXT request to the L1 cache 20.

  The RERUN-REQ signal that is a retransmission request instruction is a signal that is supplied to the pipeline 100 by the instruction execution unit 4 that has received the RERUN signal that is a retransmission request.

  The RERUN-2nd signal that is the second instruction for retransmission request is a signal obtained by decoding 71 when a WID signal that is a flow ID described later indicates 71. “WID = 71” specifies that the previous flow is due to a retransmission request and is a WAITed flow without occurrence of a cache hit or error. In other words, “WID = 71” indicates that the second instruction for retransmission request has already written data into the data buffer 5 in the previous flow, and the current flow is a flow that returns an STV signal. Show. Therefore, the pipeline 100 decodes the WID signal received together with the INT request, thereby setting the RERUN-2nd signal to “H” and flowing the RERUN-2nd signal to each stage of the pipeline as one of the flag signals.

  A flag signal 1102 is a flag signal held in TW, MW, and BW. The attribute or identification information included in the flag signal 1102 is the above-described VALID, port ID, pipe ID, and instruction part ID. The flag signal 1103 is a flag signal held in the RW. The attribute or identification information included in the flag signal 1103 is the above-described VALID, port ID, pipe ID, command unit ID, and WID.

The WID specifies the reason why the pipeline has stopped, and has the following types.
“WID = 10” indicates that the pipeline is interrupted due to a cache miss. The pipeline 100 waits until data is loaded from the L2 cache 400 to the L1 cache 20. “WID = 60” indicates that the pipeline is interrupted due to a TLB miss. “WID = 70” indicates that the pipeline is interrupted due to a cache error. “WID = 71” indicates that the first flow having received the retransmission request is completed without a cache hit and an error.

  FIG. 10 is a truth table that defines the priority of selection of flag signals held in the holding circuits RW, BW, MW, and TW. The priority circuit 102 selects the flag signal held in the flag signal address according to the truth table 1200 shown in FIG. “*” In the truth table 1000 indicates a don't care that is not related to priority determination. “0” in the truth table 1200 indicates that the flag signal is held in the holding circuit. “1” in the truth table 1200 indicates that the flag signal is not held in the holding circuit.

  The flag signal held in the RW is always selected by the priority circuit 102 as shown in the row L1201. The flag signal held in BW is selected by priority circuit 102 when there is no flag signal in RW, as shown in row L1202. The flag signal held in the MW is selected by the priority circuit 102 when there is no flag signal in the BW and RW as shown in the row L1203. The flag signal held in the TW is selected by the priority circuit 102 when there is no flag signal in the MW, BW, and RW, as shown in the row L1203.

  FIG. 11 is a diagram illustrating an example of a TLB. The TLB 35 has M (M is an integer) entries, and each entry includes a valid bit (Valid) indicating whether the entry is valid, a virtual address (VA), and an absolute address (AA). The TLB 35 outputs an entry selection signal for selecting a matching entry by matching the virtual address used for access by the comparison unit 36 with the stored virtual address. The selection unit 37 outputs an absolute address held in the entry selected by the entry selection signal. The output absolute address is supplied to the selection circuit 140.

  As for the virtual address actually used for tag matching, a predetermined lower part is not used for tag matching according to the page size. For example, in the 8 KB page size, the virtual address used for tag matching is 50 bits <63:14> of the 64-bit virtual address. When the virtual address is on the TLB 35, the TLB 35 supplies a TLB hit signal to the control signal generation unit 50 and the retransmission request generation unit 150.

  FIG. 12 is a diagram illustrating an example of a tag RAM. The tag RAM 30 has N (N is an integer) entries, and each entry includes a valid bit (Valid) indicating whether the entry is valid and an absolute address (AA). The decoder 31 of the tag RAM 30 selects an entry by decoding an access address (for example, <13: 7>) that is a part of a 64-bit virtual address. The tag RAM 30 outputs an absolute address from the selected entry. In the case of a set associative cache memory in which the tag RAM has a plurality of ways and an entry of each way is selected for one index, the absolute addresses are output by the number of ways. The output absolute address is output to the selection circuit 140.

  FIG. 13 is a diagram illustrating an example of the data RAM. The data RAM 120 has the same N entries (N is a positive integer) as the tag RAM, and each entry includes data and a parity bit of the data. The decoder 41 of the data RAM 120 decodes an access address that is the same as the access address supplied to the tag RAM 30 and selects an entry. The data RAM 120 outputs data from the selected entry. The output data is supplied to the error check circuit 130 and the selection circuit 140.

  The data RAM 120 may use a plurality of RAMs to form one way when one RAM is not enough to secure the data width of one line. For example, if four RAMs form one way and there are two ways, 4 × 2 = 8 RAMs are required.

  FIG. 14 is a diagram illustrating an example of the clock control unit. The clock control unit 110 includes an OR circuit 111, a latch circuit 112, and a clock buffer 113.

  The OR circuit 111 receives REQ-VAL (REQust-VALid signal, MI-HLD (Move In-HoLD) signal, INT-HLD (INTrupt-HoLD) signal, and latches if any signal is “H”. The Enable signal is supplied to the subsequent clock buffer 113 via the circuit 112. When any signal is “L”, the Enable signal is not supplied to the clock buffer 113.

  The REQ-VAL signal is a signal that becomes “H” when an EXT request is supplied from the instruction execution unit 4. The MI-HLD signal is a signal that becomes “H” when the MI request is in the request input waiting state (S103) of FIG. The INT-HLD signal is a signal that becomes “H” when the INT request is in the request input waiting state (S103) of FIG.

  The clock buffer 113 applies a clock to the data RAM 120 when the output of the AND signal (logical product circuit) of the Enable signal input and the clock becomes “H”.

  Thus, the clock controller 110 applies the clock to the data RAM 120 when any of the REQ-VAL signal, the MI-HLD signal, and the INT-HLD signal is “H”, and all the signals are “L”. When the clock is not applied to the data RAM 120. Therefore, when any one of the EXT request, the INT request, and the MI request is supplied to the priority circuit 25, the clock control unit 110 supplies a clock to the data RAM 120, and when none of the requests is supplied, A clock is not supplied to the RAM 120.

  As described above, the clock control unit 110 can reduce the power consumption of the data RAM by controlling so that the clock is not supplied to the data RAM when there is no access to the data held in the data RAM 120.

  FIG. 15 is a diagram illustrating an example of an error check circuit. As illustrated in FIG. 15, the error check circuit 130 includes an ExOR circuit (negative exclusive OR circuit) 131, an OR circuit (logical sum circuit) 132, and a selection circuit 133.

  When the data read from the data RAM 120 at a time is J bytes, the negative exclusive OR 131 performs a parity check on whether or not the parity is odd using a parity bit for each byte. The ExOR circuit 131 outputs a data parity error signal of “H” when a parity error occurs.

  The OR circuit 132 outputs the logical sum of the data parity error signals for each byte received from the plurality of ExOR circuits 131 to the selection circuit 133 as a data error way signal. If even one of the data parity error signals received by the OR circuit 132 is “H”, the data error way signal becomes “H”.

  The selection circuit 133 receives a tag hit way signal that specifies a way that has caused a cache hit, and selects a data error way signal that is specified by the tag hit way signal. If the selected data error way signal is “H”, this indicates that the data read from the data RAM 120 is an error.

  FIG. 16 is a diagram illustrating an example of a retransmission request generation unit. An example of the retransmission request generation unit 150 is an AND circuit 150a. The AND circuit 150a receives a VALID, an EXT request or an INT request, a retransmission request instruction (RERUN-REQ), a tag hit (TAG-HIT), a TLB hit (TLB-HIT), and an error (ERROR). When the VALID, EXT request or INT request, tag hit, TLB hit, and error are all “H” and the retransmission request instruction is “L”, the AND circuit 150a outputs a RERUN signal of “H”. The input signals of the AND circuit 150a are all generated at the B stage, and the RERUN signal is output via the latch circuit 151 at the R stage, which is the next stage of the B stage.

  As described above, the retransmission request generation unit 150 generates a RERUN signal when an error occurs and the RERUN-REQ signal is not supplied from the instruction execution unit 4.

  FIG. 17 is a diagram illustrating an example of the control signal generation unit. The control signal generation unit 50 includes AND circuits 51, 52, 53, 54 and an OR circuit 55.

  The AND circuit 51 receives the RERUN-REQ signal, the RERUN-2nd signal, the TAG-HIT signal, and the TLB-HIT signal. The AND circuit 51 outputs a signal S51 of “H” when the RERUN-REQ signal, the TAG-HIT signal, and the TLB hit signal are all “H” and the RERUN-2nd signal is “L”.

  When the OR circuit 55 receives any one of the “H” signal S51, the “L” tag hit (TAG-HIT) signal, and the “L” TLB-HIT signal, the OR circuit 55 outputs the “H” signal S55.

  Upon receiving the “H” VALID signal, the “H” EXT request or INT request, and the “L” WAIT signal, the AND circuit 52 outputs the “H” signal S52.

  Upon receiving the “H” signal S55 and the “H” signal S52, the AND circuit 53 outputs the “H” WAIT signal.

  Upon receiving the “L” signal S55 and the “H” signal S52, the AND circuit 54 outputs the “H” STV signal.

  As described above, when receiving the “H” RERUN-REQ signal, the control signal generation unit 50 operates to output the WAIT signal and suppress the output of the STV signal. Upon receiving the “L” RERUN-REQ signal or the “H” RERUN-2nd signal, the control signal generation unit 50 outputs the STV signal, suppresses the output of the WAIT signal, and restarts the pipeline operation. To work.

  As shown in FIG. 8, when the WAIT signal is supplied to the pipeline 100, the INT signal is output. Then, as shown in FIG. 2, the WAIT signal is input to the pipeline 100.

  FIG. 18 is a diagram illustrating an example of pipeline VALID signal processing. The pipeline illustrated in FIG. 18 includes AND circuits 171, 172, and 173. When the “H” WAIT signal is supplied to the AND circuits 171, 172, 173, the outputs of the AND circuits 171, 172, 173 become “L”. Therefore, when the WAIT signal is “H”, propagation of the VALID signal can be suppressed in the pipeline.

  FIG. 19 is a diagram illustrating an example of a circuit arrangement of the arithmetic processing device. As shown in FIG. 19, since the data RAM 120 occupies a large area in the arithmetic processing unit 10, the wiring distance between the area where the data RAM 120 is arranged and the area where the pipeline 100 is arranged is inevitably. become longer. Therefore, by arranging the retransmission request generation unit 150 not in the cache controller 200 but in the vicinity of the data RAM 120, the retransmission request generation unit 150 transmits the retransmission request to the data RAM 120 while generating the retransmission request within the B stage cycle. The retransmission request can be transmitted to the data buffer 5.

  20 and 21 are time charts showing an example of pipeline processing when a retransmission request is issued. 20 and 21 show changes in the signal levels of the RERUN-REQ signal, the STV signal, the WID signal, the SBE signal indicating a data RAM error, the IBR-CE signal indicating data buffer writing, and the RERUN signal.

  In the P stage of the pipeline 100, an EXT request is received.

  In the B stage, the SBE signal becomes “H”, and the IBR-CE signal also becomes “H”. That is, error data is supplied to the data buffer 5.

  As described with reference to FIG. 17, when the RERUN-REQ signal is “L”, the control signal generation unit 50 outputs the “H” STV signal. Therefore, in the R stage, the STV signal becomes “H”.

  As described with reference to FIG. 16, the error signal becomes “H” in the input signal of the retransmission request generation unit 150, so that the RERUN signal becomes “H” in the B stage. Therefore, even if the instruction execution unit 4 receives the STV signal, it simultaneously receives the RERUN signal, thereby discarding the STV signal and avoiding the inconvenience that the instruction execution unit 4 uses the data received in the B stage. I can do it.

  When the ERRUN signal is supplied, the instruction execution unit 4 instructs the resetting of the holding circuits TW, MW, BW, RW and the pipeline VALID signal, whereby the request held by the pipeline 100 disappears, and the pipeline Operation stops.

  In the 13th to 21st cycles, the pipeline 100 receives the BIS request from the L2 cache 400, and the line causing the error in the L1 cache 20 is invalidated. In the 13th to 21st cycles, the process is shown to take two flows for executing the pipeline twice. This is to check that there is a line that needs to be invalidated in the tag RAM in the first flow and to invalidate the tag RAM in the second flow.

  In the P stage of the 21st cycle of the clock in the timing chart of FIG. 21, the instruction execution unit 4 supplies an EXT request to the pipeline. Since the RERUN-REQ signal is supplied together with the supply of the EXT request, the RERUN-REQ signal becomes “H”. As described with reference to FIG. 8, the RERUN-REQ signal propagates through the flag signal latch in each stage, and therefore the RERUN-REQ signal maintains the “H” state in the 21st to 25th cycles.

  In the B stage of the 24th cycle of the clock in the timing chart of FIG. 21, the data RAM error (SBE) is “L”. The WID signal is 10, indicating that the pipeline has been interrupted due to the occurrence of a cache miss. This is because the target line is invalidated in the second flow.

  In the period of 30 to 37 cycles of the clock in the timing chart of FIG. 21, the pipeline 100 receives the MI request from the cache controller 200, and the data loaded from the L2 cache 400 is written to the target line.

  In the 40th cycle of the clock in the timing chart of FIG. 21, the pipeline 100 receives an INT request from the cache controller 200. In response to the INT request, as described in FIG. 8, the flag signal held in the flag signal latch is turned on again. As described with reference to FIG. 9, the RERUN-REQ signal is included in the INT request, and therefore propagates through the flag signal latch in each stage. Therefore, the RERUN-REQ signal maintains the “H” state during the period of 21 to 25 cycles of the clock in the timing chart of FIG.

  In the 43rd cycle of the clock in the timing chart of FIG. 21, the SBE signal is “L”. In the 43rd cycle of the clock, the IBR-CE signal transits to “H”, and the data loaded from the L2 cache 400 is supplied to the data buffer 5. Therefore, the condition that the MI-2nd flow, which is the previous flow, is due to a retransmission request, and is a WAITed flow without a cache hit and error, and the WID signal is “71” in 44 cycles. "become.

  In the period of 47 to 51 cycles of the clock in the timing chart of FIG. 21, the RERUN-REQ signal is included in the INT request and propagates through the flag signal latch in each stage. Therefore, the RERUN-REQ signal maintains the “H” state during the period of 47 to 51 cycles.

  As described with reference to FIG. 9, “WID = 71” is held in the holding circuit RW. Therefore, the input INT request includes “WID = 71”, and “WID = 71” is decoded, so that the RERUN-2nd signal not shown in FIG. 21 becomes “H”.

  When the RERUN-2nd signal becomes “H”, the WAIT signal becomes “L” and the STV signal becomes “H” in the R stage at the 51st cycle of the clock in the timing chart of FIG. become. Therefore, the pipeline 100 is restarted and the instruction execution unit 4 can use the data held in the data buffer 5.

  In the P stage of the 47th cycle of the clock in the timing chart of FIG. 21, upon receiving the “H” RERUN-REQ signal, the control signal generator 50 outputs the STV signal, so that the instruction execution unit 4 Data received in the B stage of the 43rd cycle of the clock in the timing chart of 21 can be used.

  Thus, if an error is avoided by loading data from the L2 cache, the instruction execution unit 4 generates the STV signal at the 51st cycle of the clock in the timing chart of FIG. The data received at the 43rd cycle of the clock can be used. As described above, by supplying the STV signal and the RERUN signal to the instruction execution unit 4, the L1 cache 20 maintains the function of the STV signal even if the error detection circuit 130 does not have the error detection as an input signal. I can do it.

  FIG. 22 is a time chart illustrating an example of pipeline processing when a retransmission request is issued. In the period of 0 to 38 cycles of the clock in the timing chart of FIG. 22, although not shown in FIG. 22, the operation described in FIGS. 20 and 21 is performed.

  In the B stage of the 50th cycle of the clock in the timing chart of FIG. 22, the SBE signal is “H”, but the data is not written to the data buffer 5 because the IBR-CE signal is “L”. This is because normal data has already been sent to the instruction execution unit 4 in 43 cycles. As described above, even if an error occurs in the target line after the data has been normally sent to the instruction execution unit 4, the normal data has already been transmitted, so the invalidation by the BIS request or the L2 cache by the MI request. Processing can be continued without loading data from 400.

2 instruction part 3 execution part 4 instruction execution part 5 data buffer 10 arithmetic processing unit 20 L1 cache 25 priority circuit 30 tag RAM
35 TLB
40 Comparison Circuit 50 Control Signal Generation Unit 100 Pipeline 110 Clock Control Unit 120 Data RAM
DESCRIPTION OF SYMBOLS 130 Error check circuit 140 Selection circuit 150 Retransmission request production | generation part 180 Control part 190 L2 order holding | maintenance part 195 L2 request holding | maintenance part 200 Cache controller 400 L2 cache 500 Main memory

Claims (6)

A first storage unit for storing data;
An error detection unit that detects the occurrence of an error in the data read from the first storage unit;
A second storage unit that stores data read from the first storage unit based on a load request;
When the error detection unit detects the occurrence of an error for the data read from the first storage unit by the load request, the request for resending the load request to the first storage unit is the cycle in which the data error is detected. A retransmission request generator that generates the same cycle;
An instruction execution unit that resends a load request to the first storage unit when an error is detected and a retransmission request is given;
An arithmetic processing apparatus comprising: The arithmetic processing unit further includes a clock control unit that supplies a clock to the first storage unit when a load request to the first storage unit is given,
The arithmetic processing unit according to claim 1, wherein the first storage unit outputs data when a clock is supplied.   The arithmetic processing unit further includes a load request based on the retransmission request when no error is detected by the error detection unit for data read from the first storage unit by the load request based on the retransmission request after the load request is retransmitted. The arithmetic processing apparatus according to claim 1, further comprising a use permission control unit that outputs a use permission signal for the data read by the step to the instruction execution unit. In a control method for an arithmetic processing unit having a first storage unit and a second storage unit,
Reading data from the first storage in response to a load request;
An error detection unit included in the arithmetic processing unit detects an error in the data read from the first storage unit;
When the error detection unit detects the occurrence of an error in the data read from the first storage unit by the load request, the load request retransmission request to the storage unit is made in the same cycle as the cycle in which the data error is detected. Generating step;
When the instruction execution unit included in the arithmetic processing unit receives data in which an error is detected and a retransmission request, the instruction execution unit retransmits the load request to the first storage unit;
A control method for an arithmetic processing unit, comprising: In the control method of the arithmetic processing unit,
The arithmetic processing unit further includes a clock control unit,
5. The method according to claim 4, wherein the clock control unit includes a step of supplying a clock to the first storage unit when a load request to the first storage unit is given. The control method of the arithmetic processing unit is further
After the load request is retransmitted, if the error detection unit detects no error for the data read from the first storage unit by the load request based on the retransmission request, the data read by the load request based on the retransmission request is used. 6. The method according to claim 4, further comprising a step of outputting a permission signal to the instruction execution unit.

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