JPH06119231A - Memory initial cycle control system - Google Patents

Abstract

PURPOSE:To secure reliability of a read/write processing of a dynamic memory by securing an initial cycle time in the dynamic memory. CONSTITUTION:Immediately after a power source is turned on, at the time of read of a ROM 102 from a control part 101, in a series of operation processes for reading and writing a RAM 103, based on a vector address being data which is read out, a read-out cycle of the ROM 102 immediately after the power source is turned on is extended by a ready part 105 until a timer 104 becomes time-over in order to secure an initial cycle time prescribed by the RAM 103, and after the initial cycle of the RAM 103 is finished, control is executed so that a first access from the control part 101 to the RAM 103 is started. In such a way, an initial processing to the RAM 103 and an access processing from the control part 101 to the RAM 103 come not to be overlapped timewise, and a normal operation of read/write to the RAM 103 is secured.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an initial cycle control system for a dynamic RAM in a memory device used in a system, to which a microprocessor or the like is applied.

[0002]

2. Description of the Related Art FIG. 3 shows a conventional processing timing chart of a control unit after power is turned on. Here, it is assumed that the control unit has a self-check cycle period.
A memory device including a program ROM (hereinafter abbreviated as ROM) and a dynamic RAM (hereinafter abbreviated as RAM) will be described below as an example.

In FIG. 3, 501 is a system clock (hereinafter abbreviated as clock signal) of the control unit, 502 is a reset signal, 503 is a ROM read signal, and 504 is a RAM.
Read / write signal. Reference numeral 505 is a self-check cycle period for the control unit, 506 is an initial cycle period for RAM for initializing the RAM to realize a normal read / write operation to the RAM, 507 is a reset period, 508 is a read cycle period for ROM, 509
Is a RAM read / write cycle period.

First, the control section enters a reset state when the reset signal 502 changes from high to low in the reset period 507, and reset is released when the reset signal 502 changes from low to high.

Next, when the reset period 507 ends, the control unit enters the self-check mode, and in the self-check cycle period 505 for the control unit, the self-diagnosis of the control unit itself is performed. Also, the initial cycle period for RAM 506
Also starts at the same time as the control unit self-check cycle period 505 to perform the initialization processing of the RAM. After that, the RAM initial cycle period 506 ends first, and then the control unit self-check cycle period 50
5 ends.

Next, a ROM read cycle period 508
Then, the control unit reads the vector address, which is data, from the ROM. Next, RAM read / write cycle period 5
09, the vector address target device RA
M Read-write processing is performed.

The above is the flow from the reset process to the first read / write process to the RAM. Since the self-check cycle period 505 for the control unit is sufficiently longer than the initial cycle period 506 for the RAM, the initial cycle period 506 for the RAM is called. The RAM read / write cycle period 509 does not overlap. Therefore, the read / write operation of the RAM after the power is turned on is guaranteed without any problem.

[0008]

However, in the above conventional configuration, in the case of the memory device having the following configuration, the dynamic RAM read / write operation at power-on is not guaranteed. Here, it is assumed that the control unit does not have a self-check cycle period, and the control unit and the program ROM
(Hereinafter referred to as ROM) and dynamic RAM (hereinafter referred to as R
An example of a memory device composed of AM will be described.

FIG. 4 shows a conventional processing timing chart of the control unit after the power is turned on. In FIG. 4, reference numeral 601 denotes a system clock of the control unit (hereinafter abbreviated as clock signal), 60
2 is a reset signal, 603 is a ROM read signal, 60
Reference numeral 4 is a RAM read / write signal. 606 is a RAM
Is a RAM initial cycle period for realizing a normal read / write operation to RAM, 607 is a reset period, 608 is a ROM read cycle period, and 609 is a RAM read / write cycle period.

First, the control unit resets the reset period 607.
Then, the reset 602 changes from high to low to enter the reset state, and the change from low to high releases the reset.

Next, when the reset period 607 is completed, the control section performs the ROM read cycle period 608 during the ROM period.
At the same time that the read processing is started from, the RAM initialization processing is started in the RAM initial cycle period 606.

Next, a ROM read cycle period 608
Then, when the control unit reads the vector address which is the data from the ROM, the RAM read / write cycle period 6
09 is a RAM which is the vector address target device
Read / write processing is performed.

The above is the flow from the reset processing to the first read / write processing to the RAM. The RAM initial cycle period 606 is the ROM read cycle period 508 and the RAM read / write cycle period 509.
Since it is sufficiently longer than that of RAM, the RAM initial cycle period 606 and the RAM read / write cycle period 609 overlap. Therefore, when the control unit device target is changed, the read / write operation of the RAM after the power is turned on is not guaranteed.

The present invention solves the above-mentioned conventional problems, and prevents the control section from overlapping by preventing the initial cycle period of the dynamic memory from overlapping with the read / write cycle period of the dynamic memory regardless of the target device of the control unit. Read to dynamic RAM,
It is an object to provide a memory initial cycle control system that guarantees a write operation.

[0015]

In order to solve the above-mentioned problems, the memory initial cycle control system of the present invention uses R
The OM read cycle period 608 is extended by the initial cycle time of the RAM.

[0016]

With the above structure, the RAM read / write cycle period 609 and the RAM initial cycle period 606.
Are not overlapped with each other, the read / write operation of the dynamic RAM is guaranteed, the system runaway can be prevented, and the system reliability can be improved.

[0017]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to the drawings. FIG. 1 is a block diagram for explaining an initial cycle control system of a dynamic RAM in a memory device according to an embodiment of the present invention, and FIG. 2 is a processing timing chart of a control unit after power is turned on.

In FIG. 1, 101 is a central control unit (hereinafter abbreviated as a control unit) such as a microprocessor, 102 is a program ROM (hereinafter abbreviated as ROM), 103 is a dynamic RAM (hereinafter abbreviated as RAM), 104 is a timer, Reference numeral 105 denotes a ready unit that adjusts an access cycle when the control unit 101 accesses the ROM after the power is turned on. Reference numeral 106 denotes a reset line for initializing the control unit 101 and the timer 104, and 107 denotes a master clock (hereinafter referred to as a clock signal) of the control unit 101.
And a clock line supplied to the timer 104, 108 is an overflow line for notifying the timer 104 that the timer 104 has overflowed from the timer 104, 109 is a cycle control signal for accessing the ROM 102 from the control unit 101, and the ready unit 105 Is a ready line for transmission from the control unit 101 to the control unit 101. Again 1
Reference numeral 10 is a ROM read timing line for performing read control from the control unit 101 to the ROM 102, and 111 is a control unit 10.
RAM for controlling read / write from 1 to RAM 103
A read / write timing line for data 112 is a data bus group for transferring read / write data from the control unit 101 to the ROM 102 and the RAM 103.

In FIG. 2, 107a is a control unit clock signal output to the clock line 107, 106a is a reset signal input from the reset line 106 to the control unit 101 and the timer 104, and 110a is a ROM read timing line. A read timing signal for ROM output from the control unit 101 to the ROM 102 on 110, a time-over signal 108a output from the timer 104 to the overflow line, and 109a output from the ready unit 105 to the control unit 101 via the ready line 109. The ready signal 111a is a RAM read / write timing signal output from the control unit 101 to the RAM 103 via the RAM read / write timing line 111.

Reference numeral 121 is a reset period, 122 is a period during which the timer 104 counts, that is, a timer count period, and 123 is a RAM 103.
A RAM initialization cycle period indicating a necessary initialization period after reset, 124 is a ROM read cycle period for reading the ROM 102 from the control unit 101, and 125 is a RAM read / write cycle period for reading the RAM 103 from the control unit 101. .

A description will be given below with reference to FIGS. Here, it is assumed that the timer count period 122 is initialized by the timer 104 so that the timer count period 122 and the RAM initialization cycle period 123 are equal in time.

First, in the reset period 121, the control unit 101 and the timer 104 are initialized by the reset signal 106a through the reset line 106. Next, when the reset signal 106a is released (disable high), RO is a read cycle from the control unit 101 to the ROM 102.
Simultaneously with the start of the M read cycle period 124, the counting operation of the timer 104, that is, the timer count period 122 and the initialization process of the RAM 103, that is, the RAM initialization period 123, start. At this time, the ROM read timing signal 110a
Changes from high to low (active low), control unit 1
The read processing of the ROM 102 is started from 01 via the data bus group 112.

Next, when the RAM initialization cycle period 123 ends, the timer 104 overflows and the time-over signal 108a changes from high to low (active low).

Next, the ready section 105 takes the NOR logic of the ROM read timing signal 110a and the time-over signal 108a, and as a result, the ready signal 109a is obtained.
(Active high) is transmitted to the control unit 101 through the ready line 109.

Next, the control unit 101 fetches the ready signal 109a at the falling edge of the clock signal 107a after the timer count period 122 ends, and the ROM read cycle is performed in two cycles of the clock signal 107a after the timer count period ends. The period 124 is ended.

Next, the first read / write access from the control unit 101 to the RAM 103 is performed in the RAM read / write cycle period 125. In this way, after the power is turned on and after the RAM initialization cycle period 123 is completed, the first read / write access to the RAM 103 is performed, and the read / write operation of the RAM 103 is guaranteed.

[0027]

As described above, according to the present invention, the read / write cycle period and the initial cycle period of the dynamic memory do not overlap each other.
The read / write operation of the dynamic memory is guaranteed, and the system runaway can be prevented, so that the system reliability is improved.

[Brief description of drawings]

FIG. 1 is a block diagram for explaining a memory initial cycle control system according to an embodiment of the present invention.

FIG. 2 is a processing timing chart of the control unit after power is turned on in the same memory initial cycle control system.

FIG. 3 is a processing timing chart of a control unit after power is turned on in the conventional memory initial cycle control system.

FIG. 4 is another processing timing chart of the control unit after power-on in the conventional memory initial cycle control system.

[Explanation of symbols]

 101 control section 102 ROM 103 RAM 104 timer 105 ready section 106 reset line 107 clock line 108 overflow line 109 ready line 110 ROM read timing line 111 RAM read / write timing line 112 data bus group 106a reset signal 107a clock signal 108a time over signal 109a Ready signal 110a ROM read timing signal 111a RAM read / write timing signal 121 Reset period 122 Timer count period 123 RAM initialization cycle period 124 ROM read cycle period 125 RAM read / write cycle period

Claims (1)

[Claims] 1. A program R controlled by a central control unit (hereinafter abbreviated as control unit) such as a microprocessor.
OM (hereinafter abbreviated as ROM), dynamic RAM (hereinafter abbreviated as RAM), a timer that counts the time from immediately after power-on until the initial cycle processing defined in the RAM, and the cycle of the ROM depending on the output result of the timer A ready unit for adjusting the width is provided, and when the ROM is read from the control unit immediately after the power is turned on, the RAM, which is the target device indicated by the vector address, is read / written based on the vector address that is the data read. In order to secure the initial cycle time defined in the RAM in a series of operation processes, the read section of the ROM immediately after power-on is extended by the ready unit until the timer times out, and the read unit of the RAM is extended. After the initial cycle is completed, Memory initial cycle control method and controls to initiate access to the RAM.