JPH01166234A - Memory initialization circuit - Google Patents

Abstract

PURPOSE:To shorten the memory initializing time by securing such a constitution where the addresses, data and write signals for initialization are produced continuously and automatically after an initialization command is once given to a memory module from a CPU and the initialization is performed over the entire area of a memory array. CONSTITUTION:An initialization instruction is set at a specific address of an address 9 and an instruction is given to a memory module 3 from a CPU 1. A timing control part 5 makes an under-initialization signal 14 significant via the command data 11 and switches a write signal 7, the address 9 and the data 24 to the initialization side via selectors 1-3. Then an address counter 17 is started by a control signal 13. The counter 17 counts the signals 14 and applies a write signal 7 based on CP of a clock generating part 4 for initialization to a memory array 22 to write the initialization data 24 for initialization of the head address of the array 22. Hereafter the part 5 counts up the counter 17 with the signal 13 for each cycle time of the array 22 and makes the signal insignificant with the end of initialization. Then the part 5 stops the action of the counter 17 and applies an interruption signal 23 to the CPU 1. Each selector is switched and the access is possible to the CPU 1.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to initialization of memory in a memory module.

[Conventional technology]

Figure 2 shows, for example, the MELFLEX module overview JE
It is a block diagram of a data processing bag W using a conventional memory module shown in ZZ-IL-4332. In the figure, (1) is CPU%, (3) is a memory module, (A) is a memory array, 21 is a system bus for exchanging data between the CPU (1) and the memory array in the memory module (3), (4) is a clock generator, (5) is a timing control unit, and (6) is a Read signal, (7) is a write signal, (8) is a reply signal for the read signal (6) and write signal (7), (9) is an address specifying the memory array (4), αO is a byte or word unit. data (including parity bits).

Next, the operation will be explained. When the 9 sources of the memory module (3) are turned on, the data in the memory array (including parity pits) is not initialized and the data contents are undefined.

When CPU (1) performs a read access to the memory module (3), the parity pit may be undefined depending on the data content, and if a parity check is performed on the CPU (1) side, a parity error will occur. .get cpu
In (1), after power is turned on, it is necessary to initialize the memory array (a) by write access. Below, I will explain about the initialization operation. After the power is turned on, the CPU (1) sets the data αO to an initial pattern (the parity pits are a pattern according to the parity polarity), and sets the memory array (
2) is specified by address (9) and a write signal (7) is applied to the memory array to initialize the start address of the memory array @. The memory module (3) returns a reply signal (8) to the write signal (7) to the CPU (11).
When the reply signal (8) is returned, it is assumed that the initialization for the first address has been completed, and the initialization operation for the next address begins.

Next, leave the contents of data 00 as is, advance the address (9) by one, and apply the write signal (7) again to the memory array so that the data area advanced by one from the first address of the memory array (a) is Initialized. Thereafter, the same operations as described above are repeated to initialize the memory array (a) up to the final address.

[The juncture that the invention attempts to solve]

Conventional memory modules are configured as described above, so it is necessary to initialize each address of the memory array with a command from the PU, so the larger the capacity of the memory array, the longer it takes to initialize. There was a problem that needed to be addressed.

Although a countermeasure against this problem was taken in Japanese Patent Application Laid-Open No. 61-16993, it was not sufficient to prohibit access from the CPU during initialization.

The present invention was developed to solve the above-mentioned problems, and it is an object of the present invention to provide a memory initialization circuit that can initialize a memory at high speed without placing a burden on the CPU.

[Means for solving problems]

The memory initialization circuit according to the present invention generates initialization addresses, data, and write signals within the memory module, so that memory initialization can be performed at high speed without imposing a burden on the CPU. This is what I did.

[Effect]

In this invention, the initialization address, data, and write signal are given to the initialization command memory module only once from the CPU, and thereafter they are automatically generated within the memory module and initialized over the entire area of the memory array. Make sure to do the same.

[Embodiments of the invention]

An embodiment of the present invention will be described below with reference to the drawings.

In FIG. 1, the same reference numerals as in FIG. 2 indicate the same or corresponding parts. In Figure 1, aTJ is a command decoder, (2) is an initialization command that instructs to start initialization, OJ is an address counter control signal, 04) is an initial low/medium signal, and a8 is automatically generated by timing control 2 C61. Initialization write signal, αη is the address counter, (to) is the initialization address that is the output of the address counter αη, Ql, (A), Ql is the selector controlled by the initial low/medium signal 04, (C) is the Initialization data, (to) cpu
This is an interrupt signal given to fil.

Next, the operation will be explained. CPU (1) executes an initialization instruction to memory module (3). The initialization instruction is determined at a specific address (9),
The information is transmitted to the memory module (3) by executing a smart write access. When the memory module (3) receives the initialization command from the CPU (1), the initialization command (2) is sent from the command decoder αn to the timing control unit (6).
) is given to When the timing control unit (6) receives the initialization command (2), it makes the initial low/medium signal α4 significant, and selects the selectors Ql, Q, and Ql from the system bus connection side, respectively, and generates the initial signal ζn inside the memory module. write signal OG for initialization, address for initialization (to), initialization data (
It is switched to the c) side. Due to the above actions. Since the selector is located on the internal connection side, access from the system bus side is disabled.Roughly, the address counter aη starts operating in response to the address counter control signal αj.

The address counter is initially set to the beginning of the memory array @. After the initialization signal o4 becomes significant, the timing control unit (5) applies the initialization write signal OG to the memory array @ based on the clock provided from the clock generation unit (4), and initializes the initialization data @. ? 9 times,
Initialize the starting address of the memory array (a).

Thereafter, the timing control unit (5) increments the address counter α power using the address counter control signal (to) every time the cycle time of the memory array (a) elapses, and sends the periodization write signal OG to the memory array@ give to

When the initialization is completed up to the final address of the memory array (to), the initialization signal α4 is turned off and the address counter (to) is reset.
and gives an interrupt signal to CPU (1).

When CPU (1) receives the interrupt signal @, it can determine that the initialization of the memory module has been completed.

Note that when the initialization signal α4 becomes insignificant, the selector Ql,
The e2TJ becomes the system path connection side again, and the memory array (2) can be accessed from the CPU (1).

〔Effect of the invention〕

As described above, according to the present invention, i is memory initialization h, c
When the memory module receives an initialization command from the PU, it is automatically executed within the memory module, and during initialization, even if there is an incorrect access from the system bus side (from the CPU side), it is prohibited by the selector. Since the time required to initialize the memory can be reduced, and
The load on the CPU can be reduced, and furthermore, the initialized data will not be destroyed even if it is accidentally accessed from the CPU side during initialization.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing a memory initialization circuit according to an embodiment of the present invention, and FIG. 2 is a block diagram of a conventional data processing device. α9 is a command decoder, 07) is an address counter, 1113 is an initialization write signal, (to)
is the initialization address, (c) is the initialization data, 0 theft, ■
, 6℃ is the selector, and the device is the interrupt signal. In addition, in the figures, the same reference numerals indicate the same or equivalent parts.

Claims (1)

[Scope of Claims] In a data processing device equipped with a CPU and a readable and writable memory, a command decoder that generates an initialization start command using an initialization signal from the CPU; , a timing control circuit that generates an address counter control signal and an initializing signal, an address counter that generates an initialization address signal that sequentially specifies initialization addresses when the address counter control signal is present, and an address counter that generates an initialization address signal that sequentially specifies initialization addresses. and the above initialization write signal,
A selector is provided for supplying the initialization address signal and initialization data to the memory and prohibiting access to the memory from the CPU, and while the initialization signal is being generated, the address counter is sequentially incremented to access the memory. A memory initialization circuit characterized by initializing the memory.