JPH06112777A - Data interpolating circuit - Google Patents

Abstract

PURPOSE:To constitute a binary digital data interpolating circuit with small- scale hardware. CONSTITUTION:Input data has the timing made uniform by a data latch circuit 1 and is delayed in a data latch circuit 2 by a half period, and outputs of circuits 1 and 2 are multiplied in coefficient devices 3 and 4 by coefficients. Outputs of devices 3 and 4 are added by an adder 5, and the result is multiplied in a coefficient device 6 by 1/2, and data is delayed by a half period by a D F/F 7 operated by two-fold clock and is outputted, thus interpolating data. Thus, the data interpolating circuit has small-scale hardware and copes with not only two-fold clock but also N-fold clock.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a digital signal processing circuit, and more particularly, to a data interpolating circuit for increasing data to a frequency clock which is an integral multiple of double, triple, ... Regarding

[0002]

2. Description of the Related Art A conventional data interpolating circuit inputs IN data to a data latch circuit 8 as shown in a data interpolating circuit 2 of FIG. 3 and creates data A delayed by one cycle as shown in FIG. . This data A is input to the data delay circuit 9, and data B delayed by two cycles from the IN data is created as shown in FIG. The data B and the data A are added by the adder I to create the interpolation data C as shown in FIG. A data latch circuit in which the interpolation data C and the data B delayed by two cycles are selected by a 2-1 selector circuit 12 with a clock having a duty ratio of 50%, and the data is operated with a clock twice as long as the IN data. The data is latched at 13, and the IN data and the interpolated data are alternately output as shown in FIG. In this way, the conventional data interpolation circuit is constructed.

[0003]

A conventional data interpolation circuit is one data latch circuit, one data delay circuit,
The circuit scale is large because it consists of one adder, 2-1 selector circuit, and one, and two or three interpolation data are created from two data to make the sampling clock frequency an integer multiple of 2 or more. Sometimes, the respective coefficients are multiplied and then added, and the addition result of 2 is multiplied by the sampling frequency by an integer. A selector with an integer multiple input was needed.

[0004]

Therefore, in the present invention, when the data is interpolated in the N signal clock for the above-mentioned purpose, the following means are used.

First, input data is latched by a data latch circuit to align the data timing. Using the (N-1) data delay circuits that operate with the clocks with different phases created by the N signal clock, combine the data with different periods by 1 / N period and the first data latch output. N pieces of data are created, and the N pieces of data are weighted by N coefficient units corresponding to the respective pieces of data. All of them are added by the adder. The data interpolating circuit is configured to latch the data with a data latch circuit operating with a clock of N signals and create a data interpolating output at the same timing of the data.

[0006]

According to the present invention, when the data is interpolated for the doubled clock, two data latch circuits, one data delay circuit and one adder perform the same function as the conventional circuit. Since it is possible to reduce one 2-1 selector circuit, the circuit scale is reduced.

Further, if the present invention is used, not only double,
It is possible to support any integral multiple clock.

[0008]

Embodiment 1 Next, Embodiment 1 of the present invention will be described with reference to FIGS.
Will be described with reference to.

1 is a data latch circuit for aligning data, 2 is a data delay circuit to which a clock having a phase opposite to that of 1 is input in order to delay 1/2 cycle, 3 is a coefficient unit for weighting the output of 2, 4 Is a coefficient unit for weighting the output of 1, 5 is an adder for adding the output of the coefficient units of 3 and 4, 6 is a coefficient unit for multiplying the output of 5 by a coefficient, and 7 is a data latch for aligning the output data of 6. Circuit. Next, the operation will be described.

This circuit is a circuit for interpolating output data of a double clock with respect to input data as shown in FIG. First, input data is latched by the data latch circuit 1 to align the data timing, and the coefficient unit 4
Is multiplied by 1 to create data A shown in FIG. Next, the output of the data latch circuit 1 is delayed by ½ cycle data by the data delay circuit 2 in which the clock of the opposite phase is input and is multiplied by 1 by the coefficient unit 3 to create the data B shown in FIG. The data B and the data A are added by the adder 5. The output from the adder 5 is halved by the coefficient unit 6 configured by bit shift,
The data is latched by the data latch circuit 7 operating with a double clock, and the data is aligned and output. This data serves as a data interpolating circuit that alternately outputs input data and interpolation data as shown in FIG.

Next, a second embodiment of the present invention will be described with reference to FIGS. 6 and 7.

In this embodiment, the data latch circuit 14, the data delay circuit 15 and the data delay circuit 16 are used to output data having a clock cycle three times as long as the input data, and the delay amount is 1/3 cycle. Data A, data B, and data C as shown in FIG. The respective data are input to the coefficient units 17 to 19, multiplied by a factor of 1, 2, and output. Add each coefficient output to adder 2
0 and 21 are used for addition, and the coefficient unit 22 multiplies by 1/4.
The data is latched by the data latch circuit 23 operating at the triple clock, and the data in FIG.
A data interpolation output as shown in UT can be obtained.

The third embodiment will be described with reference to FIGS. 7 and 8.

This embodiment has the same configuration as that of the second embodiment, and since the interpolation data for 4 times the clock is created, each data output is made by the data latch circuit 24 and the data delay circuits 25 to 27. The delay time is made to differ for each ¼ cycle, and the data latch circuit 36 at the final stage is operated with a quadrupled clock. With this configuration, data can be interpolated for the quadruple clock.

[0015]

As described above, according to the present invention, in order to perform data interpolation corresponding to the clock of N signals, 0 / N, 1 /
N, 2 / N ... Create data with different delay times delayed by N-1 / N by a data / delay circuit, multiply the data by coefficients by coefficient multipliers corresponding to each data, and add all of them. To do. By multiplying the added data by a coefficient and latching the data by the data latch circuit operating at the clock of N signals, there is an effect that interpolation data corresponding to the N times clock can be created.

[Brief description of drawings]

FIG. 1 is a data interpolation circuit 1 of the present invention.

FIG. 2 is a timing chart of the data interpolation circuit 1 of the present invention.

FIG. 3 shows a conventional data interpolation circuit 2.

FIG. 4 is a timing diagram of a conventional data interpolation circuit 2.

FIG. 5 is a data interpolation circuit 3 according to the second embodiment of the present invention.

FIG. 6 is a timing chart of the data interpolation circuit 3 according to the second embodiment of the present invention.

FIG. 7 is a data interpolation circuit 4 according to the third embodiment of the present invention.

FIG. 8 is a timing chart of the data interpolation circuit 4 according to the third embodiment of the present invention.

[Explanation of symbols]

1,7,8,13,14,23,24,368 8bit
Data latch circuit 2, 9, 15, 16, 25, 26, 27 8-bit data / data delay circuit 5, 10, 20, 32, 33 8-bit adder 3, 4, 17, 19, 28-31 1-fold coefficient Unit 6,11 1/2 multiplication coefficient unit 12 2-1 selector circuit 21 10 bit adder 34 9 bit adder stage 18 2 multiplication coefficient unit 22,35 1/2 multiplication coefficient unit

Claims (1)

[Claims] 1. In the case of performing data interpolation corresponding to an N signal clock of the data from continuously input data, X + 0 / N, X + 2 / N, X + 2 / N ... X + N-1
Data delay circuit for creating a delay time of / N cycle, a coefficient unit for weighting the data delay output, an adder for adding all of the output of the coefficient unit, and a data latch circuit for latching the adder output A data interpolating circuit having: