JPS6236912A - Noncycle type digital filter - Google Patents

Abstract

PURPOSE:To obtain a noncyclic filter with small circuit scale by using a multiplication circuit in common as to taps having an equal coefficient and utilizing the result of multiplication for a coefficient state of plural taps in a digital filter of transposition type constitution. CONSTITUTION:Three basic circuits i, ii, iii of the transposition type constitution filter having a symmetric coefficient are connected in cascade to constitute the transposition type. A signal zero is inputted to the 1st partial sum circuit in the basic circuit (i) as the 1st partial sum output. The 1st partial sum output at the circuit (i) is obtained by an adder circuit 75 and a delay circuit 82. Then the result of multiplication is accumulated as the ii and iii stages. The result of multiplication of a coefficient h0 in the 1st partial sum output of the iii stage is added by an adder circuit 78, the result is delayed at a delay circuit 85 by a period T and becomes an input signal to the 2nd partial sum circuit of the iii stage. The result of accumulation of all the filter coefficients is obtained at the output of the 2nd partial sum circuit of the (i) stage and the result is outputted at an output terminal 16 as a filter output signal Yn.

Description

[Detailed Description of the Invention] [Field of Application of the Invention] The present invention relates to an acyclic digital filter, and more specifically, an acyclic filter that multiplies a sampled input signal by a plurality of coefficients and accumulates the multiplication results. Regarding.

[Background of the invention]

Acyclic filters have the advantage of making the phase characteristics linear by making the coefficient sizes symmetrical. Therefore,
It is often used in fields where phase linearity is important, such as video signal processing filters and data transmission filters.

The structure of an acyclic filter is a so-called direct type.

Transposed configurations are known. In addition, in the case of an acyclic filter having symmetrical coefficient values, outputs from taps with the same coefficients may be added together (Japanese Unexamined Patent Publication No. 47-12 (161, Japanese Patent Publication No. 55-28446)), or set up (
(Japanese Patent Publication No. 60-16131), the number of multiplication circuits can be halved.

What is the operation of an acyclic filter?

Y, = Σ h i−X, −t ・
...(1) Y,: Filter output X at time t=nT
k: filter input at time t=kT;: first weighting coefficient N of the filter; parameter representing the size of the tap. FIG. 2(a) shows a configuration of equation (1) for the case of 7 taps (N=3). In the same figure, 2 to 7 are delay circuits that delay the input signal xk by a sampling period T;
4 is a weighting coefficient for the input signal X delayed by time T, which is the output of the delay circuits 2 to 7; 3. h-2, h-,, h
a multiplication circuit that multiplies o, h,, h2 and h3;
15 is an adder circuit group that adds the outputs of the multiplier circuits 8 to 14, and 16 is an output terminal of the filter output Y1. Second
Figure (b) shows the same filter in a so-called transposed configuration, in which the multiplication results are accumulated in the opposite direction to that in Figure 2 (a) by addition circuits (24 to 29) and delay circuits (17 to 23). By delaying the delay circuits, the necessary registers (same as the delay circuits) can be shared by the delay circuits 2 to 7 and the adder circuit group 15 in the figure (,), thereby preventing restrictions on the operating speed of the circuits and an increase in the circuit scale. There is.

In a filter with a linear phase characteristic, the coefficients are symmetrical, and equation (1) is expressed as Y −=h a−X, 10Σh −” (x, −, +
−+t) ...(2)h-, =h, (i=1 to N) It is expressed as follows. FIG. 3(a) shows a structure that directly expresses equation (2) (direct form), and FIG. 3(b) shows an example of a structure in a transposed form. In the same figure (a), adder circuits 30, 31.3
Registers (delay circuits) 33, 3 for setting the time of the calculation result output when the calculation time of 2 can be ignored compared to the sampling period T.
4.35 can be omitted, and the multiplication circuit 39 that multiplies the coefficient h0
The output of the delay circuit 4 is input to the . The same applies to the configuration shown in FIG.

The configuration shown in FIG. 3 has the advantage that the number of multiplication circuits is approximately halved because the input signals having the same coefficient are added together in advance and then multiplied by the coefficients. However, since the input signal to the multiplier circuit is the sum of the two input signals xk, the number of bits increases by one bit, causing a problem that the circuit scale of the multiplier circuit increases. In particular, if the multiplication circuit is implemented using a conversion table written in a read-only memory (ROM), the required memory capacity will be twice that of the case shown in Figure 2, and the memory amount of the entire filter, that is, the circuit scale, will not change. There is a problem.

[Purpose of the invention]

An object of the present invention is to provide an acyclic filter with a smaller circuit scale.

A further object of the present invention is to provide an acyclic filter that reduces the required memory amount by half when a multiplication circuit that multiplies coefficients is implemented using a conversion table.

Another object of the present invention is to provide an acyclic filter that can be easily realized using a semiconductor integrated circuit.

[Summary of the invention]

To achieve the above object, the present invention provides a digital filter with a so-called transposed configuration in which an input signal is multiplied by a coefficient value corresponding to each tap coefficient, and the multiplication results are accumulated in the reverse order of the taps. The feature is that a multiplication circuit is shared and the multiplication results are used in coefficient stages of a plurality of taps. This makes it possible to obtain an acyclic filter with a small circuit scale. In particular, in the case of a symmetric coefficient type, the scale of the unit multiplier circuit is smaller than that of conventionally known circuit configurations, and the number of required delay circuits is also reduced.

[Embodiments of the invention]

An embodiment of the present invention will be described below with reference to FIG. Second
In the transposed configuration shown in Figure (b), the input signal is directly multiplied by each tap coefficient value. For taps with the same coefficient value, a multiplication circuit can be used in common. FIG. 1(,) shows the basic circuit configuration of a transposed configuration filter with symmetric coefficients. In the figure, an input signal xk is input to an input terminal 61, and is multiplied by a coefficient value d in a multiplier circuit 62. Multiplier circuit 6
1 (7) Output cover, additional opening %64, 6B, Nen Vi1
1st consisting of 8111165.69. The husband's power is input to the second partial sum circuit. In the first partial sum circuit, input terminal 63
The output of the first partial sum circuit in the previous stage input to the output terminal 62 is added to the output of the multiplication circuit 62, and the delay circuit 65 delays the output by one sampling period T, and outputs a new partial sum output to the output terminal 66. This is used as an input signal to the first partial phase circuit in the next stage.

The second partial sum circuit adds the output of the second partial sum circuit in the next stage inputted to the input terminal 67 and the output of the multiplication port @@62, delays it in the delay circuit 69, and outputs it to the output terminal 70. A new partial sum output is output and is used as an input signal to the second partial sum circuit at the previous stage.

Figure 1(b) shows a 7-tap symmetrical filter as shown in Figure 1(a).
This is an embodiment in which three basic circuits are connected in cascade to form a transposed type. In the basic circuit 1 on the left end, the signal "O" is input to the first partial sum circuit as the first partial sum output of the previous stage, and the adder circuit 75. The first partial sum output of the i-th stage is obtained by the delay circuit 82, and thereafter, the multiplication results are accumulated in the ii-th stage and the iii-th stage sequentially.

The first partial sum output of the second stage is the input signal to the second partial sum circuit of the second stage after the multiplication result of the coefficient value h0 is added in the adder circuit 78 and delayed by the period T in the delay circuit 85. It has become. The output of the second partial sum circuit of the i-th stage is the cumulative result of all filter coefficients, and the filter output signal Y
It is output to the output terminal 16 as 1.

FIG. 1(c) shows a configuration example (in the case of 8 taps) of an acyclic filter having an even number of taps and symmetric coefficients according to the present invention. In this case, the four basic circuits shown in Figure (a) (
x + he 111. It can be realized by cascade connection of iv).

In the embodiments shown in FIGS. 1(b) and 1(Q), the adder circuit 75 of the first partial sum circuit of the leftmost basic circuit i can be omitted, and the output of the multiplier circuit 75 is directly routed to the delay circuit 82.
You may enter

Comparing the circuit of Fig. 1(b) with the conventional circuit of Fig. 3(a) or (b), the number of delay circuits is reduced by about half, and the inputs for coefficient values h□ to h3 are Since the number of signal bits is 1 bit less, the multiplier circuits 71, 72, and 73 have 3 bits.
It can be realized with a smaller logic circuit scale than 8.87.36. When a multiplication circuit is implemented using a conversion table, the number of words in the table corresponds to the number of bits of the input signal of the multiplication circuit, and it can be implemented with one bit, or half the number of words, reducing the total memory amount of the conversion table to approximately It can be halved.

Note that the present invention can be applied to all other taps with equal coefficient values that can be applied in the case of symmetric coefficients, and the scale of the multiplication circuit can be reduced.

Calculate the specific circuit scale. In the case of a logarithmic filter with an 8-bit input signal and 15 taps, if the internal calculation precision is 8 bits, 8 multiplication circuits are required, and the memory capacity of the conversion table is 256 words x 8 bits x 8.
= 16384 bits, and 15 8-bit two-man addition circuits and 15 8-bit registers are also required. The number of logic elements in the 8-bit adder circuit and register is 100 gates.

There are 50 gates, making a total of 2250 gates. With current integrated circuit technology, this circuit scale can easily be reduced to one LSI.
This is something that can be realized. In particular, if the conversion table is constructed from a read-only memory (PRON), a one-chip filter with a small chip area and low cost can be realized. On the other hand, if the conversion table is constructed from a programmable read-only memory (so-called FROM) that can be written by the user, the user can obtain an acyclic filter with desired characteristics as needed.

〔Effect of the invention〕

According to the present invention, in an acyclic filter having the same tap coefficients, the number of multiplier circuits can be reduced without increasing the scale of the multiplier circuit, and the number of delay circuits required in a filter with symmetric coefficients can be reduced compared to the conventionally known number. Since the number can be reduced by about half compared to the above configuration, it is possible to exhibit a great effect in making the acyclic filter mII and economical.

Furthermore, by realizing the multiplication circuit with a conversion table, an acyclic filter can be easily realized as a one-chip integrated circuit, which has a great effect on making the device smaller and more economical.

[Brief explanation of drawings]

FIG. 1 is a block diagram of an embodiment of the present invention, and FIGS. 2 and 3 are block diagrams of a conventional acyclic filter. 1.1.6,61. ．． 63, 66. 67. 70... Input (output) terminal, 2 to 7, 17 to 23, 33, 34° 35
．． 4.2,43,45,52,53,54゜58.59
, 60, 65, 69, 82-88...delay circuit (or register), 15...addition circuit group, 24-29.
30-32, 41. ．． 4-2.44°49-51.55
~57,64.68.75~81...addition circuit.

Claims (1)

[Claims] 1. In an acyclic filter that multiplies a sampled input signal by a plurality of coefficients and accumulates the multiplication results, a plurality of multiplications that multiply different coefficient values connected to the input signal. an adder circuit that adds the output of the multiplier circuit and the partial sum output of the previous stage and accumulates the results up to the coefficient to obtain a new partial sum; and an adder circuit that delays the added output and supplies it to the partial sum circuit of the next stage. 1. An acyclic digital filter comprising a delay circuit, which shares a multiplication circuit for the same coefficient, and supplies its output to a plurality of stages of partial sum circuits. 2. In an acyclic filter with symmetric coefficient values,
It consists of a multiplication circuit that multiplies an input signal by a coefficient value, and first and second partial sum circuits that accumulate the output of the multiplication circuit, and the first
The partial sum circuit adds the output of the first partial sum circuit in the previous stage and uses the output as the input to the first partial sum circuit in the next stage.
The partial profit circuit adds the output of the second partial sum circuit of the next stage and uses the output as the input of the second partial sum circuit of the previous stage,
2. The acyclic digital filter according to claim 1, wherein the number of multiplication circuits is reduced by half. 3. A multiplication circuit according to claim 1 or 2, characterized in that a multiplication circuit for multiplying an input signal by a coefficient value is configured with a conversion table whose address is the input signal and whose content is the multiplication output result. Acyclic digital filter. 4. In an acyclic filter that multiplies a sampled input signal by a plurality of coefficients and accumulates the multiplication results, the multiplication circuit is configured with a conversion table whose address is the input signal and whose content is the accumulation result, An acyclic filter characterized in that the conversion table and the accumulation circuit are configured on the same semiconductor integrated circuit.