JPH06110815A - I/o channel control system - Google Patents

Abstract

PURPOSE:To set a channel program header and a channel command entry in the continuous areas and to read them into the memory of an I/O controller with a single system bus access. CONSTITUTION:A channel program header CPH 2 and a channel command entry CCE 22 are continuously stored in main storage 2. Then the CPU 31 of an I/O controller 3 reads the CPH 21 out of the storage 2 together with the continuous areas including the storage area of the CPH 21. Both the CPH 21 and the CCE 22 are read into the internal memory MEM 33 of the controller 3 with a single access of a system bus 10. Thus the CCE 22 can be read out in advance.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an I / O channel control system applied to an I / O channel device of a computer system which is required to have high performance, and more particularly to I / O channel control system by performing a pre-read of a channel program. The present invention relates to an I / O channel control method that shortens the overhead time of I / O processing.

[0002]

2. Description of the Related Art A conventional I / O channel control system in an I / O channel device of a computer system will be described with reference to FIGS. FIG. 1 is a block diagram showing a configuration of an I / O channel device, and FIG. 3 is a flow chart showing a channel control processing procedure according to a conventional I / O channel control method. The CPU 31 of the I / O controller 3 receives the start I / O (SI) from the CPU 1 that controls the system.
When the instruction O) is received, the processing shown in FIG. 3 is executed.

That is, the CPU 31 of the I / O controller 3
Is a system bus 10 and a bus controller (BC)
First, the channel program header (CPH) 21 is read from the main memory 2 via 32 (step S in FIG. 3).
01), then read the channel program header (C
By referring to the address contained in (PH), the main memory 2 is accessed again and the channel command entry (CCE) 22 is read into the internal memory (MEM) 33 of the I / O controller 3 (step S02 in FIG. 3). Then, the read channel program is analyzed (step S03 in FIG. 3), actual I / O processing is executed (steps S04 to S05 in FIG. 3), and finally, the end result is displayed as a channel program header (CP).
H) is written (step S06 in FIG. 3), and a channel program end interrupt is issued to the CPU 1 (step S07 in FIG. 3).

As described above, in the conventional channel control processing,
Read channel program header (CPH) 21,
Each time the channel command entry (CCE) 22 is read, the system bus 10 is accessed.
Data access from the system bus 10 is usually
Use an appropriately sized block transfer.

[0005]

In the above conventional channel control processing, the channel program header (CPH) is used.
21 read, channel command entry (CCE)
Accessing the system bus 10 is accompanied each time reading 22 or the like.

In a high performance computer system, I / O
Reducing the processing overhead time is important for improving system performance. Internal processing complicated I /
In the case of O processing, the overhead time can be expected to be considerably shortened by improving the performance of the I / O processing processor. However, in the case of simple I / O processing, access to the system bus occupies most of the time, so the performance improvement of the I / O processing processor does not directly contribute to the reduction of the overhead time of the I / O processing.

The present invention has been made in view of the above circumstances,
An object of the present invention is to provide an I / O channel control method in which the number of accesses to the system bus is reduced to reduce the overhead of I / O processing and improve the I / O processing performance of a computer system.

[0008]

According to the present invention, the number of accesses to the system bus can be reduced by reading the channel command entry at the same time as reading the channel program header and performing the read processing of the I / O channel program in advance. The overhead of the I / O processor is reduced.

[0009]

In order to reduce the overhead of I / O processing, it is effective to reduce the number of accesses to the system bus as much as possible. Depending on the I / O, the channel command entry (CCE) may have more data, and if the frequency is high enough, the channel program header (CPH) and the channel command entry (CC
Reading E) into the internal memory of the I / O controller with a single system bus access will reduce overhead.

Therefore, according to the present invention, the channel program header (CPH) and the channel command entry (CCE) are used.
Is set as a continuous area and I can be accessed with a single system bus access.
By reading to the internal memory of the I / O controller and reading the channel program in advance, I / O can be processed only by the firmware processing of the I / O processing processor.
The processor overhead can be reduced.

[0011]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT An embodiment of the present invention will be described below with reference to FIGS. FIG. 1 is a block diagram showing the configuration of a system to which the present invention is applied.

In FIG. 1, reference numeral 1 designates a system control C.
PU, 2 is main memory, 3 is I / O controller (IOC)
And are connected to each other via the system bus 10. 4 is an I controlled by the I / O controller 3
/ O device. Reference numeral 21 is a channel program header (CPH) set in the main memory 2, and 22 is a channel command entry (CCE) similarly set in the main memory 2.
Is. In this embodiment, the channel program header (CPH) 21 and the channel command entry (CCE)
And 22 are stored in a predetermined continuous area. Three
1 to 33 are components of the I / O controller 3.

Of the components of the I / O controller 3, reference numeral 31 is a CPU that controls the I / O controller 3. In this embodiment, the CPU 1 is started by the start I / O, and as shown in FIG. , Channel program header (CPH) 21 and channel command entry (CCE)
22 executes channel program processing having a simultaneous reading processing function. In this processing, C that controls the system control
When a start I / O (SIO) instruction is received from PU1, the channel program header (CP
H) Reading is executed to a predetermined continuous area including the storage address of 21 and the memory (MEM) inside the I / O controller is accessed by one access of the system bus 10.
33 Read into memory.

Reference numeral 32 denotes a system bus controller (BC) which interfaces with the system bus 10.
Data is input to and output from the system bus 10 under the control of the CPU 31. Here, the data block-transferred onto the system bus 10 is fetched, and the memory (MEM) 33
Write in.

Reference numeral 33 denotes a memory (MEM) inside the I / O controller, which is read from the main memory 2 here.
Data of a continuous area including a channel program header (CPH) 21 transferred in blocks on the system bus 10 is written. FIG. 2 shows I according to one embodiment of the present invention.
9 is a flowchart showing a processing procedure of an / O channel control method. Here, the operation of the embodiment of the present invention will be described with reference to FIGS. C of I / O controller 3
When the PU 31 receives a start I / O (SIO) instruction from the CPU 1 that controls the system, the PU 31 executes the process shown in FIG.

First, the channel program header (CPH) 21 is read from the main memory 2 via the system bus 10 and the bus controller (BC) 32 (step S11 in FIG. 2).

At this time, the read access to the main memory 2 is
It is executed for a predetermined continuous area including the storage address of the channel program header (CPH) 21, and is read into the memory (MEM) 33 inside the I / O controller. That is, one access to the system bus 10 causes the channel program header (CPH) 21
The data of the continuous area including is read into the memory (MEM) 33 memory inside the I / O controller.

Next, the CPU 31 confirms the address of the channel command entry (CCE) 22 and stores it in the memory (M
In the data of the above-mentioned continuous area read in EM) 33,
It is checked whether or not the correct channel command entry (CCE) 22 exists (step S12 in FIG. 2).

If the correct channel command entry (CCE) 22 exists, the channel program is analyzed (step S13 in FIG. 2) and the actual I / O processing is executed (steps S15 to S16 in FIG. 2). Finally, the end result is written in CPH (step S17 in FIG. 3), and the CPU
A channel program end interrupt is issued to 1 (step S18 in FIG. 2).

Also, the correct channel command entry (C
When the CE) 22 does not exist, that is, when the channel command entry (CCE) 22 cannot be normally read in advance, the main memory 2 is accessed as in the conventional case.
The channel command entry (CCE) 22 is read into the internal memory (MEM) 33 of the I / O controller 3 (step S14 in FIG. 2), the channel program is analyzed (step S13 in FIG. 2), and the actual I / O processing is executed. Yes (Fig. 2
Steps S15-S16).

As described above, the channel program header (CPH) 21 and the channel command entry (CCE) 22 are continuously stored in the main memory 2, and the CPU 31 of the I / O controller 3 stores the channel program from the main memory 2. When reading the header (CPH) 21, the storage area of the channel program header (CPH) 21 includes an extra area (in a continuous area) to read data from the main memory 2, and the internal memory of the I / O controller 3 is read. (ME
By reading the channel command entry (CCE) 22 in advance by reading the M) 33, it is possible to enter the analysis processing of the channel program with one access of the system bus 10, and the overhead of accessing the system bus 10 is increased. It is possible to reduce by one dose.

In order to reduce the overhead of I / O processing, it is effective to reduce the number of accesses to the system bus as much as possible. Depending on the I / O, the channel command entry (CCE) 22 may have more data. If the frequency is sufficiently high, the channel program header (CPH) 21 and the channel command entry (CCE) 22 can be set to I by one system bus access.
By reading to the memory (MEM) 33 of the / O controller 3, the overhead is shortened.

In the above embodiment, the channel program header (CPH) 21 is set in the continuous area of the main memory 2.
And the channel command entry (CCE) 22 are stored, but the "continuous area" at this time is not necessarily an area where addresses are always continuous, and can be read by one memory access. Including a possible area.

[0024]

As described above in detail, according to the present invention, the channel program header and the channel command entry are set in the continuous area, and the I / O can be performed by one system bus access.
By reading to the internal memory of the O controller and reading the channel program in advance, the overhead of the I / O processor can be shortened only by the firmware processing of the I / O processor.

[Brief description of drawings]

FIG. 1 is a block diagram showing the configuration of a system to which an embodiment of the present invention is applied.

FIG. 2 is a flowchart showing a processing procedure of the above embodiment.

FIG. 3 is a flowchart showing a conventional processing procedure.

[Explanation of symbols]

1 ... CPU, 2 ... main memory, 3 ... I / O controller (I
OC), 4 ... I / O device, 10 ... System bus, 21 ...
Channel program header (CPH), 22 ... Channel command entry (CCE), 31 ... CPU, 32 ... System bus controller (BC), 33 ... Memory (ME
M).

Claims (3)

[Claims] 1. An I / O channel device of a computer system, characterized in that, when reading a channel program header according to an SIO instruction, the channel program header and the channel command entry are simultaneously read by one bus access. / O channel control system. 2. A means for setting a channel program header and a channel command entry in a continuous area on the main memory, and reading the continuous area on the main memory when a start I / O is instructed by the system processing unit. , I / O
Means for setting in the memory in the controller, and the above I /
An I / O channel control system characterized in that the channel program entry is read in advance by means of retrieving a channel command entry from the information of the continuous area read in the memory in the O controller. 3. A means for setting a channel program header and a channel command entry in a continuous area on the main memory, and reading the continuous area on the main memory when a start I / O is instructed by the system processing unit. , I / O
Means for setting in the memory in the controller, and the above I /
Means for determining whether or not the continuous area read into the memory in the O controller includes a correct channel command entry; and when the continuous area includes a correct channel command entry, the channel command entry When the correct channel command entry is not included in the continuous area, the channel command entry reading process is executed, and then the channel command entry analyzing process is executed. An I / O channel control method characterized in that the channel program is read in advance.