JPH06103695B2 - Method of manufacturing integrated circuit - Google Patents

Description

The present invention relates to a method for manufacturing an integrated circuit, and more particularly to a method for manufacturing an integrated circuit including an impurity-doped polysilicon layer.

[Conventional technology]

4 (a) to 4 (e) show a conventional method for manufacturing an integrated circuit, especially a general manufacturing method for obtaining a transistor.

First, as shown in FIG. 4 (a), the semiconductor substrate 1 is thermally oxidized to form the first oxide film layer 2, and then a part of the first oxide film layer 2 is partially removed by a normal photo-etching method. Etching away,
Open the base diffusion window. Then, an impurity exhibiting one conductivity type (for example, “B ⁺ ”, 30 KeV, 5 × 10 ¹³ / cm ² ) is implanted into the semiconductor substrate 1 by a normal ion implantation method, and then low temperature annealing (for example, 900 ° C. 20 ° C.) is performed. Then, the base diffusion layer 3 is formed.

Next, after forming a second oxide film layer 4 having a thickness of 0.5 μm by a normal vapor phase growth method, a part of the second oxide film layer 4 is removed by etching by a normal photo-etching method. The emitter diffusion window and the base contact diffusion layer are opened as shown in FIG.

Next, as shown in FIG. 4 (c), by a normal vapor phase growth method,
After forming the polysilicon layer 5 having a thickness of 0.15 μm, an impurity exhibiting one conductivity type (eg, “As ⁺ ”, 50 KeV, 1 × 10 ¹⁶ / cm ² ) is implanted into the polysilicon layer 5 by a normal ion implantation method. After this, the low temperature heat treatment (700 to 800 ° C.) is performed to recover the crystallinity of the polysilicon layer 5 and make the impurity distribution of the ion implantation layer uniform.

Next, as shown in FIG. 4 (b), a part of the polysilicon layer 5 was removed by etching with a solution of fluorinated nitric acid by a usual photo-etching method using a photoresist, and then used as an etching mask. Impurities exhibiting the same conductivity type (eg, "B ⁺ ", 30 KeV, 1) in a part of the semiconductor substrate 1 by the normal ion implantation method using the photoresist 10 as a mask as it is.
X 10 ¹⁵ / cm ² ) and then the base contact diffusion layer 7
To form.

Then, after removing the photoresist 10, 1 at 950-1000 ℃
Heat treatment is performed for about 5 to 60 minutes to diffuse impurities from the polysilicon layer 5 to form the emitter diffusion layer 6 and to anneal the base contact diffusion layer 7.

Finally, as shown in FIG. 4 (e), an electrode metal for extracting the characteristic is deposited and then shaped and separated to form a base electrode 9 and an emitter electrode 8.

[Problems to be solved by the invention]

In the conventional manufacturing method described above, As to the polysilicon layer 5 is
^{Since +} ion implantation is performed only under one condition, the profile becomes steep as shown in FIG. For this reason,
In the etching process of the polysilicon layer 5 shown in FIG. 4 (d), since the etching rate of the polysilicon with the fluorinated nitric acid solution has a property proportional to the impurity concentration, the etching cross-section inclination of the polysilicon layer 5 is increased. Corners 70-80
It becomes steep. Thereby, the polysilicon layer 5
There is a problem that breakage of the wiring electrode formed on the upper side, metal residue, metal fin, etc. during the processing of the wiring electrode are likely to occur, resulting in a decrease in product yield, non-defective product rate, or deterioration in reliability.

It is an object of the present invention to provide a method for manufacturing an integrated circuit which can reduce the inclination angle of the etching cross section in the polysilicon layer and improve the reliability of the upper layer wiring to improve the product yield and reliability.

[Means for solving problems]

A method of manufacturing an integrated circuit according to the present invention comprises a step of forming a polysilicon layer on a semiconductor substrate, a step of introducing impurities into the polysilicon layer, and a step of heat-treating the polysilicon layer and then etching. In addition, the step of introducing impurities into the polysilicon layer is performed on the entire surface of the polysilicon layer under conditions of different dose amounts and different ion implantation energies so as to increase the impurity concentration on the surface, and impurities after heat treatment are included. The characteristics are relaxed profile,
In addition, the etching sidewall cross-section inclination angle of the etched polysilicon layer is made gentle along the impurity profile characteristics.

〔Example〕

 Next, the present invention will be described with reference to the drawings.

1A to 1C are cross-sectional views showing an embodiment of the present invention in the order of manufacturing steps, and here, an example of manufacturing a transistor is shown.

First, in FIG. 1 (a), FIG.
The first oxide film layer 2, the base diffusion layer 3, the second oxide film layer 4, and the polysilicon layer 5 are formed on the semiconductor substrate 1 in the same manner as the conventional manufacturing method shown in FIG. Then, an impurity exhibiting one conductivity type is formed in the polysilicon layer 5 by an ion implantation method,
For example, "As ⁺ " is introduced. At this time, at the time of ion implantation, at least two or more conditions with different dose amounts, here three different conditions (for example, 10 KeV, 1 × 10 ¹⁶ / c)
Implantation is performed at m ² , 30 KeV, 5 × 10 ¹⁴ / cm ² , 60 KeV, 1 × 10 ¹³ / cm ² . After that, low temperature heat treatment (700 ~ 800
C.) to increase the surface impurity concentration of the polysilicon layer 5.

Next, as shown in FIG. 1 (b), a part of the polysilicon layer 5 is removed by etching with a fluorinated nitric acid-based solution by a usual photo-etching method, and then the photoresist 10 used as an etching mask is left as it is. The base contact layer 7 is formed by implanting impurities (for example, "B ⁺ ", 30 KeV, 1 × 10 ¹⁵ / cm ² ) having the same conductivity type into a part of the semiconductor substrate 1 by using a mask as a mask by a normal ion implantation method. To do.

Thereafter, as shown in FIG. 1C, the emitter diffusion layer 6, the base electrode 9 and the emitter electrode 8 are formed in the same manner as in the conventional manufacturing method.
To form.

According to this manufacturing method, in particular, in the step of FIG. 1A, the ion implantation of impurities into the polysilicon layer 5 is performed under three different conditions. Therefore, the impurity profile after the heat treatment is as shown in FIG. Moreover, the characteristics are relaxed compared to the conventional one. Therefore, in the etching step of the polysilicon layer 5 in the step of FIG. 1B, the etching rate of the fluorinated nitric acid-based etching solution has a magnitude according to this impurity profile, and as a result, the etching processing of the polysilicon layer 5 is performed. The cross-sectional inclination angle can be relaxed to 50-60 °.

Therefore, it is possible to suppress the disconnection failure of the wiring electrode formed on the polysilicon layer 5, the generation of metal residue and metal whiskers at the time of processing the wiring electrode, improve the product yield and the yield rate, and greatly improve the reliability. Is possible.

FIGS. 3A to 3C are sectional views showing another embodiment of the present invention in the order of steps, and here, an example of manufacturing a polysilicon resistor is shown.

First, as shown in FIG. 3A, the semiconductor substrate 1 is thermally oxidized to form a first oxide film layer 2, and then a polysilicon layer 5A having a thickness of 0.3 μ is formed by a normal vapor phase growth method. .

Next, an impurity exhibiting one conductivity type is introduced into the polysilicon layer 5A by the ion implantation method. At this time, the ion implantation should be performed under two or more conditions with different ion implantation energies (eg, “P ⁺ ”, 10 KeV, 3 × 10 ¹⁵ / cm ² , 30 KeV, 1
After implanting at × 10 ¹⁴ / cm ² , 50 KeV, 1 × 10 ¹³ / cm ² ),
A low temperature heat treatment (700 to 800 ° C.) is performed to increase the surface impurity concentration of the polysilicon layer 5A.

Next, as shown in FIG. 3 (b), the polysilicon layer 5A other than the resistance pattern region is removed by etching using RIE (anisotropic etching, gas conditions such as ccl ₄ + O ₂ ) by a normal photo-etching method. After that, the thickness is 0.3μ by the normal vapor phase growth method.
To form the second oxide film layer 4.

Next, as shown in FIG. 3 (c), a part of the second oxide film layer 4 on the polysilicon layer 5A serving as a polysilicon resistor is removed by etching, a contact window is opened, and then characteristics are extracted. The wiring electrode 11 is formed.

Also in this embodiment, the impurity ions are implanted into the polysilicon layer 5A under three different conditions.
It is possible to obtain the same impurity profile as the example shown in the figure, relax the cross-sectional inclination angle in this etching,
It is possible to mitigate the step difference in the upper second oxide film layer 4 and prevent disconnection and other problems in the wiring electrode thereabove.

The present invention can be similarly applied to the manufacture of devices other than those described above as long as the device is provided with a polysilicon layer into which impurities are introduced.

〔The invention's effect〕

As described above, according to the present invention, the step of introducing impurities into the polysilicon layer formed on the semiconductor substrate is performed under two or more conditions in which at least one of the dose amount and the ion implantation energy is different. It is possible to reduce the impurity profile in the process, reduce the polysilicon processing cross-section inclination angle after etching with a fluorinated nitric acid solution, and prevent disconnection defects of the wiring electrodes formed in the upper layer. It is possible to improve the decrease in product yield and the decrease in non-defective product rate due to metal residue and metal whiskers, and to significantly improve reliability.

[Brief description of drawings]

1 (a) to 1 (c) are sectional views showing an embodiment of the present invention in the order of steps, FIG. 2 is an impurity profile of a polysilicon layer to which the present invention is applied, and FIGS. 3 (c) is a sectional view showing another embodiment of the present invention in the order of steps, FIGS. 4 (a) to 4 (e) are sectional views showing the conventional method in the order of steps, and FIG. 5 is the conventional method. 3 is an impurity profile of a polysilicon layer to which is applied. 1 ... Semiconductor substrate, 2 ... First oxide film, 3 ... Base diffusion layer, 4 ... Second oxide film, 5, 5A ... Polysilicon layer, 6 ... Emitter diffusion layer, 7 ... Base contact layer, 8 ... Emitter Electrode, 9 ... Base electrode, 10 ... Photoresist, 11 ... Wiring electrode.

Claims (1)

[Claims] 1. A step of forming a polysilicon layer on a semiconductor substrate, and a step of introducing impurities into the polysilicon layer,
A step of subjecting the polysilicon layer to a heat treatment and an etching process, and the step of introducing impurities into the polysilicon layer is performed under conditions of different dose amounts and different ion implantation energies so as to increase the surface impurity concentration. The impurity profile after the heat treatment is relaxed on the entire surface of the polysilicon layer, and the etching sidewall cross-section inclination angle of the etched polysilicon layer is made gentle along the impurity profile characteristics. A method of manufacturing a featured integrated circuit.