JPH06103105A - Simultaneous debug processor for inter-task shared routine - Google Patents

Abstract

PURPOSE:To improve the productivity of a program by constituting the processor so that debug can be executed in each independent environment by plural terminals, that is, by plural tasks, for instance, by an on-line program, etc., using an inter-task shared routine, in the case of executing simultaneously in parallel debug of the program using the inter-task shared routine. CONSTITUTION:In the case of executing simultaneously debug to plural tasks 1, 2 by using an inter-task shared routine 5, an exclusive control part 3 avoids an interrupting instruction write operation for setting a stop point, and simultaneous write by a multi-task by an operation for saving and recovering the original instruction, in order to give an independent debug environment to every task 1, 2. A stop control part 4 discriminates an interruption to the own task, when the interruption is generated, and executes decision control for a stop and continuation.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an inter-task shared routine simultaneous debug processing device, and in particular, a transaction of each terminal is assigned to one task by an online program or the like to execute individual independent processing. The present invention relates to an inter-task shared routine simultaneous debug processing device in an execution environment.

[0002]

2. Description of the Related Art A conventional inter-task shared routine simultaneous debug processing device, when using a program utilizing an inter-task shared routine, starts debugging with one terminal, that is, one task, and stops the execution of the program. Since the task also stops, the debugging is limited to one terminal, and the other terminals have to wait until the end of debugging.

[0003]

In the conventional inter-task sharing routine simultaneous debug processing device described above, when a program shared between tasks is simultaneously debugged by a plurality of tasks, a stop point required by each task is set. Occurs randomly, and interrupt instructions for setting the stop points of multiple tasks are written in one program.
Exclusive control for avoiding simultaneous writing from a plurality of tasks is required at the time of writing an interrupt instruction for setting a stop point in each task and saving and restoring the original instruction.

Further, in the conventional inter-task shared routine simultaneous debug processing device, since interrupt instructions of a plurality of tasks are written in one program, when an interrupt occurs, the non-self task is ignored and the program is executed. Since the execution must be continued without stopping, it is necessary to identify the interrupt at the stop point for the invoking task.

[0005]

According to a first aspect of the present invention, there is provided an inter-task shared routine simultaneous debug processing device, wherein when a plurality of tasks are simultaneously debugged using an inter-task shared routine, independent debugging is performed for each task. Simultaneous debugging routine between tasks for providing environment avoids simultaneous writing by multitasking in interrupt instruction writing operation for setting breakpoint and original instruction saving and restoring operation in program debugging It has an exclusive control unit.

Further, the inter-task shared routine simultaneous debug processing apparatus of the second invention is the inter-task shared routine simultaneous debug processing apparatus of the first invention, in which an interrupt for its own task occurs when an interrupt event occurs after writing an interrupt instruction. And a stop control unit for performing stop / continuation determination control.

[0007]

Embodiments of the present invention will now be described with reference to the drawings.

FIG. 1 is a block diagram showing an embodiment of the first invention having an exclusive control unit for writing an interrupt instruction. Further, FIG. 2 is a block diagram showing an embodiment of the second invention having a stop control unit when an interrupt event occurs.

As shown in FIG. 1, the interrupt instruction write operation is performed as follows.

When the task 1 requests the setting of the stop point on the 30th line, the exclusive control unit 3 locks the program in order to make the writing operation from the other task 2 wait.

When the interrupt generation instruction is written in the 30th line, the original execution instruction is simultaneously saved in the instruction save area 6,
Also record identification information such as the task name.

When a stop point setting request is issued from the task 2 to the 90th line, the exclusive control unit 3 waits because the program is already locked. When the write operation in task 1 is completed, the exclusive control unit 3 unlocks the program and releases the write wait of another task 2.

The task 2 is released from the waiting state, the interrupt instruction is written on the 90th line, and predetermined information is recorded in the instruction save area 6 in the same manner as the task 1.

As shown in FIG. 2, the operation when an interrupt occurs is performed as follows.

When the 30th line of the program is executed in task 1, an interrupt occurs, and this event is caused by the stop control unit 4
Recognized in.

The stop control unit 4 refers to the instruction save area 6 from the line number at which the interrupt event occurred, and recognizes that the interrupt is related to task 1. Furthermore, since the name of the task currently being executed is task 1, it is determined that the interrupt is for its own task, and the program is stopped. When the continuation is requested after the program is stopped, the original instruction in the instruction save area 6 is executed and the program is continued.

Then, when the program continues to be executed in task 1, an interrupt event occurs at the 90th line and the stop control unit 4 recognizes this event.

The stop control unit 4 judges in which task the interrupt event occurred, and the event occurred in the task 2. The task name in the 90th line of the instruction save area 6 and the own task name (task 1 ) Are different, continue the original instruction without stopping the program.

Also in the execution of task 2, the stop control unit 4 operates when an interrupt event occurs, and an independent debug environment is realized by parallel processing without being affected by other tasks.

[0020]

As described above, in the inter-task shared routine simultaneous debug processing apparatus of the present invention, one task is assigned to each terminal for an online program,
Since they are executed as independent processes, each terminal is provided with an independent debug environment, enabling simultaneous debugging on multiple terminals, which improves memory usage efficiency and significantly improves productivity during debugging. There is an effect such as various improvements.

[Brief description of drawings]

FIG. 1 is a block diagram showing an embodiment of a first invention.

FIG. 2 is a block diagram showing an embodiment of the second invention.

[Explanation of symbols]

 1, 2 tasks 3 exclusive control unit 4 stop control unit 5 shared task routine 6 instruction save area

Claims (2)

[Claims] 1. An inter-task shared routine simultaneous debug processor for providing an independent debug environment for each task when a plurality of tasks are simultaneously debugged by using the inter-task shared routine. An inter-task shared routine simultaneous debug processing apparatus having an exclusive control unit for avoiding simultaneous writing by multitasking at the time of writing an interrupt instruction for setting a stop point and saving and restoring the original instruction. 2. The inter-task task according to claim 1, further comprising a stop control unit for identifying an interrupt for an own task and performing stop / continuation determination control when an interrupt event occurs after writing an interrupt instruction. Shared routine simultaneous debug processor.