CN114661543A - Method and device for eliminating interrupt false triggering of multi-core DSP - Google Patents

Method and device for eliminating interrupt false triggering of multi-core DSP Download PDF

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Publication number
CN114661543A
CN114661543A CN202210175352.5A CN202210175352A CN114661543A CN 114661543 A CN114661543 A CN 114661543A CN 202210175352 A CN202210175352 A CN 202210175352A CN 114661543 A CN114661543 A CN 114661543A
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core
interrupt
false triggering
dsp
value
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陈令刚
连志鹏
彭惠
陈鸿跃
曹全
徐云辉
段祉鸿
刘希强
董彦维
朱曦曼
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Beijing Institute of Space Launch Technology
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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/30—Monitoring
    • G06F11/3003—Monitoring arrangements specially adapted to the computing system or computing system component being monitored
    • G06F11/302—Monitoring arrangements specially adapted to the computing system or computing system component being monitored where the computing system component is a software system
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/30—Monitoring
    • G06F11/3065—Monitoring arrangements determined by the means or processing involved in reporting the monitored data

Abstract

The invention provides a method and a device for eliminating interrupt false triggering of a multi-core DSP. The method comprises the following steps: setting an interrupt tag L corresponding to a core nnN is 1, …, N-1, N is the number of cores in the multi-core DSP; setting L in interrupt service routine for core 0n1, N-1, …, N-1; at the start of the interrupt service routine for core n, read LnA value of (A) if LnWhen the value is 1, then L is addednClearing and executing subsequent program codes; if L isnWhen the value is equal to 0, directly quitting the interrupt program; n-1, 2, …, N-1. The invention effectively solves the problem of interrupt repeated false triggering among the cores of the multi-core DSP embedded software, ensures that the interrupt service program immediately exits when a certain core generates interrupt repeated false triggering, does not generate false triggering on the subsequent core any more, can ensure that the core program and other core programs stably run, and ensures the high running reliability of the multi-core DSP embedded software system.

Description

Method and device for eliminating interrupt false triggering of multi-core DSP
Technical Field
The invention belongs to the technical field of computer interruption, and particularly relates to a method and a main device for eliminating interruption false triggering of a multi-core DSP.
Background
At present, the application of multi-core computers is more and more extensive. For example, an internal navigation computer board of a positioning and directional aiming system (hereinafter referred to as a positioning and directional aiming system) is provided with 4 cores, namely core 0, core 1, core 2 and core 3, by using a multi-core DSP (TMS320C 6674). Each core runs its own software program, and the interaction of data and instructions between cores is generally handled in response by an inter-core interrupt method. The sequence of the inter-core interruption is started by a core 0, the core 0 triggers a core 1, the core 1 triggers a core 2, and the core 2 triggers a core 3, wherein the core 0 is triggered by the interruption of a timer every 1ms, so that the phenomenon of repeated false triggering can be avoided, but each core in the subsequent cores 1,2 and 3 can have the phenomenon of repeated false triggering, so that the following false triggering phenomenon is generated when other cores respond to the inter-core interruption, and the system software is unstable in operation; which in severe cases can cause software crash of some cores.
Disclosure of Invention
In order to solve the above problems in the prior art, the present invention provides a method and an apparatus for eliminating false triggering of multi-core DSP interrupt.
In order to achieve the above object, the present invention adopts the following technical solutions.
In a first aspect, the present invention provides a method for eliminating interrupt false triggering of a multi-core DSP, including:
setting an interrupt tag L corresponding to a core nnN is 1, …, N-1, N is the number of cores in the multi-core DSP;
interrupt garment at core 0Set L in the service programn＝1，n＝1,…,N-1；
At the start of the interrupt service routine for core n, read LnA value of (A) if LnWhen the value is 1, then L is addednClearing and executing subsequent program codes; if L isnWhen the value is equal to 0, directly quitting the interrupt program; n-1, 2, …, N-1.
Further, the interrupt of core 0 is triggered by a timer interrupt.
Further, a core N interrupt is triggered before core (N-1) exits its interrupt service routine, N-1, ….
Further, the interruption tag LnThe setting method comprises the following steps: adding an array Label [ N-1 ] after the original data and command parameter areas of the shared memory area of the multi-core DSP]，Ln＝Label[n-1]，n＝1,…,N-1。
Further, the method further comprises: if L isnAnd sending prompt information about repeated false triggering of the core N, wherein N is 1,2, … and N-1, and exiting the interrupt program.
Further, N ═ 4.
In a second aspect, the present invention provides an apparatus for eliminating interrupt false triggering of a multi-core DSP, including:
a tag setting module for setting an interrupt tag L corresponding to the core nnN is 1, …, N-1, N is the number of cores in the multi-core DSP;
a tag assignment module for setting L in interrupt service routine of core 0n＝1，n＝1,…,N-1；
A false trigger judgment module for reading L at the start of interrupt service program of core nnIf L is a value ofnWhen the value is 1, then L is addednClearing and executing subsequent program codes; if L isnWhen the value is equal to 0, directly quitting the interrupt program; n-1, 2, …, N-1.
Further, the core 0 interrupt is triggered by a timer interrupt.
Further, a core N interrupt is triggered before core (N-1) exits its interrupt service routine, N-1, …, N-1.
Further, the interruption tag LnThe setting method comprises the following steps: in multiple coresAdding array Label [ N-1 ] behind original data and command parameter areas of shared memory areas of DSP]，Ln＝Label[n-1]，n＝1,…,N-1。
Further, the method further comprises: if L isnAnd sending prompt information about repeated false triggering of the core N, wherein N is 1,2, … and N-1, and exiting the interrupt program.
Further, N ═ 4.
Compared with the prior art, the invention has the following beneficial effects.
The invention sets the interrupt label L corresponding to the core nnSetting L in interrupt service routine of core 0n1, at the start of the interrupt service routine for core n, read LnA value of (A) if LnWhen the value is 1, then L is addednClearing, executing subsequent program codes, if LnAnd (5) directly quitting the interrupt program to be 0, and realizing the inter-core interrupt of the multi-core DSP. The invention effectively solves the problem of interrupt repeated false triggering among the cores of the multi-core DSP embedded software, and when a certain core generates interrupt repeated false triggering, the interrupt service program immediately exits without generating false triggering on the subsequent core, so that the core program and other core programs can stably run, and the high running reliability of the multi-core DSP embedded software system is ensured.
Drawings
Fig. 1 is a flowchart of a method for eliminating interrupt false triggering of a multi-core DSP according to an embodiment of the present invention.
FIG. 2 is a diagram illustrating the interrupt execution relationship between 4-core DSP cores.
FIG. 3 is a schematic diagram of a 4-core DSP inter-core interrupt response flow.
FIG. 4 is a block diagram of an apparatus for eliminating interrupt false triggering of a multi-core DSP according to an embodiment of the present invention.
Detailed Description
In order to make the objects, technical solutions and advantages of the present invention clearer and more obvious, the present invention is further described below with reference to the accompanying drawings and the detailed description. It is to be understood that the described embodiments are merely exemplary of the invention, and not restrictive of the full scope of the invention. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
Fig. 1 is a flowchart of a method for eliminating interrupt false triggering of a multi-core DSP according to an embodiment of the present invention, including the following steps:
step 101, setting an interrupt label L corresponding to a core nnN is 1, …, N-1, N is the number of cores in the multi-core DSP;
step 102, set L in interrupt service routine of core 0n＝1，n＝1,…,N-1；
Step 103, at the start of the interrupt service routine for core n, reads LnA value of (A) if LnIf 1, then LnClearing and executing subsequent program codes; if L isnWhen the value is equal to 0, directly quitting the interrupt program; n-1, 2, …, N-1.
The embodiment provides a method for eliminating interrupt false triggering of a multi-core DSP. The multi-core DSP is provided with a plurality of cores, each core runs a respective software program, and interaction of data and instructions among different cores is generally responded and processed in an inter-core interrupt mode. The inter-core interrupts are sequentially executed according to a set sequence, for example, the interrupts start from core 0, core 0 triggers core 1, core 1 triggers core 2, and so on. Since core 0 is not triggered by other cores (e.g., its interrupt may be triggered every 1ms by a timer interrupt), the interrupt of core 0 generally does not have a repetitive false trigger. However, the interrupt repeated false triggering phenomenon can occur in the interrupt of the subsequent core 1, the subsequent core 2 and the like, and the following false triggering phenomenon is caused when other cores respond to the inter-core interrupt, so that the system software is unstable in operation; severe cases may result in software crashes for some cores. Therefore, the embodiment provides a method for solving the problem of inter-core interrupt false triggering of the multi-core DSP embedded software, which is suitable for the situation of inter-core interrupt repeated false triggering in the inter-core interrupt process.
In this embodiment, step 101 is mainly used to set an interrupt tag. The purpose of setting the interrupt tag is to judge whether the corresponding core interrupt is triggered or not according to different values (such as 0 and 1), and on the basis, certain measures are taken to eliminate the influence of false triggering. In this embodiment, the total number of kernels is assumed to be N, where N is greater than or equal to 2; n number ofThe cores are sequentially called core 0, core 1, …, core (N-1); the execution sequence of the N core interrupts is core 0, core 1, … and core (N-1) in sequence, namely, the core 0 interrupt is triggered first, the core 1 interrupt is triggered before the interrupt service program exits, the core 1 triggers the core 2 interrupt again, and so on until the core (N-1) is triggered. Therefore, the interrupt of only core 0 is not triggered by the interrupts of other cores, so the interrupt of core 0 generally does not have the repeated false triggering phenomenon. Therefore, in the embodiment, one interrupt tag is set for each core except for the core 0 in the multi-core DSP, that is, a total of (N-1) tags are set. To avoid loss of generality, the interrupt tag corresponding to core n is marked as LnWherein N is 1, …, N-1.
In this embodiment, step 102 is mainly used to modify the interrupt service routine of core 0. As previously mentioned, core 0 has specificity compared to the other (N-1) cores, and thus modification of the core 0 interrupt service routine is also required to be performed separately from modification of the other core interrupt service routines. In this embodiment, the modification method for the kernel 0 interrupt service routine is as follows: setting the value of all interrupt tags to 1, i.e. setting L n1, N is 1, …, N-1. In this embodiment, a value of 1 for the interrupt tag indicates that the interrupt of the corresponding core has not been triggered, and a value of 0 for the interrupt tag indicates that the interrupt of the corresponding core has been triggered. Of course, 0 may be used to indicate that the trigger is not triggered, 1 may be used to indicate that the trigger is triggered, and other numbers different from 0 and 1 may be used for distinction.
In this embodiment, step 103 is mainly used to modify the interrupt service routine of other cores. The modification methods of the interrupt service programs of the core 1 to the core (N-1) are the same, and the value L of the interrupt label corresponding to the core is read at the beginning of the interrupt service programnIf L isnA value of 1 indicates that the interrupt of the core has not been previously triggered (or responded to), L will benAfter the zero clearing, the subsequent program code of the interrupt service program is executed, of course, the subsequent program code of the interrupt service program can be executed first, and L is executed before the interrupt service program exitsnClearing; if L isnThe value of (1) is 0, indicating that the interrupt of the core has been triggered, and the interrupt routine is directly exited. This avoids repeated responses to the interrupt service routine being triggered by error.
In this embodiment, the interrupt tag is set, the value of the interrupt tag is checked in the nuclear interrupt service program, whether the inter-core interrupt repeated false triggering is determined according to whether the value is 0 or 1, and if the inter-core interrupt repeated false triggering is determined, the interrupt service program is immediately exited (not executed), so that the core program and other core programs can stably run, the high running reliability of the multi-core DSP embedded software system is ensured, and the problem of inter-core interrupt repeated false triggering of the multi-core DSP embedded software is effectively solved.
As an alternative embodiment, the core 0 interrupt is triggered by a timer interrupt.
This embodiment provides a technical solution for triggering core 0 interrupt. As described above, the core 0 interrupt is not triggered by other core interrupts, and the core 0 interrupt is triggered by a timer interrupt in this embodiment. The interruption means that when some unexpected situations occur in the running process of the computer and the host needs to intervene, the machine can automatically stop the running program and transfer to the program for processing the new situation, and after the processing is finished, the original suspended program is returned to continue running. The interrupts include external interrupts and internal interrupts, to which the timer interrupt belongs. A timer interrupt is an interrupt that is applied for by a timer overflow. Many processors or singlechips are internally provided with timers, for example, a 51-chip singlechip has two timers T0 and T1, and has the functions of timer 0 interrupt and timer 1 interrupt. The timer generally adopts a periodic interrupt mode, namely, an interrupt is triggered every other period. The core 0 interrupt of this embodiment is triggered by a timer every 1 millisecond.
As an alternative embodiment, the core N interrupt is triggered before core (N-1) exits its interrupt service routine, N-1, …, N-1.
The embodiment provides a triggering method of an inter-core interrupt. In this embodiment, except for core 0, interrupts for other cores are triggered before the interrupt service routine for the previous core adjacent to it exits. For example, a core 1 interrupt is triggered by core 0 exiting the interrupt service routine; the core 3 interrupt is triggered before the core 2 exits the interrupt service routine. The specific implementation method is that at the end of the interrupt service program of each core, a statement triggering the next core interrupt is added. Of course, the last core, i.e., core (N-1), is excluded.
As an alternative embodiment, the interruption tag LnThe setting method comprises the following steps: adding an array Label [ N-1 ] after the original data and command parameter areas of the shared memory area of the multi-core DSP]，Ln＝Label[n-1]，n＝1,…,N-1。
The embodiment gives the setting of the interrupt label LnA specific technical scheme of the method. In the embodiment, an array is added behind the original data and command parameter area of the shared memory area to serve as an interrupt tag. As previously mentioned, when the number of cores is N, (N-1) interrupt tags need to be set (core 0 does not need), so the length of the array, i.e., the number of elements in the array, should be (N-1), denoted as Label [ N-1 ]]。Label[0]Is the first interrupt tag L1，Label[1]Is the second interrupt tag L2Analogize in turn, Label [ N-2 ]]Is the (N-1) th interrupt tag LN-1。
As an alternative embodiment, the method further comprises: if L isnAnd (4) sending prompt information about repeated false triggering of the core N when the core N is equal to 0, and then exiting the interrupt program, wherein N is equal to 1,2, … and N-1.
The embodiment provides a technical scheme for performing the alarm of the repeated false triggering of the core. In this embodiment, if the value of the interrupt tag is found to be 0, it indicates that a core repetitive false trigger occurs, and first sends an alarm message to prompt, and then exits the interrupt service routine. This, of course, requires the addition of a statement regarding the sending of alarm information at the beginning of the corresponding interrupt service routine. Similarly, the core according to the present embodiment is all the cores other than core 0, i.e., core 1 to core (N-1).
As an alternative embodiment, N ═ 4.
This embodiment defines the total number of cores N. In this example, N is 4, that is, 4 cores, which are core 0, core 1, core 2, and core 3, respectively. FIG. 2 is a diagram illustrating the interrupt execution relationship between 4-core DSP cores; FIG. 3 is a schematic diagram of the interrupt response flow between 4-core DSP cores, and the 3 interrupt tags in FIG. 3 are the array Label [3 ].
Fig. 4 is a schematic composition diagram of a device for eliminating interruption false triggering of a multi-core DSP according to an embodiment of the present invention, where the device includes:
a tag setting module 11 for setting an interrupt tag L corresponding to the core nnN is 1, …, N-1, N is the number of cores in the multi-core DSP;
a tag assignment module 12 for setting L in the interrupt service routine of core 0n＝1，n＝1,…,N-1；
A false trigger judgment module 13 for reading L at the start of the interrupt service routine of the core nnA value of (A) if LnWhen the value is 1, then L is addednClearing and executing subsequent program codes; if L isnWhen the value is equal to 0, directly quitting the interrupt program; n-1, 2, …, N-1.
The apparatus of this embodiment may be used to implement the technical solution of the method embodiment shown in fig. 1, and the implementation principle and the technical effect are similar, which are not described herein again. The same applies to the following embodiments, which are not further described.
As an alternative embodiment, the core 0 interrupt is triggered by a timer interrupt.
As an alternative embodiment, the core N interrupt is triggered before core (N-1) exits its interrupt service routine, N-1, …, N-1.
As an alternative embodiment, the interruption tag LnThe setting method comprises the following steps: adding an array Label [ N-1 ] after the original data and command parameter area of the shared memory area of the multi-core DSP]，Ln＝Label[n-1]，n＝1,…,N-1。
As an optional embodiment, the method further comprises: if L isnAnd sending prompt information about repeated false triggering of the core N, wherein N is 1,2, … and N-1, and exiting the interrupt program.
As an alternative embodiment, N ═ 4.
The above description is only for the specific embodiment of the present invention, but the scope of the present invention is not limited thereto, and any changes or substitutions that can be easily conceived by those skilled in the art within the technical scope of the present invention are included in the scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the protection scope of the claims.

Claims (10)

1. A method for eliminating interrupt false triggering of a multi-core DSP is characterized by comprising the following steps:
setting an interrupt tag L corresponding to a core nnN is 1, …, N-1, N is the number of cores in the multi-core DSP;
setting L in interrupt service routine for core 0n＝1，n＝1,…,N-1；
At the start of the interrupt service routine for core n, read LnA value of (A) if LnWhen the value is 1, then L is addednClearing and executing subsequent program codes; if L isnWhen the value is equal to 0, directly quitting the interrupt program; n-1, 2, …, N-1.
2. The method according to claim 1, wherein the interrupt of core 0 is triggered by a timer interrupt.
3. The method of claim 2, wherein the core N interrupt is triggered before the core (N-1) exits its interrupt service routine, where N is 1, …, N-1.
4. The method according to claim 3, wherein the interrupt tag L is a label L for eliminating interrupt false triggering of the multi-core DSPnThe setting method comprises the following steps: adding an array Label [ N-1 ] after the original data and command parameter areas of the shared memory area of the multi-core DSP]，Ln＝Label[n-1]，n＝1,…,N-1。
5. The method according to claim 4, wherein the method further comprises: if L isnAnd sending prompt information about repeated false triggering of the core N, wherein N is 1,2, … and N-1, and exiting the interrupt program.
6. The method according to any one of claims 1 to 5, wherein N is 4.
7. An apparatus for eliminating interrupt false triggering of a multi-core DSP, comprising:
a tag setting module for setting an interrupt tag L corresponding to the core nnN is 1, …, N-1, N is the number of cores in the multi-core DSP;
a tag assignment module for setting L in interrupt service routine of core 0n＝1，n＝1,…,N-1；
A false trigger judgment module for reading L at the start of interrupt service program of core nnIf L is a value ofnWhen the value is 1, then L is addednClearing and executing subsequent program codes; if L isnWhen the value is equal to 0, directly quitting the interrupt program; n-1, 2, …, N-1.
8. The apparatus according to claim 7, wherein the core 0 interrupt is triggered by a timer interrupt.
9. The apparatus of claim 8, wherein the core N interrupt is triggered before the core (N-1) exits its interrupt service routine, where N is 1, …, N-1.
10. The apparatus according to claim 9, wherein the interrupt tag L is configured to eliminate interrupt false triggering of a multi-core DSPnThe setting method comprises the following steps: adding an array Label [ N-1 ] after the original data and command parameter areas of the shared memory area of the multi-core DSP]，Ln＝Label[n-1]，n＝1,…,N-1。
CN202210175352.5A 2022-02-24 2022-02-24 Method and device for eliminating interrupt false triggering of multi-core DSP Pending CN114661543A (en)

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