CN113360294B - Method, system, terminal and storage medium for establishing multi-process inter-core communication - Google Patents
Method, system, terminal and storage medium for establishing multi-process inter-core communication Download PDFInfo
- Publication number
- CN113360294B CN113360294B CN202110656166.9A CN202110656166A CN113360294B CN 113360294 B CN113360294 B CN 113360294B CN 202110656166 A CN202110656166 A CN 202110656166A CN 113360294 B CN113360294 B CN 113360294B
- Authority
- CN
- China
- Prior art keywords
- address
- data
- identification
- core
- storage address
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
- 230000006854 communication Effects 0.000 title claims abstract description 136
- 238000004891 communication Methods 0.000 title claims abstract description 135
- 238000000034 method Methods 0.000 title claims abstract description 116
- 230000008569 process Effects 0.000 claims abstract description 57
- 238000012545 processing Methods 0.000 claims abstract description 26
- 238000012544 monitoring process Methods 0.000 claims abstract description 23
- 230000006870 function Effects 0.000 claims description 29
- 238000004806 packaging method and process Methods 0.000 claims description 9
- 238000004590 computer program Methods 0.000 claims description 3
- 230000003993 interaction Effects 0.000 abstract description 10
- 230000005856 abnormality Effects 0.000 abstract description 7
- FFBHFFJDDLITSX-UHFFFAOYSA-N benzyl N-[2-hydroxy-4-(3-oxomorpholin-4-yl)phenyl]carbamate Chemical compound OC1=C(NC(=O)OCC2=CC=CC=C2)C=CC(=C1)N1CCOCC1=O FFBHFFJDDLITSX-UHFFFAOYSA-N 0.000 description 10
- 238000010586 diagram Methods 0.000 description 5
- 230000003068 static effect Effects 0.000 description 5
- 230000008878 coupling Effects 0.000 description 3
- 238000010168 coupling process Methods 0.000 description 3
- 238000005859 coupling reaction Methods 0.000 description 3
- 230000003287 optical effect Effects 0.000 description 3
- 238000006467 substitution reaction Methods 0.000 description 3
- 239000005441 aurora Substances 0.000 description 2
- 238000013461 design Methods 0.000 description 2
- 238000007726 management method Methods 0.000 description 2
- 230000007246 mechanism Effects 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 230000009471 action Effects 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 230000005540 biological transmission Effects 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 230000006386 memory function Effects 0.000 description 1
- 230000008520 organization Effects 0.000 description 1
- 238000013468 resource allocation Methods 0.000 description 1
Images
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/46—Multiprogramming arrangements
- G06F9/54—Interprogram communication
- G06F9/545—Interprogram communication where tasks reside in different layers, e.g. user- and kernel-space
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/30—Monitoring
- G06F11/3003—Monitoring arrangements specially adapted to the computing system or computing system component being monitored
- G06F11/3006—Monitoring arrangements specially adapted to the computing system or computing system component being monitored where the computing system is distributed, e.g. networked systems, clusters, multiprocessor systems
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/30—Monitoring
- G06F11/3051—Monitoring arrangements for monitoring the configuration of the computing system or of the computing system component, e.g. monitoring the presence of processing resources, peripherals, I/O links, software programs
Abstract
The invention provides a method, a system, a terminal and a storage medium for establishing multi-process inter-core communication, wherein the method comprises the following steps: the communication request core selects an identification storage address and sends the identification storage address to a target core, and the target core processes an interrupt processing function and then performs data updating on the identification storage address; and monitoring the data updating state of the identification storage address, judging that the communication connection is successful if the monitored data of the identification storage address is updated by the target core, and resetting the data of the identification storage address. The invention realizes the information interaction of communication establishment, avoids communication failure establishment caused by the loss of a feedback signal ACK, and avoids various system abnormalities caused by multi-process simultaneous communication by appointing an identification storage address, informing the address to a target core, interrupting a processing function after the target core receives a communication request, updating data of the identification storage address after an interrupt program is completed, and monitoring that the core requesting communication establishment judges that the communication establishment is successful after the data is updated.
Description
Technical Field
The invention belongs to the technical field of servers, and particularly relates to a method, a system, a terminal and a storage medium for establishing multi-process inter-core communication.
Background
A multi-core processor refers to a processor that integrates two or more complete computing engines (cores) into one processor, and the processor can support multiple processors on a system bus, and a bus controller provides all bus control signals and command signals.
The inter-core communication is the communication between two processes on two service modules, and this requires the support of communication channels on hardware for data transmission and handshaking in the communication process. What is described herein is a synchronization method in the handshake process.
The handshake process is typically implemented by means of an interrupt, which is sent when one core a wants to communicate with another core B, and then enters a polling state to wait for the feedback signal ACK from B. After receiving the interrupt signal, the core B enters an interrupt processing function, and an ACK signal is set at the end of the interrupt processing function. After core a has queried the ACK signal, the following process continues.
The first thing core B enters the interrupt handling function is to clear the interrupt to ensure that the subsequent interrupt signal can enter normally, which also includes clear ACK signal. This handshake works stably when core a has only one process communicating with core B. When a plurality of processes in core a need to communicate with core B, one or more processes in core a may lose the ACK signal and subsequent processes may not be performed.
Disclosure of Invention
In view of the foregoing defects in the prior art, the present invention provides a method, a system, a terminal, and a storage medium for establishing multi-process inter-core communication, so as to solve the foregoing technical problems.
In a first aspect, the present invention provides a method for establishing multi-process inter-core communication, including:
the communication request core selects an identification memory address and sends the identification memory address to a target core, and the target core processes an interrupt processing function and then performs data updating on the identification memory address;
and monitoring the data updating state of the identification storage address, judging that the communication connection is successful if the monitored data of the identification storage address is updated by the target core, and resetting the data of the identification storage address.
When a communication request core needs to communicate with other cores in a certain process, an identification storage address is selected, the address is notified to a target core, the target core interrupts a processing function after receiving a communication request, and data of the identification storage address is updated after an interrupt program is completed, so that information interaction of communication establishment is realized, and communication failure caused by feedback signal ACK loss is avoided.
Further, the communication request core selects an identifier storage address and sends the identifier storage address to a target core, including:
and randomly selecting one storage bit from the register as an identification storage address, packaging the identification storage address into a data packet, and sending the data packet to a target core.
Further, randomly selecting a storage bit from the register as the identification storage address includes:
traversing all storage bits of the register, and taking the storage bit with empty storage data as a storage bit to be selected;
randomly selecting an identification storage address from storage bits to be selected;
and binding the process number requesting communication with the identification storage address, and storing the process number and the identification storage address in a pair in an address list.
Further, monitoring a data update state of the tag memory address, and if it is monitored that the data of the tag memory address is updated by the target core, determining that the communication connection is successful, and resetting the data of the tag memory address, including:
polling the identification storage address in the address list;
if the data of the identification memory address is monitored to be updated to 1, judging that the data of the identification memory address is updated by a target core;
and after the successful communication connection is confirmed, clearing the data of the identification storage address.
In a second aspect, the present invention provides a system for establishing multi-process inter-core communication, including:
the address determination unit is used for the communication request core to select an identification storage address and send the identification storage address to a target core, and the target core processes an interrupt processing function and then performs data updating on the identification storage address;
and the updating monitoring unit is used for monitoring the data updating state of the identification storage address, judging that the communication connection is successful if the monitored data of the identification storage address is updated by the target core, and resetting the data of the identification storage address.
When a communication request core needs to communicate with other cores in a certain process, an identification storage address is selected, the address is notified to a target core, the target core interrupts a processing function after receiving a communication request, and data of the identification storage address is updated after an interrupt program is completed, so that information interaction of communication establishment is realized, and communication failure caused by feedback signal ACK loss is avoided.
Further, the address determination unit includes:
and the address selection module is used for randomly selecting a storage bit from the register as an identification storage address, packaging the identification storage address into a data packet, and sending the data packet to a target core.
Further, the address option module includes:
the traversal submodule is used for traversing all storage bits of the register and taking the storage bit with empty storage data as a storage bit to be selected;
the selection submodule is used for randomly selecting the identification storage address from the storage bits to be selected;
and the binding submodule is used for binding the process number of the request communication with the identification storage address and storing the process number and the identification storage address in a pair into an address list.
Further, the update monitoring unit includes:
the polling module is used for polling the identification storage address in the address list;
the judging module is used for judging that the data of the identification memory address is updated by a target core if the data of the identification memory address is monitored to be updated to 1;
and the clearing module is used for clearing the data of the identification storage address after the successful communication connection is confirmed.
In a third aspect, a terminal is provided, including:
a processor, a memory, wherein,
the memory is used for storing a computer program which,
the processor is used for calling and running the computer program from the memory so as to make the terminal execute the method of the terminal.
In a fourth aspect, a computer storage medium is provided, having stored therein instructions that, when executed on a computer, cause the computer to perform the method of the above aspects.
The beneficial effect of the invention is that,
the method for establishing the communication among the multiprocess cores comprises the steps of appointing the identification storage address, informing the target core of the address, interrupting the processing function after the target core receives the communication request, updating the data of the identification storage address after the interruption program is completed, monitoring the data updating, and judging that the communication establishment is successful by the core requesting to establish the communication, thereby realizing the information interaction of the communication establishment, avoiding the communication failure establishment caused by the loss of a feedback signal ACK, and avoiding various system abnormalities caused by the simultaneous communication of the multiprocess.
The multi-process inter-core communication establishment system provided by the invention has the advantages that the identification storage address is appointed by the address determining unit and is informed to the target core, the target core interrupts a function after receiving a communication request and updates the data of the identification storage address after finishing an interrupt program, and the core requesting to establish communication judges that the communication establishment is successful after the update monitoring unit monitors that the data is updated, so that the information interaction of the communication establishment is realized, the communication failure establishment caused by the loss of a feedback signal ACK is avoided, and various system abnormalities caused by the simultaneous communication of multiple processes are avoided.
The multi-process inter-core communication establishment terminal provided by the invention can execute a multi-process inter-core communication establishment method, the target core is informed of the address by designating the identification storage address, the target core interrupts the processing function after receiving the communication request, the data of the identification storage address is updated after the interrupt program is completed, and the core requesting to establish communication judges that the communication establishment is successful after monitoring that the data is updated, thereby realizing the information interaction of the communication establishment, avoiding the communication failure establishment caused by the loss of a feedback signal ACK, and avoiding various system abnormalities caused by the simultaneous communication of multiple processes.
The storage medium stores an executive program of a multi-process inter-core communication establishment method, the address is notified to a target core by designating an identification storage address, the target core interrupts a processing function after receiving a communication request, updates data of the identification storage address after finishing an interrupt program, and monitors that the core requesting for establishing communication judges that the communication establishment is successful after the data is updated, thereby realizing information interaction of the communication establishment, avoiding communication failure establishment caused by the loss of a feedback signal ACK, and avoiding various system abnormalities caused by simultaneous communication of multiple processes.
In addition, the invention has reliable design principle, simple structure and very wide application prospect.
Drawings
In order to more clearly illustrate the embodiments or technical solutions in the prior art of the present invention, the drawings used in the description of the embodiments or prior art will be briefly described below, and it is obvious for those skilled in the art that other drawings can be obtained based on these drawings without creative efforts.
FIG. 1 is a schematic flow diagram of a method of one embodiment of the invention.
FIG. 2 is a schematic block diagram of a system of one embodiment of the present invention.
Fig. 3 is a schematic structural diagram of a terminal according to an embodiment of the present invention.
Detailed Description
In order to make those skilled in the art better understand the technical solution of the present invention, the technical solution in the embodiment of the present invention will be clearly and completely described below with reference to the drawings in the embodiment of the present invention, and it is obvious that the described embodiment is only a part of the embodiment of the present invention, and not all embodiments. All other embodiments, which can be obtained by a person skilled in the art without making any creative effort based on the embodiments in the present invention, shall fall within the protection scope of the present invention.
The following explains key terms appearing in the present invention.
A Process (Process) is a running activity of a program in a computer on a data set, is a basic unit for resource allocation and scheduling of a system, and is the basis of an operating system structure. In early process-oriented design of computer architectures, processes were the basic execution entities of programs; in contemporary thread-oriented computer architectures, processes are containers for threads. A program is a description of instructions, data, and their organization, and a process is an entity of a program.
A multi-core processor is a processor that integrates two or more complete computing engines (cores) into one processor, and the processor can support multiple processors on a system bus, and a bus controller provides all bus control signals and command signals.
The register, the function of the register is to store the binary code, it is formed by flip-flop combination with memory function. One flip-flop can store 1-bit binary codes, so a register for storing n-bit binary codes needs to be formed by n flip-flops. Registers can be divided into two broad categories, basic registers and shift registers, according to their functions. The basic registers can only be fed with data in parallel and can only be output in parallel. The data in the shift register can be shifted to the right or left bit by bit in sequence under the action of shift pulses, and the data can be input in parallel and output in parallel, can be input in series and output in series, can be input in parallel and output in series, or can be input in series and output in parallel, so that the method is very flexible and has wide application.
FIG. 1 is a schematic flow diagram of a method of one embodiment of the invention. The execution subject in fig. 1 may establish a system for multi-process inter-core communication.
As shown in fig. 1, the method includes:
110, a communication request core selects an identification memory address and sends the identification memory address to a target core, and the target core processes an interrupt processing function and then performs data updating on the identification memory address;
and 120, monitoring the data updating state of the identification storage address, judging that the communication connection is successful if the monitored data of the identification storage address is updated by the target core, and resetting the data of the identification storage address.
In order to facilitate understanding of the present invention, the method for establishing multi-process inter-core communication provided by the present invention is further described below by using the principle of the method for establishing multi-process inter-core communication of the present invention and combining the process of establishing multi-process inter-core communication in the embodiments.
Example 1
The embodiment provides a method for establishing multi-process inter-core communication, taking a dual-core processor as an example, and the method comprises the following steps:
s1, a communication request core selects an identification memory address, the identification memory address is sent to a target core, and data updating is carried out on the identification memory address after the target core interrupts a processing function.
In this embodiment, two cores of the processor are core 1 and core 2, respectively, and both process 1 and process 2 of core 1 need to communicate with core 2.
The core 1 randomly selects two storage bits from the empty storage bits of the register, wherein the two storage bits are respectively an address 1 and an address 2, the address 1 is bound as an identification storage address of the process 1, and the address 2 is bound as an identification storage address of the process 2.
An address list is created, as shown in table 1:
TABLE 1 address List
| Process 1 | Address 1 |
| Process 2 | Address 2 |
The method comprises the steps of packaging an address 1 into a data packet 1, packaging an address 2 into a data packet 2, sending the data packet 1 and the data packet 2 to a core 2, and writing 1 into the address 1 after an interrupt processing function according to a communication request of a process 1 after the core 2 receives the data packet 1. Similarly, for a communication request of the process 2, 1 is written at the address 2 after the interrupt processing function.
S2, monitoring the data updating state of the identification storage address, judging that the communication connection is successful if the monitored data of the identification storage address is updated by the target core, and resetting the data of the identification storage address.
The core 1 starts a polling process, calls an address list, polls an address 1 and an address 2 in the address list, if a value 1 of the address 1 is polled, the process 1 is considered to successfully establish a communication link with the core 2, and at the moment, the value of the address 1 is cleared. Similarly, if the value 1 of the address 2 is polled, it is determined that the process 2 successfully establishes the communication link with the core 2, and at this time, the value of the address 2 is cleared.
After monitoring that the communication with the core 2 is successfully established, the core 1 communicates with the core 2 in a memory sharing mode. In Linux, there are many mechanisms for implementing process communication, such as signals, pipes, semaphores, message queues, shared memory, sockets, and the like, but the memory sharing mode has the highest efficiency.
In Aurora, shared memory is the physical basis of multi-core communication, and its implementation mainly includes 3 parts: a Shared Memory Driver (SMD), a Shared Memory State Machine (SMSM), and a Shared Memory Manager (SMEM). Wherein the SMD is used for data communication between the multiple cores; the SMSM is used for state communication among the multiple cores; SMEM is a bottom layer protocol, is a management interface of a physical RAM shared memory, and is the basis of SMD and SMSM.
SMEM has two allocation modes: the system comprises dynamic SMEM and static SMEM, wherein the dynamic SMEM is distributed in real time according to needs, and the static SMEM is distributed in advance. The main interfaces of SMEM are: smem _ alloc (), smem _ find (), smem _ init (), and the like.
Implementation of SMEM, SMD, SMSM all require support from the hardware platform vendor.
Example 2
The embodiment provides a method for establishing multi-process inter-core communication, which comprises the following steps:
a register to record the status is added to the channel. Each bit corresponds to a process on the core A, when a process on the core A needs to communicate with the core B, each bit of the register is checked, the lowest bit which is not set to be 1 is taken as the identifier of the process, and the information of the bit is packed into a data packet to be transmitted to the core B. And the core B sets the corresponding bit of the state register to be 1 according to the position information at the end of the interrupt processing function. Core a polls to the bit set to 1, first clears 0 the bit, and then proceeds with the subsequent operations.
By adopting the mode, the problem of synchronization of communication among multiple cores can be well solved.
Example 3
The embodiment provides a multi-process inter-core communication establishment method, which includes the following steps:
s1, a communication request core selects an identification storage address and sends the identification storage address to a target core, and the target core processes an interrupt processing function and then performs data updating on the identification storage address.
In this embodiment, two cores of the processor are core 1 and core 2, respectively, and both process 1 and process 2 of core 1 need to communicate with core 2.
The core 1 randomly selects two storage bits from the empty storage bits of the register, wherein the two storage bits are respectively an address 1 and an address 2, the address 1 is bound as an identification storage address of the process 1, and the address 2 is bound as an identification storage address of the process 2. Initial data a1 at address 1 is recorded, and initial data b1 at address 2 is recorded. Address 1 and address 2 are set to the occupied state.
An address list is created, as shown in table 1:
TABLE 1 address List
| Process 1 | Address 1 |
| Process 2 | Address 2 |
The method comprises the steps of packaging an address 1 into a data packet 1, packaging an address 2 into a data packet 2, sending the data packet 1 and the data packet 2 to a core 2, and writing an acknowledgement indication a2 into the address 1 after an interrupt processing function according to a communication request of a process 1 after the core 2 receives the data packet 1. Similarly, for a communication request of the process 2, b2 is written at the address 2 after the interrupt processing function.
S2, monitoring the data updating state of the identification storage address, judging that the communication connection is successful if the monitored data of the identification storage address is updated by the target core, and resetting the data of the identification storage address.
The core 1 starts a polling process, calls an address list, polls an address 1 and an address 2 in the address list, if the numerical value polled to the address 1 is updated to a2, the process 1 is considered to successfully establish a communication link with the core 2, at the moment, the numerical value of the address 1 is reset to a1, and the occupied state of the address 1 is released. Similarly, if the value polled to address 2 is updated to b2, it is assumed that process 2 successfully establishes a communication link with core 2, at this time, the value of address 2 is reset to b1, and the occupied state of address 2 is released.
After monitoring that the communication with the core 2 is successfully established, the core 1 communicates with the core 2 in a memory sharing mode. In Linux, there are many mechanisms for implementing process communication, such as signals, pipelines, semaphores, message queues, shared memory, sockets, and the like, but the memory sharing mode has the highest efficiency.
In Aurora, shared memory is the physical basis of multi-core communication, and its implementation mainly includes 3 parts: a Shared Memory Driver (SMD), a Shared Memory State Machine (SMSM), and a Shared Memory Manager (SMEM). Wherein the SMD is used for data communication between the multiple cores; the SMSM is used for state communication among the multiple cores; SMEM is a bottom layer protocol, is a management interface of a physical RAM shared memory, and is the basis of SMD and SMSM.
SMEM has two allocation modes: the system comprises dynamic SMEM and static SMEM, wherein the dynamic SMEM is distributed in real time according to needs, and the static SMEM is distributed in advance. The main interfaces of SMEM are: small _ alloc (), small _ find (), small _ init (), etc.
Implementation of SMEM, SMD, SMSM all require support from the hardware platform vendor.
In the embodiment, the identification storage address is designated, the address is notified to the target core, the target core interrupts the processing function after receiving the communication request, the data of the identification storage address is updated after the interrupt program is completed, and the core requesting to establish communication judges that the communication is established successfully after monitoring that the data is updated, so that information interaction of communication establishment is realized, communication failure caused by the loss of a feedback signal ACK is avoided, and various system abnormalities caused by simultaneous communication of multiple processes are avoided.
As shown in fig. 2, the system 200 includes:
the address determination unit 210 is configured to select an identifier storage address by a communication request core, send the identifier storage address to a target core, and perform data update on the identifier storage address after the target core interrupts a processing function;
and an update monitoring unit 220, configured to monitor a data update state of the identified memory address, determine that the communication connection is successful if it is monitored that the data of the identified memory address is updated by the target core, and reset the data of the identified memory address.
When a communication request core needs to communicate with other cores in a certain process, an identification storage address is selected, the address is notified to a target core, the target core interrupts a processing function after receiving a communication request, and data of the identification storage address is updated after an interrupt program is completed, so that information interaction of communication establishment is realized, and communication failure caused by feedback signal ACK loss is avoided.
Optionally, as an embodiment of the present invention, the address determining unit includes:
and the address selection module is used for randomly selecting one storage bit from the register as an identification storage address, packaging the identification storage address into a data packet, and sending the data packet to a target core.
Optionally, as an embodiment of the present invention, the address option module includes:
the traversal submodule is used for traversing all storage bits of the register and taking the storage bit with empty storage data as a storage bit to be selected;
the selection submodule is used for randomly selecting an identification storage address from storage bits to be selected;
and the binding submodule is used for binding the process number requesting communication with the identification storage address and storing the process number and the identification storage address in a pair in an address list.
Optionally, as an embodiment of the present invention, the update monitoring unit includes:
the polling module is used for polling the identification storage address in the address list;
the judging module is used for judging that the data of the identification storage address is updated by a target core if the monitored data of the identification storage address is updated to 1;
and the clearing module is used for clearing the data of the identification storage address after the successful communication connection is confirmed.
Fig. 3 is a schematic structural diagram of a terminal 300 according to an embodiment of the present invention, where the terminal 300 may be used to execute the method for establishing multi-process inter-core communication according to the embodiment of the present invention.
Among them, the terminal 300 may include: a processor 310, a memory 320, and a communication unit 330. The components communicate via one or more buses, and those skilled in the art will appreciate that the architecture of the server shown in the figures is not intended to be limiting, and that it may be a bus architecture, a star architecture, a combination of more or fewer components than shown, or a different arrangement of components.
The memory 320 may be used for storing instructions executed by the processor 310, and the memory 320 may be implemented by any type of volatile or non-volatile storage terminal or combination thereof, such as Static Random Access Memory (SRAM), electrically erasable programmable read-only memory (EEPROM), erasable programmable read-only memory (EPROM), programmable read-only memory (PROM), read-only memory (ROM), magnetic memory, flash memory, magnetic disk or optical disk. The executable instructions in memory 320, when executed by processor 310, enable terminal 300 to perform some or all of the steps in the method embodiments described below.
The processor 310 is a control center of the storage terminal, connects various parts of the entire electronic terminal using various interfaces and lines, and performs various functions of the electronic terminal and/or processes data by operating or executing software programs and/or modules stored in the memory 320 and calling data stored in the memory. The processor may be formed by an Integrated Circuit (IC), for example, a single packaged IC, or a plurality of packaged ICs with the same or different functions. For example, the processor 310 may include only a Central Processing Unit (CPU). In the embodiment of the present invention, the CPU may be a single operation core, or may include multiple operation cores.
A communication unit 330, configured to establish a communication channel so that the storage terminal can communicate with other terminals. And receiving user data sent by other terminals or sending the user data to other terminals.
The present invention also provides a computer storage medium, wherein the computer storage medium may store a program, and the program may include some or all of the steps in the embodiments provided by the present invention when executed. The storage medium may be a magnetic disk, an optical disk, a read-only memory (ROM) or a Random Access Memory (RAM).
Therefore, the invention, by designating the identification storage address and notifying the address to the target core, the target core interrupts the function after receiving the communication request, updates the data of the identification storage address after completing the interrupt program, and monitors that the core requesting to establish communication judges that the communication establishment is successful after the data is updated, thereby realizing the information interaction of the communication establishment, avoiding the communication failure caused by the loss of the feedback signal ACK, and avoiding various system abnormalities caused by the simultaneous communication of multiple processes.
Those skilled in the art will readily appreciate that the techniques of the embodiments of the present invention may be implemented using software plus any required general purpose hardware platform. Based on such understanding, the technical solutions in the embodiments of the present invention may be embodied in the form of a software product, where the computer software product is stored in a storage medium, such as a usb disk, a removable hard disk, a Read-Only Memory (ROM), a Random Access Memory (RAM), a magnetic disk or an optical disk, and the like, and the storage medium can store program codes, and includes instructions for enabling a computer terminal (which may be a personal computer, a server, or a second terminal, a network terminal, and the like) to perform all or part of the steps of the method in the embodiments of the present invention.
The same and similar parts in the various embodiments in this specification may be referred to each other. Especially, for the terminal embodiment, since it is basically similar to the method embodiment, the description is relatively simple, and for relevant points, reference may be made to the description in the method embodiment.
In the embodiments provided in the present invention, it should be understood that the disclosed system and method can be implemented in other ways. For example, the above-described system embodiments are merely illustrative, and for example, the division of the units is only one logical functional division, and other divisions may be realized in practice, for example, a plurality of units or components may be combined or integrated into another system, or some features may be omitted, or not executed. In addition, the shown or discussed mutual coupling or direct coupling or communication connection may be an indirect coupling or communication connection through some interfaces, systems or units, and may be in an electrical, mechanical or other form.
The units described as separate parts may or may not be physically separate, and parts displayed as units may or may not be physical units, may be located in one place, or may be distributed on a plurality of network units. Some or all of the units can be selected according to actual needs to achieve the purpose of the solution of the embodiment.
In addition, functional units in the embodiments of the present invention may be integrated into one processing unit, or each unit may exist alone physically, or two or more units are integrated into one unit.
Although the present invention has been described in detail by referring to the drawings in connection with the preferred embodiments, the present invention is not limited thereto. Various equivalent modifications or substitutions can be made on the embodiments of the present invention by those skilled in the art without departing from the spirit and scope of the present invention, and these modifications or substitutions should be within the scope of the present invention/any person skilled in the art can easily conceive of the changes or substitutions within the technical scope of the present disclosure and the scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the protection scope of the claims.
Claims (6)
1. A method for establishing multi-process inter-core communication is characterized by comprising the following steps:
the communication request core selects an identification storage address and sends the identification storage address to a target core, and the target core processes an interrupt processing function and then performs data updating on the identification storage address;
monitoring the data updating state of the identification memory address, judging that the communication connection is successful if the monitored data of the identification memory address is updated by the target core, and resetting the data of the identification memory address;
the communication request core selects an identification storage address and sends the identification storage address to a target core, and the method comprises the following steps:
randomly selecting a storage bit from a register as an identification storage address, packaging the identification storage address into a data packet, and sending the data packet to a target core;
randomly selecting a storage bit from a register as an identification storage address, comprising:
traversing all storage bits of the register, and taking the storage bit with empty storage data as a storage bit to be selected;
randomly selecting an identification storage address from storage bits to be selected;
and binding the process number requesting communication with the identification storage address, and storing the process number and the identification storage address in a pair in an address list.
2. The method of claim 1, wherein monitoring the update status of the data of the identified memory address, determining that the communication connection is successful if the monitored data of the identified memory address is updated by the target core, and resetting the data of the identified memory address comprises:
polling the identification storage address in the address list;
if the data of the identification memory address is monitored to be updated to 1, judging that the data of the identification memory address is updated by a target core;
and after the successful communication connection is confirmed, clearing the data of the identification storage address.
3. A multi-process inter-core communication establishment system, comprising:
the address determination unit is used for the communication request core to select an identification storage address and send the identification storage address to a target core, and the target core processes an interrupt processing function and then performs data updating on the identification storage address;
the updating monitoring unit is used for monitoring the data updating state of the identification storage address, judging that the communication connection is successful if the monitored data of the identification storage address is updated by the target core, and resetting the data of the identification storage address; the address determination unit includes:
the address selection module is used for randomly selecting a storage bit from the register as an identification storage address, packaging the identification storage address into a data packet, and sending the data packet to a target core;
the address selection module comprises:
the traversal submodule is used for traversing all storage bits of the register and taking the storage bit with empty storage data as a storage bit to be selected;
the selection submodule is used for randomly selecting the identification storage address from the storage bits to be selected;
and the binding submodule is used for binding the process number of the request communication with the identification storage address and storing the process number and the identification storage address in a pair into an address list.
4. The system of claim 3, wherein the update monitoring unit comprises:
the polling module is used for polling the identification storage addresses in the address list;
the judging module is used for judging that the data of the identification memory address is updated by a target core if the data of the identification memory address is monitored to be updated to 1;
and the clearing module is used for clearing the data of the identification storage address after the successful communication connection is confirmed.
5. A terminal, comprising:
a processor;
a memory for storing instructions for execution by the processor;
wherein the processor is configured to perform the method of any of claims 1-2.
6. A computer-readable storage medium, in which a computer program is stored which, when being executed by a processor, carries out the method according to any one of claims 1-2.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202110656166.9A CN113360294B (en) | 2021-06-11 | 2021-06-11 | Method, system, terminal and storage medium for establishing multi-process inter-core communication |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202110656166.9A CN113360294B (en) | 2021-06-11 | 2021-06-11 | Method, system, terminal and storage medium for establishing multi-process inter-core communication |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN113360294A CN113360294A (en) | 2021-09-07 |
| CN113360294B true CN113360294B (en) | 2023-01-10 |
Family
ID=77534063
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202110656166.9A Active CN113360294B (en) | 2021-06-11 | 2021-06-11 | Method, system, terminal and storage medium for establishing multi-process inter-core communication |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN113360294B (en) |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN112328533A (en) * | 2020-11-09 | 2021-02-05 | 哲库科技(上海)有限公司 | Multi-core processing system, inter-core communication method thereof, and storage medium |
-
2021
- 2021-06-11 CN CN202110656166.9A patent/CN113360294B/en active Active
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN112328533A (en) * | 2020-11-09 | 2021-02-05 | 哲库科技(上海)有限公司 | Multi-core processing system, inter-core communication method thereof, and storage medium |
Also Published As
| Publication number | Publication date |
|---|---|
| CN113360294A (en) | 2021-09-07 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN108055343B (en) | Data synchronization method and device for computer room | |
| CN108647104B (en) | Request processing method, server and computer readable storage medium | |
| EP0361176B1 (en) | Method and apparatus for communicating data between multiple tasks in data processing systems | |
| EP3410288B1 (en) | Online upgrade method, device and system | |
| US8112559B2 (en) | Increasing available FIFO space to prevent messaging queue deadlocks in a DMA environment | |
| US20090292810A1 (en) | Message binding processing technique | |
| CN108064377B (en) | Management method and device for multi-system shared memory | |
| CN110389843B (en) | Service scheduling method, device, equipment and readable storage medium | |
| CN111176801B (en) | Multi-process management method, device, equipment and storage medium | |
| US8631086B2 (en) | Preventing messaging queue deadlocks in a DMA environment | |
| CN115525417A (en) | Data communication method, communication system, and computer-readable storage medium | |
| CN114625533A (en) | Distributed task scheduling method and device, electronic equipment and storage medium | |
| CN105373563B (en) | Database switching method and device | |
| CN113849238B (en) | Data communication method, device, electronic equipment and readable storage medium | |
| US9507637B1 (en) | Computer platform where tasks can optionally share per task resources | |
| CN113360294B (en) | Method, system, terminal and storage medium for establishing multi-process inter-core communication | |
| CN111831408A (en) | Asynchronous task processing method and device, electronic equipment and medium | |
| US10678744B2 (en) | Method and system for lockless interprocessor communication | |
| CN112099728A (en) | Method and device for executing write operation and read operation | |
| CN115658295A (en) | Resource scheduling method and device, electronic equipment and storage medium | |
| CN113220368B (en) | Storage client resource isolation method, system, terminal and storage medium | |
| CN111708631B (en) | Data processing method based on multipath server, intelligent terminal and storage medium | |
| CN115543343B (en) | Variable cross-thread operation method and device | |
| CN111930475B (en) | Method and device for starting ETT operation | |
| CN117149471B (en) | Communication method, device, embedded system, storage medium and electronic equipment |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |