JPH06101230B2 - Semiconductor memory - Google Patents

Description

TECHNICAL FIELD The present invention relates to a semiconductor memory, and more particularly to a dynamic memory for reading out charges accumulated in a capacitor by a sense amplifier.

(B) Conventional Technology A conventional dynamic memory (D-RAM) is constructed as shown in FIG. In FIG. 5, each of the plurality of sense amplifiers (1) is provided with a bit line BL and ▲ ▼ connected to a pair of sense nodes, and each bit line BL and ▲ ▼ has a row address. A plurality of memory cells (3) selected by the plurality of word lines W output from the decoder (2) are connected and a dummy cell selected by the dummy word lines DW and DW ′ output from the row address decoder (2). (4) is connected. Further, an active restore circuit (5) for raising the bit line BL or ▲ ▼ to a predetermined potential after the sense operation of the sense amplifier (1) is connected to the bit line BL and ▲ ▼, and
The MOSFET (7) controlled by the column line CL of the column address decoder (6) has output lines D ₀ and ▲ ₀ ▼ and bit lines BL and ▲ ▼ connected to the input of the output circuit (8).
It is provided between. On the other hand, the row address control signal ▲ ▼ for controlling the application of the row address data A _{0 to} A ₇ and the chip select signal ▲ ▼ for selecting the memory chip are applied to the refresh mode detection circuit (9), The detection output is applied to the refresh control circuit (10). The refresh mode detection circuit (9) detects that the row address control signal ▲ ▼ becomes "0" after the chip select signal ▲ ▼ becomes "0". The refresh control circuit (10) A refresh address counter for sequentially designating the word lines W and a timer are built in, the refresh address counter is automatically incremented according to the period of the timer, and the value is applied to the row address decoder (2) to perform refresh. Is.

In the circuit shown in FIG. 5, the bit lines BL and ▲
After the precharge of ▼, one of the word lines W and the dummy word line DW or DW 'are output, so that the bit line BL and the memory cell (3) and the dummy cell (4) designated by ▲ ▼ are output. Connected. Therefore, when the timing signal φ _S1 becomes “1”, the sense operation of the sense amplifier (1) is started, and further, when the timing signal φ _S2 becomes “1”, the sensing operation rapidly progresses, and the bit line BL and ▲
The weak potential difference generated by the difference between the charges accumulated in the memory cell (3) connected to ▼ and the dummy cell (4) is amplified by the sense amplifier (1), and the bit line BL and ▲
The potential difference of ▼ expands. Also, a sense amplifier (1)
When the timing signal φ _AR output at the timing when the sensing operation of is finished becomes “1”, the active restore circuit (5) operates and the potential of the bit line BL or ▲ ▼ at the “1” level is raised to a predetermined potential. To be In this way, the data of the memory cell (3) designated by the word line W is read to the bit lines BL and ▲ ▼ connected to all the sense amplifiers (1). Column address decoder (6) to column line CL
When one of the MOSFETs is "1", the pair of MOSFETs (7) is selected and turned on, and the data of the bit lines BL and ▲ ▼ is output through the MOSFETs (7) to the output lines D ₀ and ▲ ₀ ▼. And is output from the output circuit (8). When refreshing the memory cell (3), set the chip select signal CS to "0" and then the row address control signal ▲
By setting ▼ to "0", the refresh mode detection circuit (9) outputs a detection output, and the refresh control circuit (10) operates. As a result, the word lines W are sequentially selected at the timer cycle regardless of the row address data A _{0 to} A ₇ , and the refresh is executed.

Such a D-RAM is described on pages 169 to 192 of Nikkei Electronics, published on July 18, 1983.

(C) Problems to be Solved by the Invention By the way, in the conventional D-RAM shown in FIG.
The read method of applying the column address data after applying the row address data is a normal method, but in order to increase the read speed, by applying the row address data and then sequentially applying the column address data, By selecting the bit line BL and ▲ ▼ to read the data, or by applying the row address data and then the column address data and then setting the column address control signal ▲ ▼ alternately to “0” and “1”. A nibble mode for reading data is realized. Furthermore, after applying row address data, a static column method is realized in which data can be read by simply applying a column address within the same row address.

However, in either method, since the data generated in each bit line BL and ▲ ▼ changes during the refresh of the memory cell, the data stored in the column address in the row address specified before the refresh is read. It is not possible. Therefore, there is a drawback that it is necessary to wait for the memory access until the refresh is completed.

(D) Means for Solving the Problems The present invention has been made in view of the above-mentioned points, and the row address is sequentially selected by the refresh request signal periodically output from the refresh timer, and the sense amplifier of the sense amplifier is selected. In a semiconductor memory with a self-refresh function that includes a refresh control circuit that refreshes memory cells connected to the bit lines BL and ▲ ▼, holds the data read to the bit lines BL and ▲ ▼,
After holding the data, a holding circuit is provided which is separated from the bit line BL and ▲ ▼, the row address change detection circuit for detecting the change of the row address data while selecting the data of the holding circuit by the column address selection means, A logical product circuit (AND gate) for inputting the detection output of the row address change detection circuit and the control signal of the refresh control circuit is provided, and the output of the logical product circuit is output to the outside as a wait signal.

(E) Operation According to the above-mentioned means, in the normal read state, when the row address data is applied, the word line W designated by the row address data is selected, and the data of the memory cell connected to this word line W is selected. Is read to the bit lines BL and ▲ ▼ by the sense amplifier, and further, the read data is stored in the holding circuit after the sense operation of the sense amplifier is completed. The holding circuit that stores data is a bit line
Since it is separated from BL and ▲ ▼, the memory cell can be refreshed, and by applying the column address data even during the refresh operation, the data stored in the holding circuit is selected and output by the column address selecting means. On the other hand, when the row address data changes during the refresh operation, the change is detected by the row address change detection circuit, and the detection output is ANDed with the signal REF output from the refresh control circuit, which indicates that the refresh operation is in progress. As a result, a wait signal for prohibiting access to the column address is output to the outside.

(F) Embodiment FIG. 1 is a circuit diagram showing an embodiment of the present invention. The plurality of sense amplifiers (11) are flip-flop type sense amplifiers composed of cross-connected MOSFETs, the bit lines BL and ▲ ▼ are connected to the sense nodes, respectively, and the sense amplifiers (11) perform a sensing operation. MOSFETs (12) (13) with clock signals φ _S1 and φ _S2 to control applied to their gates
Are commonly connected. Further, for each bit line BL and ▲ ▼, a memory cell (15) selected by a plurality of word lines W output from a row address decoder (14) and a dummy cell (dummy cell selected by dummy word lines DW and DW ′ ( 16)
Are connected. The memory cell (15) is a cell composed of one capacitor and one MOSFET. In addition, the bit line BL
And ▲ ▼ are provided with an active restore circuit (17) which operates by a timing signal φ _AR applied after the sense operation of the sense amplifier (11) is completed, and the bit line BL
And the "1" level read in ▲ ▼ is set to the predetermined potential V _DD
Raise to. Also, bit line BL and ▲ ▼ and output line
Between D ₀ and ▲ ₀ ▼, MOSFET (18) and MOSFET (19)
Are connected in series, and the connection point between the MOSFET (18) and the MOSFET (19) is connected to the data input / output of the holding circuit (20). The holding circuit (20) is a depletion type MOSFET (21) connected in series between the power supply V _DD and ground and an enhancement type MOSFET (21).
MOSFET (22) and depletion type MOSFET (2
1) and an enhancement type MOSFET (22), whose inputs and outputs are interconnected. That is,
It is a flip-flop with inverters cross-connected.
Here, the gate of the MOSFET (18) has a sense amplifier (1
The timing signal φ _L which becomes “1” is applied at the timing when the sensing operation of 1) and the operation of the active restore circuit (17) are finished, while the gate of the MOSFET (19) is supplied from the column address decoder (23). Output column line CL
There are respectively connected, on the basis of the column address data A ₈ to A ₁₅ is applied to the column address decoder (23), given MOSFET (19) is selected.

Further, the timing generator (24) to which the chip selection signal ▲ ▼ is applied, the clock φ _S1 , which controls the operations of the sense amplifier (11), the active restore circuit (17), etc., based on the rising edge of the chip selection signal CE. φ _S2 ,
Create pulses such as φ _AR and φ _L. Therefore, when applying new row address data A _{0 to} A ₇ , it is necessary to drop the chip selection signal ▲ ▼. Further, the output from the refresh control circuit (25a) is also applied to the timing generator (24) and is controlled to generate various clocks when refreshing.

The refresh control circuit (25a) refreshes each memory cell (15) on the basis of a refresh request signal REQ periodically applied from the refresh timer (25b), and the row address data A _{0 to} A ₇ Instead, it has a built-in row address counter for selecting the word line W. That is, the row address counter is automatically incremented and its value is set to the row address decoder (1
4) and controls the timing generator (24) to perform a read operation to refresh the memory cell (15). Further, during refresh, a signal REF indicating that the refresh operation is in progress is applied to the AND gate (27) and the row address change detection circuit (28). Row address transition detection circuit (28) receives the row address data A ₀ to A _7, are those row address data A ₀ to A ₇ detects that it has changed the previous state, the detection output ROWCHG is AND gate (2
Applied to the input of 7). The AND gate (27) detects that the row address data has changed during the refresh operation, and when a row address different from the previous one is accessed from the outside, the holding circuit (20). Since the data stored in () is not the data of the accessed row address, the wait signal WAIT for waiting the access of the column address is output until the refresh operation is completed.

As shown in FIG. 2, the specific structure of the row address change detection circuit (28) is a signal change detection circuit (2 which detects rising and falling of each bit of the row address data A _{0 to} A _7.
9) and the output of each signal change detection circuit (29) is applied N
It is composed of an OR gate (30) and an RS flip-flop (31) to which the output of the NOR gate (30) and the output REF of the refresh control circuit (25) are applied. The signal change detection circuit (29) uses the inverted signal ▲ ₀ ▼ (A ₁ ...
With A _7), a circuit for obtaining a pulse output from the inverter (33) NAND gate (35 by the difference between the delay of the delay and the inverter (34) 4-stage 1 stage) and the inverter (36) at the rising edge of the data, The signal A ₀ (A ₁ ... A ₇ ) is used to output the signal A ₀ (from the NAND gate (39) and the inverter (40) due to the difference between the delay of one stage of the inverter (37) and the delay of four stages of the inverter (38). A ₁ ... A ₇ ) and a circuit that obtains a pulse output at the falling edge. Therefore, when the row address data A _{0 to} A ₇ changes, the pulse output of the signal change detection circuit (29) sets the flip-flop (31) via the NOR gate (30). On the other hand, the flip-flop (31) is reset by the signal REF which is "0" except for the refresh operation.
The output of the flip-flop (31) is inverted by the inverter (41) and output as the row address change detection output ROWCHG.

Next, the operation of the embodiment shown in FIG. 1 will be described with reference to FIGS. 3 and 4. FIG. 3 is a timing chart showing the operation during normal data reading, and FIG. 4 is a timing chart showing the operation in the refresh mode. In FIG. 3, when the row select data A _{0 to} A ₇ are applied to the address input terminals not shown in FIG. 1 and the chip select signal ▲ ▼ is set to "0", the timing generator (24 ) Operates and row address data A _{0 to} A ₇
Is applied to the row address decoder (14), and the word line W and the dummy word line DW or DW 'designated by the row address data A _{0 to} A ₇ become "1". When the timing signal φ _S1 becomes “1” in this state, the sense operation of the sense amplifier (11) is started, and the memory cell (15) designated by the word line W and the dummy cell designated by the dummy word line DW or DW ′. (16) The weak potential difference caused by and is generated on the bit lines BL and ▲ ▼, and when the timing signal φ _S2 becomes “1”, the sense operation of the sense amplifier (11) progresses. The difference between bit line BL and ▲ ▼ expands. Next, when the timing signal φ _AR becomes "1", the active restore circuit (17) operates to raise the bit line BL or ▲ ▼ whose "1" level has been read to a predetermined voltage level. Then, when the timing signal φ _L becomes “1”, the MOSFET (18) is turned on, and the potentials of the bit line BL and ▲ ▼ are held via the MOSFET (18) to the holding circuit (2).
0) is applied. At this time, on the bit line side that writes "1" to the holding circuit (20), a write current flows from the active restore circuit (17) that is operating, so that "1" of the bit line is guaranteed, while "0" is written. On the bit line side to be written, the level is lowered to "0" by the sense amplifier (11). In this way, when the data read to the bit line BL and ▲ ▼ is stored and held in the holding circuit (20), the signals on the bit line BL and ▲ ▼ disappear as long as the MOSFET (18) is on. There is no. When the timing signal φ _L becomes “0”, the MOSFET (18) is turned off and the bit lines BL and ▲ ▼ are separated from the holding circuit (20). Therefore, after the separation, the refresh control circuit (25) is operated to enable the refresh operation of the memory cell (15).

On the other hand, in a state in which the data of the designated row address is held in the holding circuit (20) in the row address data A ₀ to A _7, the column address data A ₈ to A ₁₅ is applied to the column address decoder (23) And column address data A _{8 to} A ₁₅
The column line CL designated by is set to "1". This allows MO
The pair of SFETs (19) are turned on, and the data held in the holding circuit (20) passes through the MOSFET (19) to the output lines D ₀ and ▲ _0.
It is sent to ▼ and applied to the output circuit (26). Therefore,
The data specified by the column address data is output from the output terminal D _OUT . Furthermore, if the column address data is applied at any time within the same row address,
The data held in the holding circuit (20) is the column lines CL and MO.
It is selected and output by the SFET (19).

On the other hand, in FIG. 4, the refresh timer (25b)
When the refresh request signal REQ output by the count-up of 1 becomes "1", the refresh control circuit (25) is activated. At this time, the refresh control circuit (25)
Outputs a signal REF indicating that the refresh operation is in progress as "1", increments the row address counter according to the period of the timer, and sends the value to the row address decoder (14). Therefore, the word lines W are sequentially selected and the memory cell (15) is refreshed. Moreover, the application of a column address data A ₈ to A ₁₅ during the refresh operation, the column address data A
_The data held in the column address holding circuit (20) specified by _{8 to} A ₁₅ is output. That is, the column address can be accessed even during the refresh operation. However, when the row address data A _{0 to} A ₇ different from the row address data A _{0 to} A ₇ currently applied to the row address decoder (14) is applied to the row address input terminal, it is applied to the row address decoder (14). Row address data A ₀
Since ~ A ₇ is different from before, the change is detected by the row address change detection circuit (28). Then, as is apparent from FIG. 2, the row address change detection output ROWCHG becomes "1". Therefore, the AND gate (27) obtains the logical product of "1" of the refresh signal REF and "1" of the address change detection output ROWCHG, and the output of the AND gate (27) becomes
It becomes "1". The output "1" of the AND gate (27) is output to the outside as a wait signal WAIT for waiting the access of the column address. This wait signal WAIT "1" prevents erroneous data from being sent to an external device (for example, a microcomputer).

When the refresh operation is completed, the signal REF output from the refresh control circuit (25) becomes "0",
The wait signal WAIT becomes "0" and the access prohibition is released. From this point, the external device can again apply the row address data A _{0 to} A ₇ to perform the normal data read shown in FIG.

(G) Effect of the Invention As described above, according to the present invention, after the row address data is applied and the read data is stored in the holding circuit,
The memory cell can be refreshed, and the column address can be accessed at any time during the refresh operation if the same row address is used. on the other hand,
When different row addresses are accessed during the refresh operation, a wait signal is output, so that incorrect data reading can be prevented. Therefore,
This has the advantage that a highly reliable semiconductor memory that can be easily controlled from the outside can be obtained.

[Brief description of drawings]

FIG. 1 is a circuit diagram showing an embodiment of the present invention, FIG. 2 is a concrete circuit diagram of the row address change detection circuit shown in FIG.
3 and 4 are timing charts showing the operation of the embodiment shown in FIG. 1, and FIG. 5 is a circuit diagram showing a conventional example. Description of main figure numbers (11) Sense amplifier, (14) Row address decoder, (15) Memory cell, (16) Dummy cell, (17)
… Active restore circuit, (20)… Holding circuit, (23)
… Column address decoder, (26)… Output circuit, (24)
... timing generator, (25a) ... refresh control circuit, (25b) ... refresh timer, (28) ... row address change detection circuit, (29) ... AND gate.

Claims (1)

[Claims] 1. A bit line connected to a sense node of a sense amplifier, row address selecting means for selecting a memory cell connected to the bit line based on row address data, and the bit based on column address data. In a semiconductor memory having a self-refresh function, comprising: a column address selecting unit for selecting data read on a line; and a refresh control circuit for sequentially selecting the row address to refresh the memory cell, A holding circuit that holds the read data on the bit line and is separated from the bit line after holding the data is provided, and the data of the holding circuit is selected by the column address selecting means and the row address data is changed. A row address change detection circuit for detecting the A semiconductor memory, wherein a logical product circuit for inputting a control signal for the fresh control circuit provided to the external output as wait signal output of the logical product circuit.