JPS6242393A - Semiconductor memory - Google Patents

Abstract

PURPOSE:To simplify external control and to improve the reliability by providing an AND circuit inputting a detected output of a row address change detection circuit and a control signal of a refresh control circuit and outputting externally the output as a weight signal. CONSTITUTION:When row address data A0-A7 different from row address data A0-A7 applied at present to a row address decoder 14 are applied to a row address input terminal during the refresh, a row address change detection circuit 28 detects the change and a row address change detection output ROWCHG goes to '1'. Thus, an AND gate 27 ANDs a logical 1 of a refresh signal REF with a logical 1 of the address change detection output ROWCHG, and an output logical 1 is outputted externally as a weight signal WAIT awaiting the access of the column address. Thus, the transmission of erroneous data to an external device is prevented.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a semiconductor memory, and more particularly to a dynamic memory in which charges stored in a capacitor are read out by a sense amplifier.

(B) Prior Art A conventional dynamic memory (D-RAM) is constructed as shown in FIG. In FIG. 5, each of the plurality of sense amplifiers (1) is provided with bit lines BL and BL connected to a pair of sense nodes, and each bit line BI and BI are connected to a row address decoder. A plurality of memory cells (3) selected by a plurality of word lines W outputted from (2) are connected, and dummy word lines DW and DW outputted from a row address decoder r2).
The dummy cell (4) selected in is connected. Further, the bit lines BL and [, IK are connected to an active restore circuit (5) that raises the bit line BL or 11 to a predetermined potential after the sensing operation of the sense amplifier (1), and
The MOS FET (7) controlled by the column line CL of the column address decoder (6) is connected to the output circuit (8
) and the output line D0 and bit line BL connected to the input of
and n. On the other hand, row address data A
Row address control signal RAS that controls the application of 0 to A.
, and a chip select signal ○ for selecting a memory chip are applied to a refresh mode detection circuit (9) K, and the detection output thereof is applied to a refresh control circuit QIK. The refresh mode detection circuit (9) detects that the row address control signal RAS becomes "0" after the chip select signal σ3 becomes "0#".
The refresh control circuit αe includes a refresh address counter for sequentially specifying word lines W and a timer, automatically increments the refresh address counter according to the period of the timer, and applies the value to the row address decoder (2). This is to perform a refresh.

In the circuit shown in FIG.
After precharging, one of the word lines W and the dummy word line DW or DW are output, so that the memory cell (3) designated by the bit lines BL and BLK and the dummy cell (4) are connected.

Therefore, the timing signal φ1. When becomes "1", the sensing operation of the sense amplifier (1) is started, and when the timing signal φ becomes "1", the sensing operation rapidly progresses, and the memory cells connected to the bit lines BL and BLK (
A weak potential difference generated by the difference between the charges accumulated in the sense amplifier (1) and the dummy cell (4) is amplified by the sense amplifier (1) iC, and the potential difference between the bit lines BL and TI''II is expanded. ), the timing signal φ, which is output at the timing when the sensing operation of
'', the active restore circuit (5) operates,
The potential of the bit line BL or fTJ, which is at 1 level, is raised to a predetermined potential. In this way, all the sense amplifiers fl+VC are connected to the bit lines BL and BL.
In K, the data of the memory cell (3) specified by the word line W is read out, but after the sensing operation is completed, one of the column lines CL becomes 1'' from the column address decoder (6), so that the pair of data is read out. The MOS FET (71) is selected and turned on, and the data on the bit lines BL and Wl is sent out to the output line via this MOS FET (7), and is output from the output circuit (8). In addition, when refreshing the memory cell (3), set the chip select signal C8 to 'O#, and then set the row address control signal τ] to °0'' to refresh the refresh mode detection circuit (9). ) outputs a detection output, and the refresh control circuit [alpha] operates.As a result, the word lines W are sequentially selected at the timer cycle and refreshed regardless of the row address data A.--person.

This is how the RAM is described, from pages 169 to 192 of Nikkei Electronics, published on July 18, 1982.
It is written on the page.

(c) Problems to be Solved by the Invention By the way, in the conventional D-RAM shown in FIG. 5, the normal reading method is to apply column address data after applying row address data. However, in order to increase the read speed, after applying row address data, column address data is sequentially applied to select the bit lines BL and 11 and read the data (page mode) or applying row address data. After that, a nibble mode is realized in which data is read by applying column address data and alternately setting the column address control signal CD to "0" and "1".Furthermore,
A static column method has been implemented in which data can be read by simply applying a column address within the same row address after applying row address data.

However, in either method, data generated on each bit line BL and BL changes during memory cell freshening, so it is difficult to read data stored at a column address within a specified row address before refreshing. I can't.

Therefore, there is a drawback that memory access must wait until refresh is completed.

B) Means for Solving the Problems The present invention has been made in view of the above-mentioned points, and the present invention has been made in view of the above-mentioned points.
In a semiconductor memory with a built-in self-refresh function, the bit line A holding circuit is provided which holds the data read out to bit lines BL and 11 and is separated from the bit lines BL and 11 after holding the data.The holding circuit selects the data with the column address selection means and selects the row address data. A row address change detection circuit that detects a change, and an AND gate that inputs the detection output of the row address change detection circuit and a control signal of the refresh control circuit are provided, and the output of the AND circuit is weighted. It is output to the outside as a signal.

(E) Operation According to the above-mentioned means, in a normal read state, when a-address data is applied, the word line W designated by the row address data is selected, and this word line Wf
f. The data of the connected memory cells is read out from the bit lines BI and BLK by the sense amplifier, and further, after the sensing operation of the sense amplifier is completed, the read data is stored in the holding circuit. Since the holding circuit that stores the data is separated from the bit lines BL and Sho I, memory cell flexibility is possible, and by applying column address data even during the refresh operation, the data stored in the holding circuit can be transferred to the column. It is selected and output by the address selection means. On the other hand, if the row address data changes during the refresh operation, the change is detected by the row address change detection circuit, and the detection output is ANDed with the signal REF output from the refresh control circuit indicating that the refresh operation is in progress. As a result, a wait signal for prohibiting column address access is output to the outside.

(f) Example FIG. 1 is a circuit diagram showing an embodiment of the present invention.

Multiple sense amplifiers αυ are cross-connected MOSFEs.
It is a 7-lip, 70-tub type sense amplifier consisting of T, and bit lines BL and 11 are connected to the sense nodes, respectively.
In addition, the sense amplifier (+DVc is a MOS whose gate is applied with clock signals φ□ and φ that control the sense operation
FET(L5(13) is commonly connected.

Furthermore, a memory cell α9 selected by a plurality of word lines W outputted from the row address decoder side and a dummy cell (161) selected by dummy word lines DW and DW are connected to each bit line BL and 11. Memory cell ([
51 is a cell consisting of one capacitor and one MOSFET. Furthermore, bits iBL and BI are provided with an active restore circuit aη that operates according to a timing signal φA1 applied after the sensing operation of sense amplifier α1) is completed, and the “1” level read to bins #BL and BL is are raised to predetermined potentials I and D. Moreover, between the bit lines BL and 11 and the output line D0 and the trace,
The MOSFETα group and MOSFET9 are each connected in series, and the connection point between MOSFETCl and MOSFETα9 is connected to the data input/output of the holding circuit (2). The holding circuit (■) consists of a depletion type MOSFET7C11) connected in series between power supplies VI and D and ground, and an enhancement type MOSFET M
OSFETU and depression type MOS F
E Tel! I) & enhancement type MOSF
ET (221), whose inputs and outputs are interconnected. That is, it is a flip-flop with cross-connected inverters.

Here, a sense amplifier (l11 sense operation and active restore circuit α
At the timing when the operation of η is completed, a timing signal φ1 is applied such that “l′←Tanewa Saki 2 呵樗”, and on the other hand, the MOSF
The column lines CL output from the column address decoder are connected to the gates of ET (19), and the column address data A,
Based on ~A,,K, the specified MOSFET (1!J
is selected.

In addition, the timing generator +24)+s to which the chip selection signal σ is applied, and the clocks φ□, φ, which control the operations of the sense amplifier aυ, the active restore circuit (171, etc.) based on the falling edge of the chip selection signal CE. φ
1. ．． Create a pulse such as φ1. Therefore, when applying new row address data A0 to A, it is necessary to lower the chip selection signal. Further, the output from the refresh control circuit (25a) is also applied to the timing generator @, and it is controlled to generate various clocks when refreshing.

The refresh control circuit (25a) refreshes each memory cell (15) based on the refresh request signal REQK periodically applied from the refresh timer (25b), and refreshes each memory cell (15) by updating the row address data A0 to A.
, has a built-in row address counter for selecting the word line W. That is, the row address counter is automatically incremented, the value is applied to the row address decoder ak, and the timing generator (124
is controlled to perform a read operation and refresh the memory cell α9. Further, a signal REF indicating that the refresh operation is in progress is applied to the AND gate (5) and the row address change detection circuit @. The row address change detection circuit □□□ detects row address data A0 to A,
Enter the raw address data of the person. ~A.

The detection output ROWCHG is applied to the input of the AND game [7]. The AND gate (3) is used to detect a change in the row address data during a refresh operation, and when there is an external access to a row address that is black from the previous one, the holding circuit Since the data stored in is not the data of the row address that was accessed, a wait signal WAIT is output to make access to the column address wait until the refresh operation is completed.

The specific configuration of the row address change detection circuit (support) is as shown in FIG. 2, as shown in FIG. ~N.

of the signal change detection circuit that detects the rise and fall of each bit of and an R-8 flip-flop Gυ to which the output REF is applied. The signal change detection circuit detects the inverter's two inverted signals A, (A, -
A, ) is used to obtain a pulse output from the NAND gate (to) and inverter (to) at the rising edge of data based on the difference between the delay of the 1331-stage inverter and the delay of the 4-stage inverter (2), and a signal generator. Using (AI...A,), the difference between the delay of 1 stage of inverter G7 and the delay of 4 stages of inverter (to) is determined by the NAND game) C31 and the signal A from inverter (4). (Al... It consists of a circuit that obtains a pulse output at the time of A7).Therefore,
Row address data A. -A.

When changes, the pulse output of the signal change detection circuit becomes NOR.
The flip-flop Gυ is set via the gate (7). On the other hand, the clip flop Gυ is reset by the signal REF which is "O" except for refresh operations. The output of flip-flop Gυ is inverted by inverter 0υ, and the row address change detection output ROW CHG
is output as

Next, the operation of the embodiment shown in FIG. 1 will be explained with reference to FIG. 31S4 and FIG. FIG. 3 is a timing diagram showing operations during normal data reading, and FIG. 4 is a timing diagram showing operations in refresh mode. Third
In the figure, row address data A is input to an address input terminal not shown in FIG. -A? With the applied
When the chip selection signal σ1 is set to “O”, the timing generator @ operates and the row address data A0
~A, is applied to the row address decoder (14), and the row address data A. The word line W and the dummy word line DW or DW designated by -A become "1". In this state, the timing signal φ8. When becomes “1”, the sensing operation of the sense amplifier (1υ is started, and the memory cell α9 specified by the word line W and the dummy word line DW or D~
The weak potential difference caused by the dummy cell (161) specified by V is amplified and generated in bits IBL and BL, and furthermore, the timing signal φ1! becomes "1", and the sensing operation of the sense amplifier αυ progresses. , furthermore, the difference between the bit lines BL and 1 increases.Next, when the timing signal φ,8 becomes 1'', the active restore circuit η
operates and raises the bit line BL or 11 from which the '1' level has been read to a predetermined voltage level.

After that, when the timing signal φ5 becomes "1", MO8F
ETQS is turned on, and the potential of the bit line BL and "l" is applied to the holding circuit (A) via MO8FFTaS. At this time, on the bit line side that writes "1#" to the holding circuit (■), the active restore Since the write current flows from the circuit aη, 1” of the bit line is guaranteed, and on the other hand,
On the bit line side where “0” is written, sense amplifier α1)K
Therefore, it is lowered to the level of ``0#.'' In this way,
When the data read to the bit line BL and 1 is stored and held in the holding circuit (21), the signals on the bit line BL and 1t will not disappear as long as the MO3FETQ barrel is on. When the timing signal φ5 becomes "0" at field 4, the MOS FETQe turns off, and the bit line BI,
The BL and the holding circuit NN f2I are separated. By operating the full run control circuit 4 after being separated at υt, refresh operation of the memory cell negative 9 becomes possible.

On the other hand, row address data A is stored in the holding circuit. When the column address data A6 to A15 is applied to the column address decoder (23) while the row address data specified by ~A is held, the column address data A
, ~A The column line CL designated by H5 becomes 1Jtll. As a result, the pair of MO3F'ETα9 is turned on, and the data held in the holding circuit f2f)K is transferred to the MOSFET.
It is sent to the output line via ET (1!
The data specified by the column address data is output from. Furthermore, within the same row address, whenever column address data is applied, the data held by the holding circuit (21 VC) is transferred to the column line CL and MO5.
It is selected and output by FEln.

On the other hand, when the refresh request signal REQ outputted by the count-up of the refresh timer (25b) reaches "l#" in 'tlE4 FIG. 1, the refresh control circuit (c) becomes operational. At this time, the refresh control circuit When the device outputs the signal REF indicating that it is in the refresh operation as "1", it increments the row address counter according to the period of the timer and sends out the value to the row address decoder 04IVc. are sequentially selected and the memory cell (I!1
9 refresh is executed. Also, during the refresh operation, column address data A, ~A1 . is applied, column address data A, ~A1 . The data held in the holding circuit (■) of the column address specified by is output. That is, column addresses can be accessed even during a refresh operation. However, the row address data A0 currently applied to the row address decoder (14)
~Person, and different row address data A. -A is applied to the row address input terminal, the row address data A0 to A applied to the row address decoder α are different from those before, so the change is detected by the row address change detection circuit @. Then, as is clear from FIG. 2, the row address change detection output ROWCHG becomes "12".

Therefore, in the AND gate, the refresh signal R
EF “1” and address change detection output ROWCHG “
1” and the output of the AND gate amount is “1#”
becomes. The output 11'' of this AND game [7] is a wait signal WAIT that waits for column address access.
It is output externally as . This wait signal WAIT''
The "1" prevents erroneous data from being sent to an external device (for example, a 1 microcomputer).

When the refresh operation is completed, the refresh control circuit (
Since the signal REF output from (to) becomes "O", the wait signal WAIT becomes "60", and the access prohibition is canceled.From this point on, the external device again writes the row address data Ao-A.

By applying , it becomes possible to perform normal data reading as shown in FIG. 3.

(G) Effects of the Invention According to the present invention as described above, after the data read by applying row address data is stored in the holding circuit,
Memory cell refresh: L operation is possible, and
Even during a refresh operation, a column address can be accessed at any time as long as it is the same row address. On the other hand, if a different row address is accessed during a refresh operation, a wait signal is output, thereby preventing erroneous data reading. Therefore, it has the advantage of providing a highly reliable semiconductor memory that is easy to control from the outside.

[Brief explanation of the drawing]

Figure f741 is a circuit diagram showing an embodiment of the present invention, Figure 2 is a specific circuit diagram of the row address change detection circuit shown in Figure 1, and Figures 3 and 4 are the same as shown in Figure 1. A timing diagram showing the operation of the embodiment, and Figure @5 is a circuit diagram showing a conventional example. Description of main figure numbers 0υ...Sense amplifier, (14)...Row address decoder, 09...Memory cell, Oe...Dummy cell, (171...Active restore circuit,
(21...Holding circuit, @...Column address decoder, (A)...Output circuit, t24)...Timing generator, (25a)...1y fresh control circuit, (25b)... Refresh timer, 2... Row address change detection circuit, ■...
・AND gate. Applicant Sanyo Electric Co., Ltd. and one other representative Patent attorney Shizuo Sano
5-wo Figure 4 WANT Figure 5

Claims (1)

[Claims] 1. A bit line connected to a sense node of a sense amplifier, a row address selection means for selecting a memory cell connected to the bit line based on row address data, and a row address selection means based on column address data. and a refresh control circuit that sequentially selects the row addresses and refreshes the memory cells. A holding circuit is provided which holds data read out to the bit line and is separated from the bit line after holding the data, and the data in the holding circuit is selected by the column address selection means, and the data read out to the bit line is separated from the bit line. A row address change detection circuit that detects a change in address data, and an AND circuit that inputs the detection output of the row address change detection circuit and the control signal of the refresh control circuit are provided, and the output of the AND circuit is weighted. A semiconductor memory characterized by external output as a signal.