JPH04106782A - Semiconductor storage device - Google Patents

Abstract

PURPOSE:To shorten the average cycle time of the semiconductor storage device by executing pre-charge of a bit line and sense amplification of a memory cell, in the case a row address is varied, and executing read/write of data of a necessary address in the next cycle. CONSTITUTION:When a row address is varied at the start time of a cycle 2, this variation is transferred to a latch circuit 81. Since the previous row address is held in a latch circuit 82, an output TA8 of an exclusive OR circuit 16 becomes H, and a nodal point N1 becomes H. The potential of the nodal point N1 is held in a latch circuit 83, and becomes a BUSY signal. In the cycle 2, a pre-charge signal BLEQ is generated by the BUSY signal, and pre-charge of a bit line BL and sense amplification of memory cell data of a new row are executed. The BUSY signal inhibits an operation of a column decoder in the cycle 2. In a period in which the signal BLEQ is H, the potential of a pair of bit lines is pre-charged to 1/2Vcc. After the bit line is pre-charged, a word line rises, and data of a prescribed memory cell in a memory cell array is read to a pair of bit lines.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor memory device suitable for use in conjunction with a microprocessor that operates with a high frequency clock.

[Conventional technology]

In recent years, with advances in semiconductor technology, the clock frequency of microprocessors has increased. For example, as shown in FIG. 11, the microprocessor receives a clock signal CLK.
During cycle 10, the data read from the semiconductor memory device according to the read address is processed, and during cycle 2, the data is written to the semiconductor memory 5 device. Therefore, the clock cycle time can be shortened. For example, the number of times that can be processed per unit time increases, speeding up the equipment,
Enables higher performance. To reduce cycle time,
Reduces microprocessor calculation time. At the same time, the cycle time of the semiconductor memory device must also be shortened.

Figure 12 is I E E E Journal 5ol
id-state C1r-cuits, Vol, 22
．． NO, 5, 0ctober 1987, pages 657 to 662, D which shortens the cycle time without multiplexing the row address signal and column access method.
It is a schematic block diagram of RAM (dynamic RAM).

In the diagram, 21 is a row address buffer, 4 is a row decoder, 5 is a memory cell array, 6 is a column decoder, 7 is a column address bar, 7.8 is a memory control circuit, and 9 is an input/output circuit.

The row decoder 4 selects one row of memory cells arranged in a matrix according to the row address signal A8~^)6 supplied via the row address buffer 1, and the column decoder 6 similarly selects a row of memory cells arranged in a matrix. Column address signal A
Go to O-A7 and select one example of the memory cells, thereby selecting one memory cell. The WE signal supplied to the control circuit 8 specifies a write cycle, and the OE@ signal specifies a read cycle.

Next, the operation of the DRAM shown in FIG. 12 will be explained using timing diagrams shown in FIGS. 13 and 14 showing the sense amplifier circuit of the DRAM.

In Figure 13, 26 is a sense amplifier, 27.2B, 29
．． 30 is MOSFET, 31.32 is capacitor, W
L.

W L + is a word line, BL, BL is a bit line, Ilo
, Ilo is the I10 line. At the start time ta of the read cycle l in FIG.
At time tl when C is precharged, the word line WLo corresponding to the input address becomes "H", and the bit line BL
The memory cell capacitor 31 is connected to the bit line pair, and at time t2, when a potential difference occurs between the bit line pairs, the sense amplifier 26 is operated to amplify the potential difference.At time t3, the bit line pair selected by the tar decoder 6 is connected to the I10 line. The signals are read out in pairs and read out of the chip via the input/output circuit 9.

At the start time t4 of write cycle 2, the beep and g lines BL and B
At 0 time t5 when L is precharged to -VCC, the word line W Lo corresponding to the manual address becomes "H", the memory cell capacitor 31 is connected to the bit line BL, and a potential difference occurs between the bit line pair. Sense amplifier 2 at t6
At time 1+, data on the I10 line pair is written only to the bit line pair selected by the column decoder 6, and this data is written into the memory cell capacitor 31.

[Problem to be solved by the invention]

Since the conventional semiconductor memory device is configured as described above, the time of one cycle of the clock signal CLK is
The problem is that the cycle time cannot be shortened sufficiently because the time required to precharge the bit line and the operating time of the sense amplifier of the memory cell are the sum of the data read and write times for the beat line pair selected by the single column decoder. there were.

In the circuits of FIGS. 12 and 13, there is an access method called static column mode, as shown in the operation timing diagram of FIG. 15. In FIG. 15, the read operation from time to to t3 is the same as the read operation in FIG. 14. 1st
In FIG. 4, the clock signal CLK is set to "H" at time t4, but in FIG. 15, only the column address is changed without setting CLK to "H" at time t4. As a result, the DRAM detects the address change and equalizes the I10 line,
The same operation occurs when only the 0th and 1st column address at which the column decoder 6 selects a bit line pair changes at time t5. 2
When reading the 3rd and 3rd data,
) Since no charge or sense amplifier is required, the cycle time of cycles 2 and 3 can be shortened compared to the time of cycle 1.

However, in this static column mode access method, a read/write cycle for data with the same row address but a different column address is faster than a read/write cycle for data with a different row address than a clock signal CLK.
In addition to shortening the cycle time, there is also the problem that the control of the clock signal CLK itself becomes complicated, such as not setting the clock signal CLK to "H" during one read/write cycle of data that differs only from this column address. Ta.

In addition, in conventional semiconductor memory devices using DRAM, SR
IEEE 15SCC as a configuration of memory that does not need to be refreshed, such as AM (static RAM).
DIGEST OF TECHNICAL PAPER
5, Feb.

Pseudo S shown in 1986, pp. 252-8253.
There is RAM. FIG. 16 shows a schematic configuration of this pseudo SRAM.

In FIG. 16, 1 is a row address buffer, 4 is a row decoder, 6 is a column decoder, 7 is a column address buffer, and 8 is a row address buffer.
9 is a control circuit, 9 is an input/output circuit, 41 is a refresh timer, 43 is a selector, and 44 is a refresh address counter.

The operation of the pseudo SRAM shown in FIG. 16 will be explained with reference to the timing chart shown in FIG. 17. Memory cell data selected at time t1 by a word line corresponding to an input address is amplified by a sense amplifier, similar to a DRAM, and read out to the outside via input/output circuit 9 at time t2.

By the way, in such a pseudo SRAM, the refresh timer 41 issues a refresh request at regular intervals,
The refresh address counter 44 is incremented by 1 for each refresh operation, and the memory cell selected by the word line of the generated row address is refreshed.

In cycle 2, when a refresh request is input from the refresh timer 41, following the read operation corresponding to the input address at time t3, the selector 43 inputs the output of the refresh address counter to the row decoder 4 at time t4. The word line specified by the refresh address counter is selected and a refresh operation is performed.

This configuration has the problem that the memory cycle time is sufficient to complete two read operations, one for normal use and one for refresh, and that it is impossible to shorten the cycle time.

The present invention was made to solve the problems of conventional semiconductor memory devices as described above, and the first object is to obtain a semiconductor memory device in which the average cycle time of the semiconductor memory device is shortened. The second object is to obtain a semiconductor memory device using DRAM in which the average cycle time does not increase even if it is equipped with an automatic refresh function.

(Means for Solving the Problems) A semiconductor memory device according to a first embodiment of the present invention includes a detection circuit that detects a change in a row address, and when a row address changes, a microprocessor is activated. It notifies that the data read/write operation at the desired address will be completed in the next cycle, and also precharges the bit line and amplifies the sense of the memory cells in the row after the address change. When the data at the address is read/written and the row address does not change, reading of the data at the required address is completed in the first cycle.

A semiconductor memory device according to a second embodiment of the present invention includes a refresh timer, and in a cycle in which a refresh request occurs, a signal is generated to notify a microprocessor that refreshing is in progress, and data is read in the next cycle. / Instructs to re-execute the write operation, refreshes the row specified by the refresh address counter, and operates in the same manner as the first invention for the read/write operation re-executed in the next cycle. It was designed to do so.

[For production]

In the semiconductor memory device of the present invention, the clock cycle time is set to a time as short as the cycle time of the static column mode, and the semiconductor memory device receives a signal indicating a change in the row address or a refresh signal. Only when the microprocessor receives a signal indicating that the process is in progress, the microprocessor stops operation for l cycles and reads/writes data in the next cycle.If the 0 column address is set as the lower address, , the frequency at which the row address changes is smaller than the frequency at which the column address changes, therefore, the clock cycle time can be reduced on average to the same level as the cycle time in the two-column mode without complicated control of the clock period. can do.

〔Example〕

Hereinafter, the present invention will be explained in detail with reference to illustrated embodiments.

In FIG. 1, l is a row address buffer, 2 is a row address change detection circuit, and 3 is a bit line precharge signal BL.
4 is a row decoder; 5 is a memory cell array; 6 is a signal generation circuit that generates an EQ and sense amplifier activation signal SE;
7 is a column decoder, 7 is a column address/<tufer, 8 is a memory control circuit, 9 is an input/output circuit, and 42 is a BUSY signal generation circuit. In the device shown in FIG. 1, a row address change detection circuit,
The structure of the other parts except for the signal generating circuit 3 and the BUSY signal generating circuit 4z is the same as that of the conventional semiconductor memory device shown in FIG.

FIG. 2 shows the row address change detection circuit 2, signal generation circuit 3, BUSY signal generation circuit 42. 2 is a schematic configuration diagram of a circuit that generates clock signals CLK, , CLK2 to each of these circuits. In the figure, the row address change detection circuit 2 receives address signals A8 to A through the row address buffer 1.
A plurality of circuits 18 of the same structure are provided which are supplied with s6.

In FIG. 2, l0111. 19 is an n-type MOSFET, 1
2.13.14.15.20.21.22.36, Ko9
is an inverter, 23.35 is a delay circuit, 24 is a NOR circuit, 16 is an exclusive OR circuit, 17.40 is an OR circuit, 2
5.37.38 is an AND circuit.

The operations in FIGS. 1 and 2 will be explained with reference to the operation timing chart in FIG. 3 and FIG. 13 shown earlier. cycle 2
When the row address changes at start time t1, this change in the row address is transferred to the start circuit 81 formed of inverters I2 and +3 via the n-type MO3FETIO in response to the clock signal CLK. Since the previous row address is held in the latch circuit 82 consisting of inverters 14 and 15, the output TA of the exclusive OR circuit 6 is “H”.
”, and the node Nl of the output of the OR circuit 17 becomes “H”.The potential of the node N1 becomes n-type M in response to the clock signal sum.
The signal is held in a latch circuit 83, which includes an inverter za and an inverter 21 connected to the OSFET+5, and becomes a BUSY signal.

In cycle 2, the BUSY signal and clock signal CLK2
A precharge signal BLEQ is generated by ANDing the bit line BL and performs sense amplification of memory cell data in a new row. The BUSY signal is supplied to column decoder 6 to inhibit operation of column decoder 6 in cycle 2. After the bit line pair is recharged while the precharge signal BLEQ is "H", the word line W L + rises, and the data of a predetermined memory cell in the memory cell array 5 is read onto the bit line pair.

The sense amplifier activation signal SE is generated by ANDing the BUSY signal and a signal delayed from the clock signal CLK2, and is generated at time t.
3 to activate the sense amplifier 26. Further, in a cycle in which the row address does not change, the BtJSY@ signal becomes "H", the sense amplifier activation signal SE becomes "H", and the data on the bit lines BL and BL are held.

FIG. 4 is a schematic configuration diagram of a system combining a semiconductor memory device M34 and a microprocessor 33 according to the present invention. Microprocessor 33 supplies address signal A dd, output activation signal OE, and write signal WE to storage device 34, and reads/writes data on bidirectional data line I10.

Also, the memory device M34 uses the BUS when the row address changes.
The Y signal is supplied to the microprocessor 33.

Semiconductor storage device 7134 and microprocessor 3 in FIG.
The operation of the device in combination with No. 3 will be explained with reference to the operation timing diagram of FIG.

In FIG. 5, an address in which only the column address has changed in cycles 1 and 2 is supplied from the processor 33 to the storage device 34, and data is read/written through the data line I10 during the same cycle. The address whose row address changed in cycle 3 is supplied from the processor. The semiconductor memory device 34 detects that the row address has changed and
supplying the USY signal to the processor 33;
is instructed to do nothing in this cycle and re-execute the operation of this cycle in the next cycle, as well as sense amplify the memory cell data of the new row, and in cycle 4, the address accessed in cycle 3 is read and write data. In cycle 5.6, an address in which only the column address has changed is supplied from the processor at intervals of clock signal CLK, and data is read and written during the same cycle.

Note that although a positive polarity BUSY signal is used, a negative polarity Ready signal (that is, when it is "H", data is output in that cycle) may also be used.

Next, a second embodiment of the invention will be described with reference to FIG. In the figure, 41 is a refresh timer, 43 is a selector, and 44 is a refresh address counter. The structure of other parts is the same as that of the device shown in FIG.

FIG. 7 is a diagram showing an example of the configuration of the refresh timer 41,
FIG. 8 is a timing diagram explaining the operation. In the same figure, 45, 46, 48, 49 are MOSFETs, 5
0 is resistance, 51 is capacitor, 52.53.54.55
is an inverter, and 56 is a delay circuit. The potential at the node between the resistor 50 and the capacitor 51 rises according to the RC time constant determined by the resistor 50 and capacitor 51, and in cycle 2, the potential at the node increases according to the clock signal C.
The refresh request signal REFREQ becomes "H" after being transmitted via the MOSFET 45 driven by LK.This "H" refresh request signal REFREQ is transmitted to node A via the MOSFET 46 driven by the delayed clock signal CKL1, and the refresh request signal REFREQ becomes "H". The potential of A becomes "H". At the same time, the MOSFET 48 is turned on by the potential at the node A, the capacitor 51 is discharged through the MO3FET 48, and the potential at the node becomes low level.

At the beginning of cycle 3, the MOSFET 45 is turned on, and since the node potential is at a low level at this time, the refresh request signal REFREQ becomes L".

At time tl of cycle 3, the MOSFET 46 is turned on by the clock signal CLKI, the refresh request signal REFREQ of 'L' is transmitted to the node A, the potential of the node A becomes 'L' again, and the MOSFET 4B is turned off. The potential of each node increases at a speed determined by the RC time constant.

Figure 9 is '! The BUSY signal generating circuit 4 in FIG. 2 is the same as the BUSY signal generating circuit 4 in FIG.
It is the same as 2.

Next, the operation of the apparatus shown in FIG. 6 will be explained with reference to the timing diagram shown in FIG. 10. In cycle 2, refresh request signal R
When EFREQ becomes "H", the selector 43 supplies the output of the refresh address counter 44 to the row decoder 4, and the BUSY signal generating circuit 42 generates the BUSY signal. In response to the BUSY signal, the precharge/sense activation signal generating circuit 3 controls bit line equalization and sense amplification in the same way as the circuit shown in FIG. 1, and reads out the memory cells in the row to be refreshed.

The microprocessor that receives the BUSY signal performs the same read operation in the next cycle. BUSY in Figure 10
The solid line of the signal indicates the case where the refreshed row and the re-read row are the same. If the address of the refreshed row is different from the address of the re-read row, as shown by the broken line of the BUSY signal in FIG.
The SY signal is generated to cause the microprocessor to re-perform the read for one more cycle.

A cycle in which the address of the refresh requested row and the address of the re-executed read row do not change can be shortened to the same extent as the cycle time of the static column mode of a DRAM.

〔Effect of the invention〕

As mentioned above, the first aspect of the present invention explained with reference to FIG.
According to the embodiment, the cycle time of a semiconductor memory device using DRAM memory cells can be shortened on average to the same level as the cycle time of a static column mode DRAM. Therefore, even if the capacity of the storage device is increased using DRAM memory cells, it can be used in a cycle time equivalent to that of SRAM, so a memory system for high-speed microcontrollers can be provided at low cost.

According to the second embodiment of the present invention described with reference to FIG. 6, even if the DRAM memory cell has the function of automatically refreshing, it is not necessary to increase the cycle time as in the pseudo SRAM described in FIG. 16. Because there is no, it is more S
It is possible to provide a high-speed storage device similar to RAM that does not require refreshing.

[Brief explanation of drawings]

FIG. 1 is a schematic configuration diagram of a semiconductor memory device according to a first embodiment of the present invention, and FIG. 2 is a row address change detection circuit, bit line precharge, and sense amplifier activation signal generation in the device of FIG. circuit, BUSY signal generation circuit and clock signal CLK
3 is an operation timing diagram for explaining the operation of the device shown in FIGS. 1 and 2, and FIG. 4 is a first implementation of the present invention shown in FIG. 1. A diagram showing a combination of a semiconductor storage device and a microprocessor according to an example; FIG. 5 is an operation timing diagram illustrating the operation of the combination circuit of the semiconductor storage device and microprocessor of FIG. 4; FIG. 7 is a circuit diagram showing an example of a refresh timer used in the semiconductor memory device of FIG. 6; FIG. 1g8 is a circuit diagram showing an example of the refresh timer operation of the semiconductor memory device of FIG. 7; FIG. 9 is an operation timing diagram explaining the BUSY used in the semiconductor memory device of FIG.
10 is an operation timing diagram for explaining the operation of the semiconductor memory device of FIG. 6; FIG. 11 is an operation timing diagram for explaining the operation of a microprocessor in general; 13 is a schematic configuration diagram showing an example of a conventional semiconductor memory device, FIG. 13 is a diagram showing a conventional DRAM sense amplifier circuit, FIG. 14 is an operation timing diagram explaining the operation of the sense amplifier circuit in FIG. 13, 815 is the semiconductor memory device of FIG. 12, and FIG. 16 is an operation timing diagram showing an access method in static column mode. FIG. 16 is a schematic configuration diagram showing an example of a semiconductor memory device using pseudo SRAM. 17 is an operation timing diagram illustrating the operation of the semiconductor memory device using the pseudo SRAM of FIG. 16. FIG. In FIG. 1 and FIG. 6, l... row address buffer, 2... row address change detection circuit, 3... bit line precharge, sense amplifier activation signal generation circuit, 4... ...Row decoder, 5-...Memory array, 6
... Column decoder, 7... Column address buffer,
8... Control circuit, 9... Input/output circuit, 41...
. . . Refresh timer, 42 . . . BUSY signal generation circuit, 43 . . . Selector, 44 . . . Refresh address counter.

Claims (2)

[Claims] (1) A memory cell array arranged in a matrix, a sense amplifier that amplifies data of one row of memory cells, and a row decoder that selects a row of the memory cell array according to a row address signal supplied to a row address signal input terminal. and,
a column decoder for selecting a column of the memory cell array according to a column address signal supplied to a column address signal input terminal; and a clock input terminal to which a clock signal defining the start of each memory cycle is supplied; In a first memory cycle in which the input address signal of changes, a first signal is generated, and in a cycle subsequent to the first memory cycle, reading and writing of the memory cell accessed in the first memory cycle is executed. However, in the second memory cycle in which the input address signal of the row decoder does not change, read and write operations of the memory cell are completed within the second memory cycle. (2) A memory device that is equipped with a DRAM memory cell, a refresh request generation circuit, a refresh address generation circuit, and a clock input terminal to which a clock signal that defines the start of each memory cycle is supplied, and in which a refresh request signal is generated. In a semiconductor memory device, during recycling, read and write operations are invalidated, a row address generated by the refresh address generation circuit is refreshed, and a first signal is supplied outside the chip.