JPH01263995A - Dynamic semiconductor storage element - Google Patents

Abstract

PURPOSE:To prevent erroneous discrimination of data by providing a sense amplifier activating timing generating circuit which can change the sense amplifier activating timing in response to a request from the outside and a circuit which causes a wait signal to be outputted against the outside in accordance with the timing generated by the generating circuit. CONSTITUTION:A sense amplifier 1 which compares memory cell data with reference cell data is activated by a sense amplifier activating signal given from a sense amplifier activating timing generating circuit 2 through a signal line 6. When a chip activating signal is inputted to an input buffer 3, a signal which activates the sense amplifier activating timing generating circuit 2 is outputted to a signal line 4. On the other hand, when a timing changing request is inputted to the circuit 2 from an external voltage variation detect circuit through a signal line 5, the signal line 6 transmits the signal which changes the sense amplifier activating timing to the sense amplifier. When the sense amplifier activating timing is changed, a wait signal generating circuit 7 generates a wait signal against the outside. Therefore, erroneous discrimination of data can be prevented.

Description

[Detailed Description of the Invention] [Industrial Application Fields] The present invention stores extremely small charges in the cell itself, and substantially reduces the read/write operation by amplifying the potential of the accumulated charges in the cell using a sense amplifier. The present invention relates to a dynamic semiconductor memory element characterized in that it is performed in a dynamic manner.

[Prior Art] Conventionally, in this type of dynamic semiconductor memory element, the storage capacity per chip has quadrupled every three years, and it is difficult to form many small memory cells on a chip of approximately the same size. This is a major factor that determines the quality of the product.

On the other hand, as microprocessors and peripheral LSIs become faster, the timing of activating a sense amplifier, which is activated after a micromemory cell is connected to a data line, is becoming smaller as the cell area decreases (therefore, the potential change due to the cell is becoming smaller). (even though things tend to slow down), they have been shortened. (This timing reduction applies not only to the sense amplifier but also to the address buffer, data in/out buffer, I10 amplifier, etc.) [Problems to be solved by the invention] However, with the above-mentioned conventional technology, The sense amplifier that amplifies the stored potential (hereinafter referred to as data) cannot be of sufficient size due to the layout of the memory cells (in a cell array consisting of rows and columns, one sense amplifier occupies the space between the memory cells as shown in Figure 3). There is also a limit to the sense sensitivity (the size is limited depending on the size), and the timing for activating the sense amplifier has been shortened due to the demand for higher speeds, so even if the cell data is lost even slightly due to voltage fluctuations, etc. If insufficient, the read/write operation will be executed before the sense amplifier can detect a change in the potential of the data line due to the data in the memory cell, and as a result, data will likely be erroneously determined.

Therefore, a situation arises in which the detection capability originally possessed by the sense amplifier is not fully utilized, resulting in a drawback that the operating margin is narrowed.

Furthermore, even if the cell data is sufficient, this state occurs when the memory cell is connected to the data line during a read/write operation and the sense amplifier is activated next. The same problem can occur even when the output is relatively fast at low temperatures or when the power supply voltage is high.

[Differences between the invention and the prior art] In the prior art described above, the sense amplifier activation signal always has a constant timing, and if it deviates even slightly from the expected memory cell data level due to noise, power supply fluctuations, etc., sensing becomes impossible. (Therefore, the data will be incorrect). - The strength tree invention is different in that the timing can be switched internally or externally as necessary.

Means for Solving Problems] The dynamic semiconductor memory element of the present invention has a sense amplifier activation timing generation system that can change the sense amplifier activation timing during normal use in response to requests from inside or outside the chip. and a wait signal output circuit that outputs a wait signal to the outside in accordance with the sense amplifier activation timing generated by the timing generation circuit.

[Example code] Next, the present invention will be explained using examples.

FIG. 1 is a block diagram of one embodiment. In the figure, reference numeral 1 denotes a sense amplifier for comparing memory cell data and reference cell data, and is activated by a sense amplifier activation signal applied from a sense amplifier activation timing generation circuit 2 through a signal line 6. Reference numeral 3 denotes an input buffer, into which chip activation signals, address signals, etc. from the outside are manually input. When a chip activation signal is manually input to this buffer, a signal that activates the sense amplifier activation timing generation circuit 2 is output to the signal line 4 (
This is the normal access timing). On the other hand, when a timing change request from an external voltage fluctuation detection circuit is input to the sense amplifier activation timing generation circuit 2 via the signal line 5, the signal line 6 changes the sense amplifier activation timing. (This is the timing when the change is made.) 7 is a wait signal generation circuit that generates a wait request to the outside when there is a timing change. Fig. 2 shows the above timing. In Fig. 2, the sense signal is output when the timing is changed. I'm trying to keep her awake.

After this change, microprocessors and the like will be able to know from this wait signal that data access is becoming slower.

The voltage fluctuation (or drop) detection circuit used in this example outputs a detection signal to the outside when a predetermined voltage range is exceeded, and is composed of a Zener diode, a transistor, an operational amplifier, etc. This is a known circuit.

Another possible external timing change request is a change in temperature that exceeds the recommended operating range, and in this case the sense timing must be delayed. In this case, a temperature detection circuit including an external temperature sensor may be used.

[Effects of the Invention] As explained above, the present invention accepts timing change requests from the voltage fluctuation drop detection circuit or temperature detection circuit provided inside or outside the chip, and changes the sense timing accordingly. It has a control circuit that enables
Even in the range where the cell level voltage cannot be sensed at normal timing due to sudden changes in external temperature or fluctuations in voltage, the cell data detection timing is delayed to ensure that the potential changes in the data line due to cell data are sufficiently detected. By causing this to occur, it is possible to realize a dynamic semiconductor memory element that can be sensed and has a wide operating margin.

In addition, especially in applications such as battery backup where the power supply is switched from the normal operating voltage to a lower voltage,
This has the effect of allowing use at a lower voltage.

Furthermore, the refresh period specified by the standard (256KD
4m5 in RAM), it is possible to eliminate elements that depend on sense timing even when refreshing or reading data (in particular, testing the retention capacity of the memory cell itself).

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram showing one embodiment, FIG. 2 is a timing diagram of one embodiment, and FIG. 3 is a layout diagram of a conventional example. DESCRIPTION OF SYMBOLS 1...Sense amplifier, 2...Sense amplifier activation timing generation circuit, 3...
...Input buffer, 7...Wait signal generation circuit. Patent Applicant: NEC Corporation Representative, Patent Attorney: Kiyoshi Kuwai −

Claims (1)

[Claims] Timing generation means for changing data level judgment timing by a sense amplifier when the accumulated charge in a dynamic memory cell is insufficient; and timing generation means for changing the judgment timing when the accumulated charge is insufficient. What is claimed is: 1. A dynamic semiconductor memory element characterized by having a means for transmitting information to the outside.