JP3190119B2 - Semiconductor storage device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device,
In particular, it relates to a DRAM having a self-refresh function. In recent years, DRAMs having a self-refresh function for automatically refreshing cells in a memory chip have been proposed. However, in a DRAM equipped with such a self-refresh function, it is not possible for the outside (a user or the like) to know up to which cell the refresh operation is currently performed, and the stored information in the DRAM may be incorrect depending on the usage. There is a need for a solution.

[0002]

2. Description of the Related Art FIG. 6 is a block diagram showing an example of a conventional general semiconductor memory device. FIG. 7 is a waveform diagram for explaining the operation of the semiconductor memory device of FIG. 6, and FIG. 7A illustrates a refresh operation in a general DRAM, and FIG. FIG. 3 illustrates a refresh operation (self-refresh operation) in a DRAM having a self-refresh function.

As shown in FIG. 6, a general semiconductor memory device includes clock generators 201 and 202, a mode controller 203, a gate circuit 204, and a write clock generator.
205, address buffer / predecoder 206, refresh address counter 207, substrate bias generator 208, row decoder 209, column decoder 210, memory cell array 21
2, a data input buffer 213 and a data output buffer 214 are provided.

As shown in FIG. 7 (a), in a conventional general DRAM, first, the / CAS signal is dropped, and the / RAS signal is sequentially changed at a constant cycle.
The user refreshes the cell. By the way, conventionally, in a system equipped with a general DRAM (for example, a personal computer or the like), if power is cut off, stored information written in cells of the DRAM is erased. The storage information is stored in another storage medium (such as a magnetic floppy disk). Therefore, in recent years, there has been proposed a DRAM in which a refresh operation (self-refresh operation) is automatically performed inside the DRAM even if the power supply of all drivers other than the DRAM is cut off. In the DRAM having the self-refresh function, there is no need to store information stored in the DRAM in another storage medium such as a magnetic floppy disk even when the power is turned off.

As shown in FIG. 7B, in a DRAM having a self-refresh function, after a / CAS signal falls and a / RAS signal falls, a predetermined time (for example, 100 μsec.) Elapses. Then, a self-refresh mode is set and the cell is automatically refreshed. Here, the judgment of CBR (CAS Before RAS) and self-refresh is made by the mode controller 203.
The internal address is supplied from the refresh address counter 207, and the cells are sequentially refreshed.

[0006]

In the conventional semiconductor memory device described above, when the power is turned on and the system is operated, it is difficult to determine which cell the user or the like is currently refreshing. Is DRAM
There was a risk that the stored information inside would be wrong. The present invention has been made in consideration of the above-described problems of the conventional semiconductor storage device, and has as its object to prevent stored information in a DRAM from being erroneous.

[0007]

According to the present invention, there is provided a semiconductor memory device having a self-refresh mode for automatically refreshing a plurality of cells, wherein refresh of all addresses in a predetermined memory area is completed. A refresh signal detection circuit 10 that outputs a predetermined signal S3 when the refresh operation has been performed, and the refresh of all the addresses is completed in response to a signal from the refresh address detection circuit 10 by an external self-refresh mode release signal / RAS. The semiconductor memory device is characterized in that the self-refresh mode is continued until the operation is completed.
According to the present invention, there is also provided a semiconductor memory device having a self-refresh mode for automatically refreshing a plurality of cells, comprising: an address terminal; an internal address line;
Address signal applied to the address terminal
A first buffer for supplying a dress line and the internal address
From the refresh address counter transmitted to the line.
A second buffer for outputting the address to the address terminal;
Wherein the first and second buffers are refreshed.
A semiconductor memory device characterized by being selectively operated in response to a reset signal . Further, according to the present invention, there is provided an internal refresh control method for a semiconductor memory device having a self-refresh mode for automatically and sequentially refreshing a plurality of cells in a predetermined memory region, wherein the self-refresh is performed in a first cycle. Executing the step, generating a change control signal for changing the execution of the self-refresh by an external control signal, receiving the change control signal, and setting the change control signal in a second cycle shorter than the first cycle. Continuously executing self-refresh until refresh of all cells in the memory area is completed.

[0008]

According to the semiconductor memory device of the present invention, when the self-refresh mode is released by the external self-refresh mode release signal / RAS, refreshing of all addresses is completed according to the signal from the refresh address detection circuit 10. Until the self-refresh mode is continued. Further, according to the semiconductor memory device of the present invention, the first buffer is applied to the address terminal.
Address signal to the internal address line, and
The buffer of No. 2 stores the refresh transmitted to the internal address line.
Address from the address counter to the address pin
Output. And the first and second buffers store
It is alternatively operable in response to a refresh signal . Furthermore, according to the internal refresh control method of the semiconductor memory device of the present invention, a change control signal for changing execution of self-refresh is received by an external control signal,
The self-refresh is continuously performed in the second cycle shorter than the first cycle until the refresh of all the cells in the memory area is completed.

As described above, according to the semiconductor memory device of the present invention, even when the refresh of all cells is not completed, the refresh is automatically completed up to the last cell.
That is, by continuing the refresh operation until the refresh of all the cells is completed, it is possible to prevent erroneous information stored in the DRAM.

[0010]

Embodiments of the present invention will be described below with reference to the accompanying drawings. FIG. 1 is a block diagram showing one embodiment of a semiconductor memory device according to the present invention. As shown in the figure, the semiconductor memory device of the present embodiment includes clock generators 1, 2, a CBR determination circuit 3, a switching circuit 4, oscillation circuits 5, 6, an output control circuit 7, a self-refresh counter 8,
It includes a self-refresh controller 9, a refresh address detection circuit 10, a refresh address counter 11, a refresh address output buffer 12, and an address input terminal 13. Here, the refresh address counter 11, the refresh address output buffer 12,
And, the address input terminal 13 has a plurality of addresses A0 to A1.
1 is provided for each. The oscillating circuit 5 generates a pulse signal having a short cycle, and the oscillating circuit 6 generates a pulse signal having a long cycle.
The self-refresh counter 8 and the self-refresh controller 9 are the same as the conventional ones, and the self-refresh mode is activated or released in accordance with the output of the output control circuit 7.

In the semiconductor memory device of the present embodiment, for example, after the / CAS signal falls by the CBR determination circuit 3, / RAS
CBR (CAS Before RAS)
Is determined. Furthermore, a self-refresh counter 8
And the self-refresh controller 9
After a determination of CBR, a predetermined time (for example, 100 μs
When the passage of c.) is detected, the self-refresh mode is entered. As a result, the external address is cut off, the internal address is supplied from the refresh address counter 11, and the cells are refreshed sequentially. Here, the refresh address detection circuit 10 detects the value of the refresh address counter 11 of each of the addresses A1 to A11, and the output control circuit 7 outputs two oscillation circuits 5 and 5 according to the output signal S3 of the refresh address detection circuit 10. 6 is performed. That is, in the self-refresh mode, when the / RAS signal rises to a high level “H” to release the self-refresh mode, and when the last cell is not refreshed, the refresh of all addresses is completed. In response to the output signal S3 of the refresh address detection circuit 10 which becomes a predetermined level (for example, low level "L"), the output control circuit 7 releases the self-refresh mode after the refresh operation of all the cells is completed. It has become. Here, the output control circuit 7 switches from the oscillation circuit 6 that generates a pulse signal with a long cycle to the oscillation circuit 5 that generates a pulse signal with a short cycle before entering the self-refresh mode and after releasing the self-refresh mode. Refreshing is performed in a short time.

As described above, the output control circuit 7 in the semiconductor memory device of the present embodiment provides the refresh address detection circuit when the / RAS signal rises to the high level "H" in the cell refresh mode to release the self refresh mode. In response to the ten output signals S3, the self-refresh mode is continued until the refresh operation of all cells is completed.

FIG. 2 is a circuit diagram showing an example of an oscillation circuit and an output control circuit in the semiconductor memory device of FIG. As shown in the figure, the oscillation circuit 5 includes a plurality of P-type MOSs.
The oscillator circuit 6 includes a transistor 511, an inverter 512, and an N-type MOS transistor 513.
An S transistor 611, an inverter 612, and an N-type MOS transistor 613 are provided. Here, each of the oscillation circuits 5 and 6
, Odd-numbered stages are respectively connected in series to a plurality of inverters 512 and 612, and the number of inverters 512 in the oscillation circuit 5 is
, The output signal S2 of the oscillation circuit 5
Is a pulse signal having a shorter cycle than the output signal S5 of the oscillation circuit 6.

The signal S1 (eg, the / RAS signal) is directly supplied to the gate of the N-type MOS transistor 513 in the oscillation circuit 5, and the inverter 41 is connected to the gate of the N-type MOS transistor 613 in the oscillation circuit 6. An inverted signal S1 is supplied via the switch. Therefore, when the signal S1 is at a low level, the oscillation circuit 6 is operated, and when the signal S1 is at a high level, the oscillation circuit 5 is operated.

The output control circuit 7 includes NAND gates 71 and 73 and an OR gate 72. The output S2 of the oscillation circuit 5 is supplied to a three-input NAND gate 71, and the output S5 of the oscillation circuit 6 is supplied to a two-input OR gate 72. NAND gate
71 and the other input of OR gate 72 have signal S4 (eg, / R
AS signal), and the output signal S3 of the refresh address detection circuit 10 is supplied to another input of the NAND gate 71.
Is supplied. Further, the output of the NAND gate 71 and the output of the OR gate 72 are supplied to the self-refresh counter 8 via the two-input NAND gate 73. That is, at the time of CBR and self-refresh, the signal S1 becomes low level “L”, the oscillation circuit 6 operates, and the signal S6 corresponding to the output S5 of the oscillation circuit 6 is supplied to the cell refresh counter 8. When the signal S1 is at a high level “H”, the oscillation circuit 5 operates.
Is high, the signal S6 corresponding to the output S2 of the oscillation circuit 5 is supplied to the cell refresh counter 8. When the signal S3 (the output signal of the refresh address detection circuit 10) is at a high level "H", the output S2 of the oscillation circuit 5 is high.
Are not transmitted as the signal S6. Note that the signals S1 and S4 are low level "L" only during CBR and self refresh, and are high level "H" in other cases.

FIG. 3 is a circuit diagram showing another example of the output control circuit in the semiconductor memory device of FIG. That is, FIG.
The output control circuit 7 shown in FIG.
The OR gate 72 and the NAND gate 73 are configured as an AND gate 71a, a NOR gate 72a, and a NOR gate 73a, respectively, and the operation is the same as that of FIG. FIG. 4 is a circuit diagram showing an example of the refresh address detection circuit in the semiconductor memory device of FIG. As shown in the figure, the refresh address detection circuit 10 has four three-input
NAND gates 101, 102, 103, 104, two NOR gates 105, 106,
And a NAND gate 107, and the NAND gates 101 to 104
Are supplied with the outputs of the refresh address counter 11 for the addresses A0 to A11, respectively. Therefore, the refresh address detection circuit 10 is provided with the NAND gate 1
Of the signals A1 to A11 (outputs of the refresh address counter 11) supplied to 01 to 104, the output signal S3 becomes high level "H" if at least one is low level "L".

FIG. 5 is a circuit diagram showing an example of a refresh address output buffer in the semiconductor memory device of FIG. The refresh address output buffer 12 is provided between the refresh address counter 11 for each of the addresses A1 to A11 and the address input terminal 13;
It comprises a transistor 121, an N-type MOS transistor 123, and inverters 122, 124, 125, 126. Here, the signal S7 is supplied to the gates of the transistors 121 and 123,
It is configured to switch between using the terminal 13 for inputting an address signal and outputting a refresh address. The signal S7 is at a high level "H" only during CBR and self refresh, and is at a low level "L" in other cases.

That is, when the signal S7 is at the low level "L", the inverter 124 is operated to transmit the address input signal supplied to the terminal 13 to the inside, and when the signal S7 is at the high level "H". In this case, the inverter 122 is operated, and a refresh address at the time of self-refresh is taken out via the terminal 13.

As described in detail above, according to the embodiment of the semiconductor memory device of the present invention, when the self-refresh mode is canceled or when the refresh is not completed up to the last cell, the period is automatically set. The short oscillation circuit 5 operates to perform the refresh operation up to the last cell. Further, by making the address input terminal 13 an I / O common, it is possible to always inform the outside of which cell is currently being refreshed.

[0020]

As described above in detail, according to the semiconductor memory device of the present invention, even when refreshing of all cells is not completed, refreshing is automatically completed up to the last cell. By continuing the refresh operation until the refresh of the cell is completed,
Alternatively, it is possible to prevent erroneous storage information in the DRAM by notifying the outside of which cell is currently refreshed.

[Brief description of the drawings]

FIG. 1 is a block diagram showing one embodiment of a semiconductor memory device according to the present invention.

FIG. 2 is a circuit diagram showing an example of an oscillation circuit and an output control circuit in the semiconductor memory device of FIG.

FIG. 3 is a circuit diagram showing another example of the output control circuit in the semiconductor memory device of FIG. 1;

FIG. 4 is a circuit diagram illustrating an example of a refresh address detection circuit in the semiconductor memory device of FIG. 1;

FIG. 5 is a circuit diagram showing an example of a refresh address output buffer in the semiconductor memory device of FIG. 1;

FIG. 6 is a block diagram showing an example of a conventional general semiconductor memory device.

FIG. 7 is a waveform chart for explaining the operation of the semiconductor memory device of FIG. 6;

[Explanation of symbols]

 1, 2, clock generator 3, CBR determination circuit 4, switching circuit 5, oscillation circuit (generating a signal with a short cycle) 6, oscillation circuit (generating a signal with a long cycle) 7, output control circuit 8, refresh counter 9 ... Self-refresh controller 10 ... Refresh address detection circuit 11 ... Refresh address counter 12 ... Refresh address output buffer 13 ... Address terminal

────────────────────────────────────────────────── ─── Continuation of the front page (56) References JP-A-2-3150 (JP, A) JP-A-2-105389 (JP, A) (58) Fields investigated (Int. Cl. ⁷ , DB name) G11C 11/40-11/41

Claims (6)

(57) [Claims] 1. A semiconductor memory device having a self-refresh mode for automatically refreshing a plurality of cells, wherein the refresh device outputs a predetermined signal when all addresses in a predetermined memory area have been refreshed. A semiconductor memory comprising an address detection circuit, wherein a self-refresh mode is continued until refresh of all the addresses is completed in response to a signal from the refresh address detection circuit in response to an external self-refresh mode release signal. apparatus. 2. The semiconductor memory device according to claim 1, wherein after the external self-refresh mode release signal is input, the first time from when the external refresh signal is input.
A semiconductor memory device wherein refresh is continued in a second refresh cycle shorter than the refresh cycle. 3. The semiconductor memory device according to claim 2, further comprising: said first refresh cycle and said second refresh cycle.
A semiconductor memory device comprising: an output control circuit that controls a refresh cycle by the external self-refresh mode release signal. 4. The semiconductor memory device according to claim 2, further comprising: said first refresh cycle and said second refresh cycle.
A semiconductor memory device comprising: an output control circuit that controls a refresh cycle according to a signal from the refresh address detection circuit. 5. A semiconductor memory device having a self-refresh mode for automatically refreshing a plurality of cells , comprising: an address terminal , an internal address line, and an address signal applied to the address terminal.
A first buffer to be supplied to the address line, and a refresh address buffer transmitted to the internal address line.
Output the address from the address counter to the address terminal.
And the first and second buffers.
Can be operated alternatively in response to a refresh signal.
The semiconductor memory device which is characterized in that. 6. A method for controlling internal refresh of a semiconductor memory device having a self-refresh mode for automatically and sequentially refreshing a plurality of cells in a predetermined memory area, wherein the self-refresh is performed in a first cycle. Generating a change control signal for changing execution of self-refresh in response to an external control signal; and receiving the change control signal to generate a change control signal for the memory area in a second cycle shorter than the first cycle. Continuously executing the self-refresh until the refresh of all the cells is completed.