JPH059873B2 - - Google Patents

Info

Publication number
JPH059873B2
JPH059873B2 JP61253016A JP25301686A JPH059873B2 JP H059873 B2 JPH059873 B2 JP H059873B2 JP 61253016 A JP61253016 A JP 61253016A JP 25301686 A JP25301686 A JP 25301686A JP H059873 B2 JPH059873 B2 JP H059873B2
Authority
JP
Japan
Prior art keywords
data
fifo
circuit
stage
input
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
JP61253016A
Other languages
English (en)
Japanese (ja)
Other versions
JPS63106987A (ja
Inventor
Shinichi Hirano
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nippon Electric Co Ltd filed Critical Nippon Electric Co Ltd
Priority to JP61253016A priority Critical patent/JPS63106987A/ja
Publication of JPS63106987A publication Critical patent/JPS63106987A/ja
Publication of JPH059873B2 publication Critical patent/JPH059873B2/ja
Granted legal-status Critical Current

Links

Landscapes

  • Logic Circuits (AREA)
  • Information Transfer Systems (AREA)
JP61253016A 1986-10-23 1986-10-23 Ｆｉｆｏ回路のデ−タ空領域検出回路 Granted JPS63106987A (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP61253016A JPS63106987A (ja) 1986-10-23 1986-10-23 Ｆｉｆｏ回路のデ−タ空領域検出回路

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP61253016A JPS63106987A (ja) 1986-10-23 1986-10-23 Ｆｉｆｏ回路のデ−タ空領域検出回路

Publications (2)

Publication Number Publication Date
JPS63106987A JPS63106987A (ja) 1988-05-12
JPH059873B2 true JPH059873B2 (cs) 1993-02-08

Family

ID=17245312

Family Applications (1)

Application Number Title Priority Date Filing Date
JP61253016A Granted JPS63106987A (ja) 1986-10-23 1986-10-23 Ｆｉｆｏ回路のデ−タ空領域検出回路

Country Status (1)

Country Link
JP (1) JPS63106987A (cs)

Also Published As

Publication number Publication date
JPS63106987A (ja) 1988-05-12

Similar Documents

Publication Publication Date Title
US4845675A (en) High-speed data latch with zero data hold time
US3971960A (en) Flip-flop false output rejection circuit
US5459421A (en) Dynamic-static master slave flip-flop circuit
EP0219846B1 (en) Latch circuit tolerant of undefined control signals
US4420695A (en) Synchronous priority circuit
US4387294A (en) Shift register-latch circuit driven by clocks with half cycle phase deviation and usable with a serial alu
GB2121254A (en) Data bus precharging circuits
US4045684A (en) Information transfer bus circuit with signal loss compensation
US4020362A (en) Counter using an inverter and shift registers
US3969717A (en) Digital circuit to eliminate display flicker
JPH059873B2 (cs)
US4259595A (en) Clocking system for MOS transistor logic circuit
US4459683A (en) Read resettable memory circuit
JP3016985B2 (ja) 半導体記憶装置
US4947059A (en) Method of dividing an input-output line by decoding
JPH058516B2 (cs)
JPS63122314A (ja) 出力バツフア回路
JP2782946B2 (ja) 半導体集積回路
US5675774A (en) Circuit element on a single ended interconnection for generating a logical output finish/clock signal when detecting a state change to logical "1 or 0".
JPS63119318A (ja) 位相比較器
JPH05100778A (ja) 半導体出力回路
JPS614979A (ja) 半導体集積回路装置
KR970003139Y1 (ko) 저전압동작의 롬구조
JPS63263943A (ja) デ−タバス回路
JPS61264817A (ja) クロツク信号発生回路