JPH059827B2 - - Google Patents

Info

Publication number
JPH059827B2
JPH059827B2 JP58160703A JP16070383A JPH059827B2 JP H059827 B2 JPH059827 B2 JP H059827B2 JP 58160703 A JP58160703 A JP 58160703A JP 16070383 A JP16070383 A JP 16070383A JP H059827 B2 JPH059827 B2 JP H059827B2
Authority
JP
Japan
Prior art keywords
ruled line
ruled
line data
lines
bit information
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
JP58160703A
Other languages
Japanese (ja)
Other versions
JPS6051976A (en
Inventor
Yasuo Koyama
Mitsuaki Shimodaira
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Seiko Epson Corp
Original Assignee
Seiko Epson Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Seiko Epson Corp filed Critical Seiko Epson Corp
Priority to JP58160703A priority Critical patent/JPS6051976A/en
Publication of JPS6051976A publication Critical patent/JPS6051976A/en
Publication of JPH059827B2 publication Critical patent/JPH059827B2/ja
Granted legal-status Critical Current

Links

Classifications

    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F40/00Handling natural language data
    • G06F40/10Text processing
    • G06F40/12Use of codes for handling textual entities

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Audiology, Speech & Language Pathology (AREA)
  • Health & Medical Sciences (AREA)
  • Computational Linguistics (AREA)
  • General Health & Medical Sciences (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Artificial Intelligence (AREA)
  • Input From Keyboards Or The Like (AREA)
  • Processing Or Creating Images (AREA)
  • Image Generation (AREA)
  • Document Processing Apparatus (AREA)

Description

【発明の詳細な説明】 (技術分野) 本発明は、ワードプロセツサに適した罫線作成
装置に関する。
DETAILED DESCRIPTION OF THE INVENTION (Technical Field) The present invention relates to a ruled line creation device suitable for a word processor.

(従来技術) 作表作業には太線、細線を使分けた罫線引きを
必要とするが、端部や交差部では、第1図aに示
したように罫線の太さと方向の組合せによる色々
のパターンイ乃至タが発生し、これら全てのパタ
ーンに対応するには、容量の大きい辞書メモリを
必要とするため、通常ワードプロセツサでは、線
径の異なる罫線が交差する箇所ロ,ホ,ト,チ,
ヌ,カでは、同図bに示したようにいづれか一方
の線径に揃えて表示、印刷することが行なわれて
おり、できあがつた表罫が不揃いで見ぐるしいと
いう不都合があつた。
(Prior art) Tabulation work requires drawing lines using thick and thin lines, but at edges and intersections, various combinations of the thickness and direction of the ruled lines can be drawn, as shown in Figure 1a. Patterns are generated, and a dictionary memory with a large capacity is required to accommodate all of these patterns. blood,
As shown in FIG. 2B, the wire diameters are displayed and printed according to one of the wire diameters, which has the disadvantage that the resulting table lines are irregular and look messy.

(目的) 本発明はこのような問題に鑑み、罫線が交差す
る箇所でのパターンを逐次合成しながら美しい表
罫を作成することができる新規な罫線作成装置を
提供することを目的とする。
(Objective) In view of such problems, an object of the present invention is to provide a novel ruled line creation device that can create beautiful front ruled lines while sequentially synthesizing patterns at locations where ruled lines intersect.

(構成) そこで、以下に本発明の詳細を図示した実施例
に基づいて説明する。
(Structure) Therefore, details of the present invention will be described below based on illustrated embodiments.

第2図は、本発明の罫線合成装置が適用された
ワードプロセツサを示す装置のブロツク図であつ
て、図中符号1は、キイボード2により入力され
たデータに基づいてシステム全体の制御を行なう
中央処理装置で、キイボードからの読みデータ入
力によりカナ漢字変換や記号等が格納された辞書
メモリ3にアクセスをかけ、所定の漢字や記号の
パターンをビデオラム4(ビデオメモリの一例)
に出力し、CRT5やプリンタ6により表示、印
刷するように構成されている。7は、本発明の特
徴部分をなす罫線作成装置であつて、図中符号8
は、パターン認識部で、先に入力された罫線デー
タ(以下、旧罫線と呼ぶ)と今回入力された罫線
データ(以下、新罫線と呼ぶ)が同一キヤラクタ
単位に格納される場合、つまり罫線が交絡する場
合にこれを検出するとともに、旧罫線に重ねられ
る新罫線との線径が同じであるか否かを判断し、
同一線径の場合に辞書メモリ3にアクセスして所
定のパターンを呼出し、これを旧罫線が納められ
ているビデオラムのアドレスに格納する。一方
新、旧罫線の線径が異なる場合には旧罫線のパタ
ーンをビデオラム4から読出し、罫線のパターン
を第3図aに示したように矢印方向に順番に線径
データ(表1)により、 表1 空白 細径 太径 00 01 10 同図bの横方向の細径では00,01,00,01に、
cの縦方向の太径では10,00,10,00、さらに同
図d及びeの半線では10,00,00,00及び00,
00,00,01というようなビツト情報に変換して出
力するように構成されている。9は、罫線合成装
置で、パターン認識部8により変換されたビデオ
ラム4からの旧罫線のビツト情報と、キイボード
2からの新罫線のビツト情報を加算したビツト情
報を生成するように構成されている。10は、変
換テーブルで、罫線合成制御装置9からのビツト
情報を基にし、これに対応した罫線パターンを発
生するように構成されている。11は、罫線合成
制御装置の演算過程におけるデータを一時保存す
る一時記憶装置である。
FIG. 2 is a block diagram of a word processor to which the ruled line synthesis device of the present invention is applied, and the reference numeral 1 in the figure controls the entire system based on data input from the keyboard 2. The central processing unit accesses the dictionary memory 3 in which kana-kanji conversions, symbols, etc. are stored by inputting reading data from the keyboard, and converts predetermined kanji and symbol patterns into the video RAM 4 (an example of video memory).
It is configured to output the data to a CRT 5 or printer 6 for display and printing. 7 is a ruled line creation device which is a characteristic part of the present invention, and is designated by the reference numeral 8 in the figure.
In the pattern recognition section, if the previously input ruled line data (hereinafter referred to as old ruled line) and the newly inputted ruled line data (hereinafter referred to as new ruled line) are stored in the same character unit, that is, the ruled line is In the case of interlacing, this is detected, and it is determined whether the wire diameter of the new ruled line superimposed on the old ruled line is the same.
If the wire diameters are the same, the dictionary memory 3 is accessed, a predetermined pattern is called up, and this is stored at the address of the video ram where the old ruled line is stored. On the other hand, if the wire diameters of the new and old ruled lines are different, the old ruled line pattern is read out from the video ram 4, and the ruled line pattern is sequentially changed according to the wire diameter data (Table 1) in the direction of the arrows as shown in Figure 3a. , Table 1 Blank Thin diameter Thick diameter 00 01 10 The narrow diameter in the horizontal direction shown in b in the same figure is 00, 01, 00, 01.
The large diameter in the longitudinal direction of c is 10,00, 10,00, and the half line of d and e in the same figure is 10,00,00,00 and 00,
It is configured to convert and output bit information such as 00, 00, 01. Reference numeral 9 denotes a ruled line synthesis device configured to generate bit information by adding the bit information of the old ruled line from the video ram 4 converted by the pattern recognition unit 8 and the bit information of the new ruled line from the keyboard 2. There is. Reference numeral 10 denotes a conversion table, which is configured to generate a corresponding ruled line pattern based on bit information from the ruled line synthesis control device 9. Reference numeral 11 denotes a temporary storage device that temporarily stores data in the calculation process of the ruled line composition control device.

次にこのように構成した装置の動作を第4図に
示したフローチヤートに基づいて説明する。
Next, the operation of the apparatus configured as described above will be explained based on the flowchart shown in FIG.

作表を行なうべくキイボード2から罫線データ
を入力すると、中央処理装置1を介してビデオラ
ム4に格納されてデイスプレイ5に表示される。
このようにして同一方向、例えば横方向の太径の
罫線を次々に引いてゆくと(第5図a)、相互に
交差することがないので、そのままビデオラム4
に格納されていく。次に、方向が異なる縦方向
の細径の罫線を引くと(第5図b)、太径の旧罫
線と交差する(第5図c)。パターン認識部8は、
この異なる線径の交差zを検出し、同一キヤラ
クタ単位内に存在する旧罫線データをビデオラム
4から呼出し、ビツト情報(00,10,00,10)
に変換して罫線合成装置9を介して一時記憶装
置11に出力する。一方交差が生じる新罫線
は、パターン認識部8によりビツト情報(01,
00,00,00)を罫線合成装置9に入力し、一時
記憶装置11に格納されている旧罫線のビツト情
報と合成{(00,10,00,10)+(01,00,00,
00)}され、両罫線を合成した新しい罫線パター
ンのビツト情報(01,10,00,10)を作成する
。このビツト情報は、変換テーブル10に入力
してこれにより表される罫線パターン(第5図
e)に変換されてた後、旧罫線を呼出したビデ
オラム4のアドレスに入力する。これによりビ
デオラム4には各方向の線径が統一された罫線が
格納され、CRT5及びプリンタ6により各方向
に統一が取れた表罫が表示、印刷される。いうま
でもなく、同一径の罫線が交絡する場合には、辞
書メモリ3に格納されている罫線パターンを呼出
し、これをビデオラム4の旧罫線が格納されて
いるアドレスに出力し、表示、印刷する。
When ruled line data is input from the keyboard 2 for tabulation, it is stored in the video ram 4 via the central processing unit 1 and displayed on the display 5.
In this way, if you draw thick ruled lines one after another in the same direction, for example the horizontal direction (Fig. 5a), they will not intersect with each other, so the video ram 4
will be stored in. Next, when a thin vertical ruled line is drawn in a different direction (FIG. 5b), it intersects with the old thick ruled line (FIG. 5c). The pattern recognition unit 8 is
The intersection z of these different wire diameters is detected, the old ruled line data existing in the same character unit is called from the video ram 4, and the bit information (00, 10, 00, 10) is
, and output it to the temporary storage device 11 via the ruled line synthesis device 9. On the other hand, new ruled lines that intersect are identified by the pattern recognition unit 8 as bit information (01,
00, 00, 00) is input to the ruled line synthesis device 9 and synthesized with the bit information of the old ruled line stored in the temporary storage device 11 {(00, 10, 00, 10) + (01, 00, 00,
00)} and create bit information (01, 10, 00, 10) of a new ruled line pattern by combining both ruled lines. This bit information is input into the conversion table 10 and converted into the ruled line pattern (FIG. 5e) represented by the conversion table 10, and then inputted into the address of the video ram 4 from which the old ruled line was called. As a result, ruled lines with uniform wire diameters in each direction are stored in the video ram 4, and front ruled lines with uniform diameters in each direction are displayed and printed by the CRT 5 and printer 6. Needless to say, if ruled lines of the same diameter are intertwined, the ruled line pattern stored in the dictionary memory 3 is called up, and this is output to the address where the old ruled line is stored in the video ram 4, and displayed and printed. do.

なお、この実施例では、線径の異なる2本の罫
線が直交する場合を例に採つて説明したが、言う
までもなく同一線径の罫線が交差する場合や、斜
めに交差する場合についても同様に合成できるこ
とは明らかである。
In this example, the case where two ruled lines with different wire diameters intersect at right angles is taken as an example, but needless to say, the same applies to cases where ruled lines with the same wire diameter intersect or diagonally intersect. It is clear that it can be synthesized.

(効果) 以上、説明したように本発明によれば、複数の
罫線が交絡するキヤラクタエリアでの各罫線のパ
ターンをビツト情報に変換してこれらの罫線によ
り形成されるパターンを演算するようにしたの
で、辞書メモリの容量を小さくすることができる
ばかりでなく、交差部処理の見苦しさをなくし、
木目の細かい作表が可能となる。
(Effects) As explained above, according to the present invention, the pattern of each ruled line in a character area where a plurality of ruled lines are intertwined is converted into bit information, and the pattern formed by these ruled lines is calculated. Therefore, not only can the capacity of the dictionary memory be reduced, but also the unsightliness of intersection processing can be eliminated.
It is possible to create tabulations with fine grains.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図a,bは、それぞれ作表作業により生じ
る罫線のパターン、及び従来の処理状態を示す説
明図、第2図は、本発明の装置の一実施例を示す
装置のブロツク図、第3図は、同上装置のパター
ン認識部の動作を示す説明図、第4図は、同上装
置の動作を示すフローチヤート、第5図は、同上
装置の作表過程を示す説明図である。 7……罫線作成装置。
FIGS. 1a and 1b are explanatory diagrams showing a ruled line pattern generated by tabulation work and a conventional processing state, respectively; FIG. 2 is a block diagram of an apparatus showing an embodiment of the apparatus of the present invention; and FIG. FIG. 4 is an explanatory diagram showing the operation of the pattern recognition section of the above device, FIG. 4 is a flowchart showing the operation of the same device, and FIG. 5 is an explanatory diagram showing the tabulation process of the same device. 7... Ruled line creation device.

Claims (1)

【特許請求の範囲】 1 複数の線径の罫線を使用する罫線作成装置に
おいて、 入力された罫線データを格納するビデオメモリ
と、 引続いて入力されるデータが罫線データで、か
つ前回入力された罫線データと同一キヤラクタ単
位に存在する場合に前記2つの罫線の線径が異な
るか否かを判断し、線径が異なる場合に前記ビデ
オメモリからこのキヤラクタ単位の前回入力され
た前記罫線データを呼出してビツト情報に変換す
るとともに今回入力された罫線データをビツト情
報に変換する手段と、 前記手段からの前記2つのビツト情報を合成
し、これに基づいて罫線パターンを作成して前記
ビデオメモリの所定のアドレスに再入力する手段
とからなる罫線作成装置。
[Claims] 1. A ruled line creation device that uses ruled lines of a plurality of wire diameters, comprising: a video memory that stores input ruled line data; and a video memory that stores input ruled line data; If the two ruled lines exist in the same character unit as the ruled line data, it is determined whether the wire diameters of the two ruled lines are different, and if the wire diameters are different, the previously inputted ruled line data in this character unit is called from the video memory. a means for converting the currently input ruled line data into bit information; and a means for synthesizing the two bit information from the means, creating a ruled line pattern based on this, and storing the ruled line data in a predetermined location in the video memory. and a means for re-entering the address of the ruled line.
JP58160703A 1983-08-31 1983-08-31 Method and apparatus for preparing ruled line Granted JPS6051976A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP58160703A JPS6051976A (en) 1983-08-31 1983-08-31 Method and apparatus for preparing ruled line

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP58160703A JPS6051976A (en) 1983-08-31 1983-08-31 Method and apparatus for preparing ruled line

Related Child Applications (1)

Application Number Title Priority Date Filing Date
JP4124886A Division JPH05181848A (en) 1992-05-18 1992-05-18 Ruled line generating method

Publications (2)

Publication Number Publication Date
JPS6051976A JPS6051976A (en) 1985-03-23
JPH059827B2 true JPH059827B2 (en) 1993-02-08

Family

ID=15720640

Family Applications (1)

Application Number Title Priority Date Filing Date
JP58160703A Granted JPS6051976A (en) 1983-08-31 1983-08-31 Method and apparatus for preparing ruled line

Country Status (1)

Country Link
JP (1) JPS6051976A (en)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0695276B2 (en) * 1986-06-16 1994-11-24 横河電機株式会社 How to display ruled line types
JPS636657A (en) * 1986-06-27 1988-01-12 Casio Comput Co Ltd Ruled line producing device

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5814249A (en) * 1981-07-20 1983-01-27 Fujitsu Ltd Display control system for ruled line

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5814249A (en) * 1981-07-20 1983-01-27 Fujitsu Ltd Display control system for ruled line

Also Published As

Publication number Publication date
JPS6051976A (en) 1985-03-23

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