JPH05181848A - Ruled line generating method - Google Patents

Ruled line generating method

Info

Publication number
JPH05181848A
JPH05181848A JP4124886A JP12488692A JPH05181848A JP H05181848 A JPH05181848 A JP H05181848A JP 4124886 A JP4124886 A JP 4124886A JP 12488692 A JP12488692 A JP 12488692A JP H05181848 A JPH05181848 A JP H05181848A
Authority
JP
Japan
Prior art keywords
ruled line
bit information
ruled
line data
lines
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP4124886A
Other languages
Japanese (ja)
Inventor
Yasuo Koyama
泰男 小山
Mitsuaki Shimodaira
光明 下平
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Seiko Epson Corp
Original Assignee
Seiko Epson Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Seiko Epson Corp filed Critical Seiko Epson Corp
Priority to JP4124886A priority Critical patent/JPH05181848A/en
Publication of JPH05181848A publication Critical patent/JPH05181848A/en
Pending legal-status Critical Current

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  • Processing Or Creating Images (AREA)
  • Document Processing Apparatus (AREA)

Abstract

PURPOSE:To execute an elaborate tabulation by converting a pattern of each ruled line in a character area in which plural rules lines are confounded to bit information, and calculating the pattern formed by these ruled lines. CONSTITUTION:Inputted ruled line data is stored in a prescribed address of a video memory, and in the case data inputted continuously is ruled line data, and also, exists in the same character unit as ruled line data inputted in the previous time, whether the line diameters of two ruled lines are different or not is decided. As a result, in the case the line diameters are different, the ruled line data inputted in the previous time of this character unit is called from the video memory and converted to bit information, and also, ruled line data inputted this time is converted to bit information. Subsequently, two bit information is synthesized, and based on this bit information, a ruled line pattern is generated, and reinputted to the address which executes a call of the video memory. In such a way, the capacity of a dictionary memory can be made small, and an elaborate tabulation can be executed.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【産業上の利用分野】本発明は、特にワードプロセッサ
に適した罫線作成方法に関する。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a ruled line forming method particularly suitable for a word processor.

【0002】[0002]

【従来の技術】作表作業には太線、細線を使分けた罫線
引きを必要とするが、端部や交差部では、図1(a)に
示したように罫線の太さと方向の組合せによる色々のパ
ターン(イ)乃至(タ)が発生し、これら全てのパター
ンに対応するには、容量の大きい辞書メモリを必要とす
るため、通常ワードプロセッサでは、線経の異なる罫線
が交差する箇所(ロ)(ホ)(ト)(チ)(ヌ)(カ)
では、同図(b)に示したようにいずれか一方の線経に
揃えて表示、印刷することが行なわれており、できあが
った表罫が不揃いで見苦しいという不都合があった。
2. Description of the Related Art A table drawing operation requires ruled line drawing using thick lines and thin lines, but at the ends and intersections, as shown in FIG. 1A, the combination of ruled line thickness and direction is used. Various patterns (a) to (t) occur, and a large-capacity dictionary memory is required to support all of these patterns. Therefore, in a normal word processor, a part (rule) where ruled lines with different lengths cross each other is required. ) (Ho) (to) (chi) (nu) (mosquito)
However, as shown in FIG. 3B, the lines are displayed and printed on one of the lines, and the resulting ruled lines are not uniform and unsightly.

【0003】なお、罫線作成に関連して特開昭56−2
079号公報、特開昭58−27229号公報に開示さ
れた発明があるが、本願発明は目的、構成、効果等から
これらの発明と異なるものである。
Incidentally, in relation to the creation of ruled lines, Japanese Patent Laid-Open No. 56-2
Although there are inventions disclosed in Japanese Patent Application Laid-Open No. 079 and Japanese Patent Application Laid-Open No. 58-27229, the present invention is different from these inventions in view of the object, constitution, effect and the like.

【0004】[0004]

【発明が解決しようとする課題】本発明はこのような問
題に鑑み、罫線が交差する箇所でのパターンを逐次合成
しながら作表することができる新規な罫線作成方法を提
案することを目標とする。
In view of the above problems, the present invention aims at proposing a new ruled line creating method capable of tabulating while sequentially synthesizing patterns at locations where ruled lines intersect. To do.

【0005】[0005]

【課題を解決するための手段】本発明の罫線作成方法
は、入力された罫線データをビデオメモリの所定アドレ
スに格納する工程、引続いて入力されるデータが罫線デ
ータで、かつ前回入力された罫線データと同一キャラク
タ単位に存在する場合に前記2つの罫線の線経が異なる
か否かを判断する工程と、線経が異なる場合には前記ビ
デオメモリからこのキャラクタ単位の前回入力された罫
線データを呼出してビット情報に変換するとともに今回
入力された罫線データをビット情報に変換する工程、前
記2つのビット情報を合成する工程、該ビット情報に基
づいて罫線パターンを作成して前記ビデオメモリの呼出
しをかけたアドレスに再入力する工程を備えたものであ
る。
According to the ruled line forming method of the present invention, the step of storing the inputted ruled line data in a predetermined address of the video memory, the data which is subsequently inputted is the ruled line data and is inputted last time. If the ruled line data and the ruled line data exist in the same character unit, the step of determining whether or not the two ruled lines have different line lengths, and if the line values are different, the previously input ruled line data in character units from the video memory. To convert the ruled line data input this time into bit information, combine the two bit information, create a ruled line pattern based on the bit information, and call the video memory. It is provided with a step of re-inputting the address to which the call is applied.

【0006】[0006]

【作用】このようにすると辞書メモリの容量を小さくす
ることができる、種々の罫線パターンに対応することが
でき、木目の細かい作表が可能となる等の作用を有す
る。
In this way, the capacity of the dictionary memory can be reduced, various ruled line patterns can be dealt with, and fine tabulation can be performed.

【0007】[0007]

【実施例】そこで、以下に本発明の詳細を図示した実施
例に基づいて説明する。
Embodiments of the present invention will be described below in detail with reference to the illustrated embodiments.

【0008】図2は、本発明の罫線合成装置が適用され
たワードプロセッサを示す装置のブロック図であって、
図中符号1は、キーボード2により入力されたデータに
基づいてシステム全体の制御を行なう中央処理装置で、
キーボードからの読みデータ入力によりカナ漢字変換や
記号等が格納された辞書メモリ3にアクセスをかけ、所
定の漢字や記号のパターンをビデオラム4(ビデオメモ
リの一例)に出力し、CRT5やプリンタ6により表
示、印刷するように構成されている。7は、本発明の特
徴部分をなす罫線作成装置であって、図中符号8は、パ
ターン認識部で、先に入力された罫線データ(以下、旧
罫線と呼ぶ)と今回入力された罫線データ(以下、新罫
線と呼ぶ)が同一キャラクタ単位に格納される場合、つ
まり罫線が交絡する場合にこれを検出するとともに、旧
罫線に重ねられる新罫線との線径が同じであるか否かを
判定し、同一線径の場合に辞書メモリ3にアクセスして
所定のパターンを呼出し、これを旧罫線が納められてい
るビデオラムのアドレスに格納する。一方新、旧罫線の
線径が異なる場合には旧罫線のパターンをビデオラム4
から読出し、罫線のパターンを図3(a)に示したよう
に矢印方向に順番に線径データ表1により、
FIG. 2 is a block diagram of an apparatus showing a word processor to which the ruled line synthesis apparatus of the present invention is applied.
Reference numeral 1 in the figure is a central processing unit that controls the entire system based on the data input by the keyboard 2.
By inputting the reading data from the keyboard, the dictionary memory 3 in which kana-kanji conversion or symbols are stored is accessed, and a predetermined kanji or symbol pattern is output to the video RAM 4 (an example of video memory), and the CRT 5 or printer 6 is used. Are configured to be displayed and printed. Reference numeral 7 denotes a ruled line creating apparatus which is a characteristic part of the present invention, and reference numeral 8 in the drawing denotes a pattern recognition unit, which is the previously input ruled line data (hereinafter referred to as old ruled line) and the currently input ruled line data. When the new ruled line (hereinafter referred to as a new ruled line) is stored in the same character unit, that is, when the ruled line is entangled, this is detected, and whether the diameter of the new ruled line to be overlapped with the old ruled line is the same or not is detected. If it is determined that the line diameter is the same, the dictionary memory 3 is accessed to call a predetermined pattern, and this is stored in the address of the video RAM in which the old ruled line is stored. If the new and old ruled lines have different diameters, the old ruled line pattern is
The pattern of the ruled line is read in order from the wire diameter data table 1 in the direction of the arrow as shown in FIG.

【0009】[0009]

【表1】 空白 細径 太径 00 01 10 同図(b)の横方向の細径では00、01、00、01
に、(c)の縦方向の太径では10、00、10、0
0、さらに同図(d)及び(e)の半線では10、0
0、00、00及び00、00、00、01というよう
なビット情報に変換して出力するように構成されてい
る。9は、罫線合成装置で、パターン認識部8により変
換されたビデオラム4からの旧罫線のビット情報と、キ
ーボート2からの新罫線のビット情報を加算したビット
情報を生成するように構成されている。10は、変換テ
ーブルで、罫線合成制御装置9からのビット情報を基に
し、これに対応した罫線パターンを発生するように構成
されている。11は、罫線合成制御装置の演算過程にお
けるデータを一時保存する一時記憶装置である。
[Table 1] Blank Small diameter Large diameter 00 01 10 For small diameter in the horizontal direction in the same figure (b), 00, 01, 00, 01
In addition, (c) has a large vertical diameter of 10,00,10,0.
0, and in the half-lines of FIGS.
It is configured to be converted into bit information such as 0, 00, 00 and 00, 00, 00, 01 and output. A ruled line synthesizer 9 is configured to generate bit information obtained by adding the bit information of the old ruled line from the video ram 4 converted by the pattern recognition unit 8 and the bit information of the new ruled line from the keyboard 2. There is. A conversion table 10 is configured to generate a ruled line pattern corresponding to this based on the bit information from the ruled line synthesis control device 9. Reference numeral 11 denotes a temporary storage device for temporarily storing data in the calculation process of the ruled line synthesis control device.

【0010】次にこのように構成した装置の動作を図4
に示したフロチャートに基づいて説明する。
Next, the operation of the apparatus configured as described above will be described with reference to FIG.
It will be described based on the flowchart shown in FIG.

【0011】作表を行なうべくキーボード2から罫線デ
ータを入力すると、中央処理装置1を介してビデオラム
4に格納されてディスプレイ5に表示される。このよう
にして同一方向、例えば横方向の太径の罫線を次々に引
いてゆくと(図5a)、相互に交差することがないの
で、そのままビデオラム4に格納されていく(1)。次
に、方向が異なる縦方向の細径の罫線を引くと(図5
b)、太径の旧罫線と交差する(図5c)。パターン認
識部8は、この異なる線径の交差zを検出し(2)、同
一キャラクタ単位内に存在する旧罫線データをビデオラ
ム4から呼出し(3)、ビット情報(00、10、0
0、10)に変換して(4)、罫線合成装置9を介して
一時記憶装置11に出力する(5)。一方交差が生じる
新罫線は、パターン認識部8によりビット情報(01、
00、00、00)を罫線合成装置9に入力し(6)、
一時記憶装置11に格納されている旧罫線のビット情報
と加算{(00、10、00、10)+(01、00、
00、00)}され、両罫線を合成した新しい罫線パタ
ーンのビット情報(01、10、00、10)を作成す
る(7)。このビット情報は、変換テーブル10に入力
してこれにより表される罫線パターン(図5e)に変換
された後(8)、旧罫線を呼出したビデオラム4のアド
レスに入力する(9)。これによりビデオラム4には各
方向の線径が統一された罫線が格納され、CRT5及び
プリンタ6により各方向に統一が取れた表罫が表示、印
刷される。いうまでもなく、同一径の罫線が交絡する場
合には、辞書メモリ3に格納されている罫線パターンを
呼出し(10)、これをビデオラム4の旧罫線が格納さ
れているアドレスに出力し(9)、表示、印刷する。
When the ruled line data is input from the keyboard 2 to make a table, it is stored in the video RAM 4 via the central processing unit 1 and displayed on the display 5. In this way, when the ruled lines having a large diameter in the same direction, for example, the horizontal direction are drawn one after another (FIG. 5a), they do not intersect each other, and thus they are stored in the video ram 4 as they are (1). Next, if you draw a ruled line with a small diameter in the vertical direction,
b), intersects the old ruled line of large diameter (Fig. 5c). The pattern recognition unit 8 detects the intersection z of the different wire diameters (2), calls the old ruled line data existing in the same character unit from the video RAM 4 (3), and bit information (00, 10, 0).
It is converted into 0, 10) (4) and output to the temporary storage device 11 via the ruled line composition device 9 (5). On the other hand, for the new ruled line where the intersection occurs, bit information (01,
(00, 00, 00) to the ruled line synthesizer 9 (6),
Bit information of the old ruled line stored in the temporary storage device 11 and addition {(00, 10, 00, 10) + (01, 00,
00, 00)}, and bit information (01, 10, 00, 10) of a new ruled line pattern in which both ruled lines are combined is created (7). This bit information is input to the conversion table 10 and converted into the ruled line pattern (FIG. 5e) represented by this (8), and then input to the address of the video ram 4 that called the old ruled line (9). As a result, the ruled lines whose wire diameters in each direction are unified are stored in the video ram 4, and the CRT 5 and the printer 6 display and print the unified ruled lines in each direction. Needless to say, when the ruled lines having the same diameter are entangled, the ruled line pattern stored in the dictionary memory 3 is called (10) and is output to the address where the old ruled line of the video ram 4 is stored ( 9) Display and print.

【0012】なお、この実施例では、線径の異なる2本
の罫線が直交する場合を例に採って説明したが、言うま
でもなく同一線径の罫線が交差する場合や、斜めに交差
する場合についても同様に合成できることは明らかであ
る。
In this embodiment, the case where two ruled lines having different wire diameters are orthogonal to each other has been described as an example. Needless to say, however, there is a case where ruled lines having the same wire diameter intersect or diagonally intersect. It is clear that can be similarly synthesized.

【0013】[0013]

【発明の効果】以上、説明したように本発明によれば、
複数の罫線が交絡するキャラクタエリアでの各罫線のパ
ターンをビット情報に変換してこれらの罫線により形成
されるパターンを演算するようにしたので、辞書メモリ
の容量を小さくすることができるばかりでなく、交差部
処理の見苦しさをなくし、木目の細かい作表が可能とな
る。
As described above, according to the present invention,
Since the pattern of each ruled line in the character area where a plurality of ruled lines are entangled is converted into bit information and the pattern formed by these ruled lines is calculated, not only can the capacity of the dictionary memory be reduced. , It is possible to eliminate the unsightly appearance of the intersection processing and create a fine grained table.

【図面の簡単な説明】[Brief description of drawings]

【図1】 (a)(b)はそれぞれ作表作業により生じ
る罫線パターン、及び従来の処理状態を示す説明図。
FIG. 1A and FIG. 1B are explanatory views showing a ruled line pattern generated by a tabulation work and a conventional processing state, respectively.

【図2】 本発明の装置の一実施例を示す装置のブロッ
ク図。
FIG. 2 is a block diagram of an apparatus showing an embodiment of the apparatus of the present invention.

【図3】 本発明の装置のパターン認識部の動作を示す
説明図。
FIG. 3 is an explanatory diagram showing an operation of a pattern recognition unit of the device of the present invention.

【図4】 本発明の装置の動作を示すフロチャート。FIG. 4 is a flowchart showing the operation of the device of the present invention.

【図5】 本発明の装置の作表過程を示す説明図。FIG. 5 is an explanatory view showing a tabulation process of the device of the present invention.

【符号の説明】[Explanation of symbols]

7・・・罫線作成装置 7: Ruled line creation device

Claims (1)

【特許請求の範囲】[Claims] 【請求項1】 入力された罫線データをビデオメモリの
所定アドレスに格納する工程、引続いて入力されるデー
タが罫線データで、かつ前回入力された罫線データと同
一キャラクタ単位に存在する場合に前記2つの罫線の線
経が異なるか否かを判断する工程と、線経が異なる場合
には前記ビデオメモリからこのキャラクタ単位の前回入
力された罫線データを呼出してビット情報に変換すると
ともに今回入力された罫線データをビット情報に変換す
る工程、前記2つのビット情報を合成する工程、該ビッ
ト情報に基づいて罫線パターンを作成して前記ビデオメ
モリの呼出しをかけたアドレスに再入力する工程とから
なることを特徴とする罫線作成方法。
1. A step of storing inputted ruled line data at a predetermined address of a video memory, wherein when the subsequently inputted data is ruled line data and exists in the same character unit as the previously inputted ruled line data. The step of determining whether or not the two ruled lines have different line lengths, and if the line lengths are different, the previously input ruled line data in character units is called from the video memory and converted into bit information and is input this time. The step of converting the ruled line data into bit information, the step of synthesizing the two pieces of bit information, and the step of creating a ruled line pattern based on the bit information and re-inputting into the called address of the video memory. A ruled line creating method characterized by the above.
JP4124886A 1992-05-18 1992-05-18 Ruled line generating method Pending JPH05181848A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP4124886A JPH05181848A (en) 1992-05-18 1992-05-18 Ruled line generating method

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP4124886A JPH05181848A (en) 1992-05-18 1992-05-18 Ruled line generating method

Related Parent Applications (1)

Application Number Title Priority Date Filing Date
JP58160703A Division JPS6051976A (en) 1983-08-31 1983-08-31 Method and apparatus for preparing ruled line

Publications (1)

Publication Number Publication Date
JPH05181848A true JPH05181848A (en) 1993-07-23

Family

ID=14896532

Family Applications (1)

Application Number Title Priority Date Filing Date
JP4124886A Pending JPH05181848A (en) 1992-05-18 1992-05-18 Ruled line generating method

Country Status (1)

Country Link
JP (1) JPH05181848A (en)

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