JPH0597413A - Amorphous multicomponent semiconductor and device using the same - Google Patents

Abstract

PURPOSE:To obtain an amorphous multicomponent semiconductor capable of effectively utilizing sunbeams in a wide wavelength range when applied to a solar cell and capable of increasing the efficiency of photoelectric conversion because resistance components are made fine by the use of microcrystalline silicon and carriers are effectively collected. CONSTITUTION:Part or all of a semiconductor consisting of one or more kinds of elements selected among C, N, O and S, H and/or halogen and one or more kinds of elements selected among Si, Ge and Sn is made microcrystalline and doped with a group III or V element of the periodic table to obtain a p- or n-type semiconductor. A device using this semiconductor is provided.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to amorphous semiconductors and devices using the same.

[0002]

2. Description of the Related Art Photovoltaic devices and devices such as solar cells and photodetectors can directly convert sunlight into electric energy, but the biggest problem with such devices is that they are compared with other electric energy generating means. It is said that the power generation cost is extremely high. The main reason for this is that the utilization efficiency of the semiconductor material that constitutes the main body of the device is low, and moreover, much energy is required to manufacture such material.

Recently, it has been proposed to use amorphous silicon as the semiconductor material as a technique that may solve this drawback. That is, amorphous silicon can be formed inexpensively and in large quantities by glow discharge in a silicon compound atmosphere such as silane or fluorosilicon, and amorphous silicon in that case (hereinafter abbreviated as GD-aSi). Then, the average localized density of states in the width of the forbidden band is as small as 10 ¹⁷ cm ⁻³ or less, and p-type and n-type impurities can be controlled like crystalline silicon.

In a typical conventional solar cell using GD-aSi, a transparent electrode is formed on a glass substrate which transmits visible light, and a p-type layer of GD-aSi, GD-a, is formed on the transparent electrode.
Si non-doped (impurity-free) layer and GD-aSi
The n-type layer is sequentially formed, and the ohmic contact electrode is provided on the n-type layer.

In the above solar cell, when light enters the p-type layer, the non-doped layer and the n-type layer made of GD-aSi through the glass substrate and the transparent electrode, electrons and / or positive electrons mainly in the non-doped layer are positive. Holes are generated, and these are attracted and moved by the pin junction electric field formed by each of the above layers and then moved to the transparent electrode or the ohmic contact electrode to generate a voltage between both electrodes.

However, the energy conversion efficiency is restricted for the reasons described below, and active research is being conducted in various fields with the aim of improving these. (1) The light absorbed in the doping layer (p layer in the above case) on the light incident side does not become an effective carrier, but becomes a loss. (2) The energy gap of the non-doped layer that generates an effective carrier is about 1.8 eV, and long wavelength light cannot be used. (3) Light absorbed in the doping layer (n layer in the above case) opposite to the light incident side also becomes a loss, and less light is reflected by the back electrode and introduced into the non-doped layer. (4) In addition to the above example, a solar cell with a multilayer structure has been proposed in order to effectively use the solar spectrum in a wide wavelength range, but only some amorphous materials suitable for each layer have been found. Absent. (5) The characteristic of amorphous materials is that they have higher resistance than crystals, which results in lowering the carrier collection efficiency of photoelectric conversion elements. That is, the p layer or the n layer functions as a resistance layer.

Due to the reason (1) above, in particular, a small short-circuit current (Jsc) is obtained, and although it is an incidental phenomenon, the open-circuit voltage (Voc) shows only a low value of 0.8 V. . On the other hand, the inventors of the present invention filed Japanese Patent Application No. 56-12.
313, Japanese Patent Application No. 56-22690, Japanese Patent Application No. 56-6
Inventing an amorphous semiconductor capable of controlling valence electrons to p-type or n-type with a wide gearup as shown in No. 6689, and further finding that larger Jsc and Voc can be obtained by forming a heterojunction pin with amorphous silicon. .

[0008]

The present invention is based on the above (1)-
The present invention has been completed as a result of intensive research aimed at solving all the problems of (5) or developing an amorphous material capable of satisfying those requirements. That is, the present invention is
One or more elements selected from the group of elements consisting of C, N, O and S, one or more elements selected from the group of elements consisting of H and halogen, and elements consisting of Si, Ge and Sn P-type semiconductor characterized in that a part or all of a semiconductor consisting of one or more elements selected from the group is microcrystallized and doped with an element of group III or group V of the periodic table. Alternatively, the contents include an n-type semiconductor and a semiconductor element using the semiconductor.

The details will be described below. The microcrystal or amorphous semiconductor used in the present invention is C,
It is obtained by glow discharge decomposition of a gaseous or gasified compound, which is an appropriate combination of N, O, S, H, halogen, Si, Ge and Sn. Also, C,
As a target, a solid compound appropriately combined with N, O, S, H, halogen, Si, Ge and Sn is used as a target or the presence of a gas appropriately combined with C, N, O, S, H and halogen. It can also be obtained by spattering the target below. The substrate temperature at the time of performing the glow discharge method and the sputtering method is not particularly limited, but usually 200 ° C to 450 ° C is used.

The amount of Si contained in the microcrystal or amorphous amorphous semiconductor used in the present invention is preferably 50 atomic% or more, and more preferably all of the elements selected from the group consisting of C, N, O and S. It is preferable that the total amount of elements is 30 atomic% or less in the semiconductor. More preferably, the total amount of H and halogen contained in the semiconductor is about 1 or less.
It may be contained in the range of atomic% to about 40 atomic%. Further, among halogens, fluorine is the most preferable element.

In the case of doping, a compound of a group III element such as B ₂ H ₆ or a compound of a group V element such as PH ₃ is added at the time of film formation, or an ion implantation method after film formation is carried out. Can be used. The doping amount is such that the dark conductivity at 20 ° C. is 10 ⁻⁸ (Ω · cm) ⁻¹ or more, and when the junction is formed to be used as a solar cell, the diffusion potential is set to a desired value. To be elected.

The case where the above-mentioned microcrystalline multi-element semiconductor is applied to a solar cell will be described below. Amorphous multi-element semiconductors or microcrystalline multi-element semiconductors
Since the gears can be chosen quite arbitrarily, materials having a composition suitable for each layer of amorphous solar cells can be used.

A material having a large energy gap is suitable for the doping layer, and in particular, the optical bandgap (Eg.opt) of the window material used on the light incident side is preferably 1.85 eV or more. In addition, the Eg · opt of the non-doped layer that can generate an effective carrier is the Eg · opt.
If opt has a single value, the smaller is preferred.
However, more preferably, Eg · opt of the non-doped layer
Has a large value of 2 eV or more on the light incident side, decreases toward the direction opposite to the light incident side, and finally becomes about 1 eV. As a solar cell devised based on such a concept, there is a multi-layered solar cell called a graded type, (multi) stacked type or tandem type solar cell, but the semiconductor of the present invention is applicable to any of these layers. It is possible to provide a sufficiently satisfactory material. Therefore, by applying the amorphous semiconductor or the microcrystalline semiconductor to the solar cell, the solar spectrum having a wide wavelength range can be effectively used. Further, even if the solar cell does not have such a complicated structure, a microcrystalline or amorphous multi-element semiconductor is used for each layer of a general structure, for example, a pin type solar cell, Can also get improved performance. In these solar cells, it is preferable that at least one junction has a diffusion potential of 1.1 V or more, and at least one doping layer, preferably, a doping side on the light incident side. Layer thickness is about 30-300
It is preferably Å. In addition, Eg · o of the non-doped layer
For the purpose of reducing pt, among multi-element semiconductors, at least one element selected from the group of elements consisting of Si, Ge, and Sn and at least one element selected from the group of elements consisting of H and F Although it is preferable to use an intrinsic semiconductor or a microcrystalline semiconductor composed of the element (3), the element may be compensated with a group III element to make it substantially intrinsic.

The present invention will be specifically described below by taking a nip type graded structure solar cell as an example, but the semiconductor device of the present invention is not limited to this structure.

One of the typical examples of this structure is a structure of transparent electrode / n-type microcrystalline semiconductor / i-type amorphous semiconductor / p-type microcrystalline semiconductor / electrode / insulating film / metal foil. Irradiate. The thickness of the n-type amorphous semiconductor on the side irradiated with light is about 30Å to 300Å, preferably 5Å
0 Å ~ 200 Å, i layer thickness is not limited, but about 100
0Å to 10000Å is usually used. The thickness of the p layer is not limited, but about 100Å to 600Å is used. The transparent electrode is preferably ITO or SnO _{2, and} particularly ITO, and can be obtained by directly vapor-depositing on an n-type microcrystalline semiconductor. It is more preferable to add SnO ₂ of 30 to 500 Å to the interface between the ITO and the n-type microcrystalline semiconductor.

The n-type microcrystalline semiconductor has an Eg · opt of 1.8.
It is preferably 5 eV or more, and particularly preferably Si as a main component, to which C, N, O, S, H, and halogen are added. More preferably, the light incident side is closer to C, N, O, S,
It is preferable to increase the amounts of H and halogen added and gradually reduce the amounts of C, N, O, and S added toward the i layer.

The i-type amorphous semiconductor is preferably a semiconductor obtained by adding H or halogen to Si from about 1/3 to half of the thickness of the i-layer from the light incident side, and the remaining i-layer contains Ge or Sn. Addition, and the amount added was gradually increased toward the p-layer side, and finally the Eg · opt was increased to 1
It is preferably about eV.

The p-type amorphous semiconductor is preferably made of a material having a relatively large Eg · opt in order to effectively use the reflected light from the back electrode.

The substrate is a glass substrate with a transparent electrode generally used for solar cells, a metal substrate such as stainless steel,
A heat resistant polymer film such as polyimide can be used. Also, metal foil such as aluminum, copper, iron, nickel, and stainless steel, or heat-resistant polymer or SiO ₁ , Si
O ₂ , Al ₂ O ₃ , amorphous or crystalline Si
_(1-X) C _(X) , Si _(1-y) Ny, Si _(1-Xy) C _(X) N
A substrate coated with an insulating substance such as _(y) or its hydrogen and / or halide may also be used. In particular, when the power generation area is divided into a plurality of parts and each of them is connected in parallel or in series, it is necessary to use an insulating substrate.As a substrate for this purpose, glass or a heat-resistant polymer film, Is preferably a substrate obtained by coating the above-mentioned insulating material on a metal foil, and using a substrate formed by patterning electrodes on this, a semiconductor may be formed thereon.

When the insulating material is coated on the metal foil, the electric conductivity of this insulating thin film is about 10 ⁻⁷ (Ω · c).
m) ^-1 or less is preferable. The thickness of the metal foil is not particularly limited, but is preferably 5 μm to 2 mm, particularly 50 μm to 1
mm is preferred. The thickness of the insulating film is optional as long as it can insulate the metal foil, but it is usually used in the range of 1000 Å to 20 μm.

1 to 3 show a photovoltaic device as an embodiment of the present invention, 11 is a metal foil and 12 is an insulating film.
Reference numerals 3, 14, and 15 are first, second, and third power generation areas formed in a film shape on the insulating substrate.

Each of the power generation areas is opposed to the amorphous or multi-source semiconductor layer 16 with the first electrode 1 interposed therebetween.
7 and the second electrode 18. Semiconductor layer 16
Although not shown, for example, p sequentially deposited from the substrate side
Layer, a non-doped layer (i layer) and an n layer semiconductor layer, and the semiconductor layer 16 extends continuously to the first to third power generation zones.

The first electrode 17 is made of metal or tin oxide, indium oxide, ITO (In ₂ O _{3) that} makes ohmic contact with the p-layer.
+ XSnO ₂ , x ≦ 0.1) or the like, but one having ITO with 50 to 500 Å SnO ₂ is particularly preferable. The second electrode 18 is transparent tin oxide In
₂ O ₃ , ITO, or an electrode in which ITO is attached on SnO ₂ or the like. The first electrode 17 and the second electrode 18 of each of the first to third power generation zones 13-15 have extensions 19 and 20 on the substrate 12 that extend out of the respective power generation zone, and The extension portion 20 of the second electrode 18 and the extension portion 19 of the first electrode 17 of the second power generation section 14, and the extension portion 20 of the second electrode 18 of the second power generation section 14 and the first portion of the third power generation section 15 The extension portions 19 of the electrodes 17 are overlapped with each other and are electrically connected. Further, a connection portion 21 made of the same material as that of the second electrode 18 is superposed on the extension portion 19 of the first electrode 17 in the first power generation area 13. It should be noted that 21 may be omitted.

The manufacturing method of the above device will be briefly described below.
In the first step, each of the first electrodes 17 including the extension portion 19 is formed on the substrate (11 + 12) by the selective etching method or the selective sputtering method or the vapor deposition adhesion method, and in the second step, the first to third power generation areas are formed. The semiconductor layer 16 is continuously formed.

At this time, since the layer must not exist in the extension portions 19 and 20, after forming the semiconductor layer on the entire surface of the substrate 7, the unnecessary portion is removed by the selective etching method, or the unnecessary portion is removed. The semiconductor layer is formed only in a desired portion by using a mask that covers the. In the subsequent final step, the second electrode 18 including the extension portion 20 and the connection portion 2
1 is formed by selective sputtering or vapor deposition.
In the device of this embodiment, when light enters the semiconductor layer 16 through the second electrode 18, an electromotive voltage is generated in each of the first to third power generation areas 13 to 15, and the first and second electrodes 1 in each area are generated.
Since 7 and 18 are alternately connected in the extension, the electromotive voltages of the respective areas are added in series, and the first power generation area 1
The connecting portion 21 connected to 3 is the positive electrode, and the second connecting portion of the third power generation area 15 is
The voltage applied as described above is generated between the two electrodes with the extension 20 connected to the electrode 18 as the negative electrode.

Further, in the above-mentioned device, when the adjacent intervals between the power generation areas are small, a phenomenon in which a current directly flows between the first electrodes 17 or the second electrodes 18 in the adjacent areas, that is, a leakage current is generated. However, considering that the resistance value of the semiconductor layer 16 at the time of light irradiation is several to several tens of MΩ, by setting the above-mentioned adjacent interval to 1 μm or more,
The influence of the leakage current does not substantially cause a problem. If necessary, the semiconductor layer 16 may be formed separately in each power generation area, and the back surface electrode and the adjacent light receiving side electrode may be connected in series.
In practical use, a transparent polymer insulating film or SiO ₂ , a-SiC, a-S that closely surrounds the second electrode side is used.
It is preferable to provide a transparent insulating film such as iN or a-SiCN for protection. As a matter of course, a translucent substrate may be used.

As is clear from the above description, according to the structure of the present invention, a plurality of power generation areas are connected in series on the same substrate by using microcrystals or amorphous multi-element semiconductors, which are flexible. It is possible to obtain a device that is small in size and that can generate an arbitrary high voltage, and that it can be made in the same way as a conventional glass substrate was realized by using a substrate with an insulated metal foil. The manufacturing process is almost the same as the conventional manufacturing process and can be performed only by a simple film forming process, which is excellent in mass production.

Although such a solar cell can be incorporated into a small electronic device as a battery operated under a fluorescent lamp, it may be used under strong light such as AM-1 100 mw / cm ^2. In such a case, a protection circuit is usually required, but if a material having a high electric conductivity during light irradiation such as amorphous silicon is used as the insulating film 12, the electric conductivity is small under a fluorescent lamp, so that a leak occurs. However, it is preferable that strong light, such as outdoor light, increases electrical conductivity, leaks photocurrent, and functions as a protective circuit. Further, in the case of producing the amorphous amorphous semiconductor used in the present invention by glow discharge decomposition, r
An apparatus provided with a magnetic field having a region that is at least partially orthogonal to the f electric field can be used to increase the film forming speed and improve the film quality.

[0029]

As described above, when the semiconductor of the present invention is applied to a solar cell, the solar spectrum having a wide wavelength range can be effectively used. Further, by using a p-type or n-type material of microcrystalline silicon instead of the amorphous material, the resistance component is reduced, so that the carriers generated inside the photoelectric conversion element can be effectively collected. Increasing the amount of microcrystalline silicon can also increase the light transmittance, increasing the amount of light incident on the photoactive layer,
The efficiency of the photoelectric conversion element can be improved.

[Brief description of drawings]

FIG. 1 is a side view showing an embodiment.

FIG. 2 is a sectional view taken along line BB in FIG.

FIG. 3 is a sectional view taken along line CC of FIG.

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁵ Identification code Internal reference number FI Technical display location C01G 17/00 7202-4G 19/00 7202-4G C03C 8/14 6971-4G H01L 21/31 8518 -4M 31/04 // B01J 19/08 Z 6345-4G

Claims (16)

[Claims] 1. At least one element selected from the group of elements consisting of C, N, O and S, at least one element selected from the group of elements consisting of H and halogen, and Si and Ge. ,
Part or all of a semiconductor consisting of one or more elements selected from the group of elements consisting of Sn is microcrystallized and doped with an element of group III or group V of the periodic table P-type or n-type semiconductor. 2. The semiconductor according to claim 1, wherein the halogen is F. 3. The semiconductor according to claim 1, wherein the composition of Si is 50 atomic% or more. 4. The semiconductor according to claim 3, wherein the sum of all elements selected from the group of elements consisting of C, N, O and S is about 30 atomic% or less. 5. The sum of Si and all elements selected from the group of elements consisting of C, N, O and S is 60 atomic% or more and 9 or more.
It is 9 atomic% or less, The semiconductor of Claim 3 or 4 characterized by the above-mentioned. 6. The dark conductivity at 20 ° C. is 10 ⁻⁸ (Ω · c)
The semiconductor according to claim 1, wherein m) ^-1 or more. 7. An intrinsic semiconductor composed of one or more elements selected from the group of elements consisting of Si, Ge and Sn and one or more elements selected from the group of elements consisting of H and F. 7. The semiconductor element as a layer, which is a constituent element of a doping layer, according to claim 1. 8. At least one of the doping layers has an optical bandgap Eg · opt of 1.8.
8. The voltage is 5 eV or more, and the diffusion potential of at least one junction is 1.1 V or more.
The semiconductor device described. 9. The semiconductor device according to claim 8, wherein the thickness of at least one of the doping layers is about 30 to 3000Å. 10. The structure of the semiconductor element is a pin type or a laminated type thereof.
The semiconductor device described. 11. The semiconductor device has a plurality of power generation areas formed on an electrically insulating substrate, and the current collecting means of the areas are mutually connected so that the photovoltaics in the areas are in a series relationship. The semiconductor device according to claim 7, wherein the semiconductor device is electrically connected. 12. The semiconductor device according to claim 11, wherein the plurality of semiconductor devices are formed as thin films on an electrically insulating substrate formed on a metal foil. 13. The heat-insulating polymer as the electrically insulating thin film,
Or SiO, SiO ₂ , Al ₂ O ₃ , or amorphous or crystalline Si _(1-X) C _(X) , Si
_{(1-y) N (y} ), Si (1-Xy) C z N y or a semiconductor device according to claim 12, wherein the selected from Amorufu Ass silicon. 14. The semiconductor device according to claim 7, further comprising a transparent electrode provided on at least one side of the semiconductor device. 15. The transparent electrode is ITO or Sn.
Approximately 30 to 5 at the interface between O ₂ or ITO and the amorphous layer.
The semiconductor device according to claim 14, which is an ITO-SnO ₂ composite electrode provided with 00Å SnO ₂ . 16. The amorphous semiconductor is rf.
7. Manufactured by performing glow discharge decomposition using a device comprising a magnetic field having a region at least partially orthogonal to the electric field.
5. The semiconductor device according to item 5.