JPS62256481A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPS62256481A JPS62256481A JP61099939A JP9993986A JPS62256481A JP S62256481 A JPS62256481 A JP S62256481A JP 61099939 A JP61099939 A JP 61099939A JP 9993986 A JP9993986 A JP 9993986A JP S62256481 A JPS62256481 A JP S62256481A
- Authority
- JP
- Japan
- Prior art keywords
- type semiconductor
- layer
- semiconductor layer
- type
- side electrode
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 191
- 239000012535 impurity Substances 0.000 claims abstract description 37
- 238000000034 method Methods 0.000 abstract description 8
- 238000006243 chemical reaction Methods 0.000 abstract description 6
- 238000010521 absorption reaction Methods 0.000 abstract description 3
- 239000004020 conductor Substances 0.000 description 17
- 239000000463 material Substances 0.000 description 8
- 239000011521 glass Substances 0.000 description 7
- 239000000758 substrate Substances 0.000 description 7
- 230000000737 periodic effect Effects 0.000 description 6
- 238000005268 plasma chemical vapour deposition Methods 0.000 description 6
- 230000000052 comparative effect Effects 0.000 description 5
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 4
- 229910052796 boron Inorganic materials 0.000 description 4
- 230000015572 biosynthetic process Effects 0.000 description 3
- 238000004519 manufacturing process Methods 0.000 description 3
- 239000002994 raw material Substances 0.000 description 3
- 239000000126 substance Substances 0.000 description 3
- 229910017817 a-Ge Inorganic materials 0.000 description 2
- 230000004913 activation Effects 0.000 description 2
- 238000009826 distribution Methods 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 230000031700 light absorption Effects 0.000 description 2
- 229910052751 metal Inorganic materials 0.000 description 2
- 239000002184 metal Substances 0.000 description 2
- 150000002739 metals Chemical class 0.000 description 2
- 238000004544 sputter deposition Methods 0.000 description 2
- 238000007738 vacuum evaporation Methods 0.000 description 2
- 101000995861 Arabidopsis thaliana Regulatory protein NPR1 Proteins 0.000 description 1
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 1
- 229910020328 SiSn Inorganic materials 0.000 description 1
- 229910000577 Silicon-germanium Inorganic materials 0.000 description 1
- 229910021417 amorphous silicon Inorganic materials 0.000 description 1
- 229910052785 arsenic Inorganic materials 0.000 description 1
- 150000001875 compounds Chemical class 0.000 description 1
- 238000000354 decomposition reaction Methods 0.000 description 1
- 230000007423 decrease Effects 0.000 description 1
- 230000006866 deterioration Effects 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- 239000007772 electrode material Substances 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 150000002500 ions Chemical class 0.000 description 1
- 230000003287 optical effect Effects 0.000 description 1
- 229910052698 phosphorus Inorganic materials 0.000 description 1
- 239000011574 phosphorus Substances 0.000 description 1
- 229910021425 protocrystalline silicon Inorganic materials 0.000 description 1
- 229910021332 silicide Inorganic materials 0.000 description 1
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 238000002230 thermal chemical vapour deposition Methods 0.000 description 1
- 238000007740 vapor deposition Methods 0.000 description 1
Classifications
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02E—REDUCTION OF GREENHOUSE GAS [GHG] EMISSIONS, RELATED TO ENERGY GENERATION, TRANSMISSION OR DISTRIBUTION
- Y02E10/00—Energy generation through renewable energy sources
- Y02E10/50—Photovoltaic [PV] energy
Abstract
Description
【発明の詳細な説明】
［産業上の利用分野］
本発明は半導体装置に関する。さらに詳しくは光電変換
効率を向上させた光起電力素子からなる半導体装置に関
する。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor device. More specifically, the present invention relates to a semiconductor device comprising a photovoltaic element with improved photoelectric conversion efficiency.
［従業の技術］
一般に非晶質半導体層が形成されている太陽電池などの
半導体装置に使用される非晶質半導体としてはａ−３ｉ
：ＨＳａ−ＳｉＣ：Ｈ％ａ−８ＩＧｅ：Ｈｓａ−８ＩＮ
：Ｈ、ａ−８１：Ｐ：Ｈ％ａ−Ｇｅ：Ｈなどやこれらに
微結晶相を含ませた半導体が用いられている。[Employee's technology] A-3I is generally used as an amorphous semiconductor for semiconductor devices such as solar cells in which an amorphous semiconductor layer is formed.
:HSa-SiC:H%a-8IGe:Hsa-8IN
:H, a-81:P:H%a-Ge:H, and semiconductors containing these with a microcrystalline phase are used.
従来の太陽電池などの半導体装置においては、その起電
力発生部分が前記半導体に不純物を加えたｐ型層導体お
よびｎ型半導体と、真性半導体またはそれに微量の不純
物を加えた半導体からなるｎ型層導体とをｐｌｎ ｐｉ
ｎ・・・あるいはｎ１ｐｎｉｐ・・・の順に順次積層し
た構造となっている。In a conventional semiconductor device such as a solar cell, the electromotive force generating portion is composed of a p-type layer conductor and an n-type semiconductor made by adding an impurity to the semiconductor, and an n-type layer made of an intrinsic semiconductor or a semiconductor with a trace amount of impurity added thereto. conductor and pln pi
It has a structure in which layers are sequentially stacked in the order of n... or n1pnip....
第２図は３層構造のｐｉｎ型半導体を使用した従来の太
陽電池などに用いられる半導体装置を示している。図に
おいて（１）はガラス基板であり、ガラス基板（１）上
にはこれに固着して透明電極であるｐ層側電極（２）が
形成されており、ｐ層側電極（２）上にはこれに固着し
てｎ型層導体層（４）が形成されている。そしてｎ型層
導体層（４）上にはこれに固着してｎ型層導体層（５）
が形成されており、さらにその上にはこれに固着してｎ
型半導体層（６）が形成されている。そしてさらにｎ型
半導体層（６）上にはこれに固着してｎ層側電極（７′
）が形成されている。そして前記ガラス基板（１）、ｐ
層側電極（２）、ｎ型層導体層（４）、ｎ型層導体層（
５）、ｎ型半導体層（６）およびｎ層側電極（７）とに
より半導体装置（８）が構成されている。FIG. 2 shows a semiconductor device used in a conventional solar cell, etc., which uses a pin-type semiconductor with a three-layer structure. In the figure, (1) is a glass substrate, and a p-layer side electrode (2), which is a transparent electrode, is formed on the glass substrate (1), and is fixed to the glass substrate (1). An n-type conductor layer (4) is formed by adhering to this. Then, on the n-type layer conductor layer (4), an n-type layer conductor layer (5) is fixed to this.
is formed, and furthermore, n is fixed to this.
A type semiconductor layer (6) is formed. Further, on the n-type semiconductor layer (6), an n-layer side electrode (7') is fixedly attached.
) is formed. and the glass substrate (1), p
Layer side electrode (2), n-type layer conductor layer (4), n-type layer conductor layer (
5) A semiconductor device (8) is constituted by the n-type semiconductor layer (6) and the n-layer side electrode (7).
そしてこのような半導体装置（８）において光が第２図
矢符方向にそって進んでガラス基板（１）内に入射し、
さらにガラス基板（１）内およびｐ層側電極（′２Ｊ内
を透過してｐ型、ｎ型およびｎ型半導体層（４）、（５
）、（６）に照射する。そしてこの照射によって各半導
体層（４）、（５）、（６）内に電子と正孔の対が生じ
、電子がｎ型層に集められ、正孔がｐ型層に集められる
ことによってｐ層側電極（２に正、ｎ層側電極（７）に
負の電荷が生じる。このようにして光電変換が行なわれ
半導体装置（８）が光電池として機能するようになる。In such a semiconductor device (8), light travels along the direction of the arrow in FIG. 2 and enters the glass substrate (1),
Further, it passes through the glass substrate (1) and the p-layer side electrode ('2J) to p-type, n-type, and n-type semiconductor layers (4), (5
), (6). This irradiation generates pairs of electrons and holes in each semiconductor layer (4), (5), and (6), and electrons are collected in the n-type layer and holes are collected in the p-type layer, resulting in p A positive charge is generated on the layer side electrode (2) and a negative charge is generated on the n layer side electrode (7). Photoelectric conversion is performed in this way, and the semiconductor device (8) comes to function as a photovoltaic cell.
ここでｎ型層導体層（４）あるいはｎ型半導体層（６）
の不純物の濃度分布は半導体装置の作製時およびその後
に生じる熱に起因する拡散による分布変動を除けばｐ型
およびｎ型の各半導体層（４）、（６）内において一様
となっており、その不純物濃度は通常０．Ｏ１〜１．０
原子％の範囲にある。Here, the n-type conductor layer (4) or the n-type semiconductor layer (6)
The impurity concentration distribution is uniform in each of the p-type and n-type semiconductor layers (4) and (6), except for distribution fluctuations due to diffusion caused by heat generated during and after the fabrication of the semiconductor device. , its impurity concentration is usually 0. O1~1.0
in the atomic percent range.
［発明が解決しようとする問題点］
ｐｎ型層導体層ｐ層側電極およびｎ型層、導体層とｎ層
側電極との接触抵抗は一般に不純物濃度が大きくなるほ
ど小さくなることが知られている。そしてこの接触抵抗
はｎ型層導体層およびｎ型半導体層が太陽電池などの光
起電力素子用として使用されるばあいには光起電力素子
としての曲線因子を悪化させる原因となるので小さくす
ることが望ましい。従ってかかる観点からは不純物濃度
を大きくすることが望ましい。[Problems to be Solved by the Invention] It is known that the contact resistance between the p-type layer conductor layer, the p-layer side electrode and the n-type layer, and the conductor layer and the n-layer side electrode generally decreases as the impurity concentration increases. . When the n-type conductor layer and the n-type semiconductor layer are used for a photovoltaic device such as a solar cell, this contact resistance should be made small because it causes deterioration of the fill factor of the photovoltaic device. This is desirable. Therefore, from this point of view, it is desirable to increase the impurity concentration.
しかしながらｎ型半導体層およびｎ型層導体層の不純物
濃度があまり大きくなりすぎると、この不純物部分での
光の吸収損失が大きくなるなどによって光起電力素子と
しての特性が悪化するという問題がある。However, if the impurity concentration of the n-type semiconductor layer and the n-type conductor layer becomes too high, there is a problem that the characteristics as a photovoltaic element deteriorate due to increased absorption loss of light in the impurity portion.
本発明はこのような問題を解決するためになされたもの
で光電変換効率が向上した半導体装置を提供することを
目的としている。The present invention was made to solve such problems, and an object of the present invention is to provide a semiconductor device with improved photoelectric conversion efficiency.
ｃ問題点を解決するための手段］
本発明による半導体装置はｎｉｐ型またはｐｉｎ型の非
晶質を含む半導体と、該半導体中のｎ型層導体層に接続
されたｐ層側電極と前記半導体中のｎ型半導体層に接続
されたｎ層側電極とが設けられた半導体装置においてｎ
型層導体層とｐ層側電極との間および／またはｎ型半導
体層とｎ層側電極との間に各々前記ｎ型層導体層と同じ
導電型でありかつ不純物濃度が高い高濃度ｎ型層導体層
および／または前記ｎ型半導体層と同じ導電型でありか
つ不純物濃度が高い高濃度ｎ型半導体層を介装させたも
のである。Means for Solving Problem c] A semiconductor device according to the present invention includes a nip-type or pin-type semiconductor containing amorphous, a p-layer side electrode connected to an n-type layer conductor layer in the semiconductor, and the semiconductor. In a semiconductor device provided with an n-layer side electrode connected to an n-type semiconductor layer inside
A highly doped n-type layer having the same conductivity type as the n-type conductor layer and having a high impurity concentration is placed between the type layer conductor layer and the p-layer side electrode and/or between the n-type semiconductor layer and the n-layer side electrode. A high-concentration n-type semiconductor layer having the same conductivity type as the conductive layer and/or the n-type semiconductor layer and having a high impurity concentration is interposed therebetween.
［実施例コ
本発明に用いられるｐｉｎ型またはｎｉｐ型の非品質を
含む半導体において、ｎ型半導体層としては、たとえば
ａ−！ｌｉｔ：Ｈ％ａ−ＳｉＧｅ：Ｈｓ ａ−Ｇｅ：Ｉ
ｌ、ａ−８ｔ：Ｆ：Ｈ，ａ−８ＩＮ：Ｈｌａ−ＳｉＳｎ
：Ｈやこれらにホウ素、リンなどの微量をドーピングし
た半導体が使用され、その層の厚さは２５００〜９００
０人程度である。またｎ型半導体層としては、たとえば
ａ−８ＩＣ：Ｈ、ｐ ｃ−Ｓｉ：Ｉ、ａ−９１：Ｈに周
期律表ｍｂ族の元素をドーピングした半導体が使用され
、その層の厚さは８０〜３００人程度である。さらにま
たｎ型半導体層としては、たとえばａ−８１：ＩＩ、ｕ
ｃ−８１：Ｈ，ａ−８１ｅ：ＩＩに周期律表ｖｂ族の元
素をドーピングした半導体が使用され、その層の厚さは
８０〜８００人程度である。[Example 2] In the pin type or nip type semiconductor including non-quality used in the present invention, as the n type semiconductor layer, for example, a-! lit:H%a-SiGe:Hs a-Ge:I
l, a-8t: F: H, a-8IN: Hla-SiSn
: H or a semiconductor doped with trace amounts of boron, phosphorus, etc. is used, and the thickness of the layer is 2500 to 900 mm.
Approximately 0 people. Further, as the n-type semiconductor layer, for example, a semiconductor obtained by doping a-8IC:H, pc-Si:I, or a-91:H with an element of group MB of the periodic table is used, and the thickness of the layer is 80°C. ~300 people. Furthermore, as the n-type semiconductor layer, for example, a-81:II, u
Semiconductors in which c-81:H and a-81e:II are doped with elements of Group VB of the periodic table are used, and the thickness of the layer is about 80 to 800 layers.
そして前記ｎ型半導体層についてはａ−８ＩＣ：ＩＩ
。And for the n-type semiconductor layer, a-8IC:II
.
ａ−Ｓｉ ： Ｈに周期律表ｍｂ族の元素をドーピング
したものが電気伝導に寄与する正孔を発生する活性化エ
ネルギーの値が小さく光の吸収損失も小さいなどの点か
ら好ましい。また前記ｎ型半導体層についてはａ−８ｌ
ｃ：Ｈｓ μｃ−８１：Ｈ％ａ−ｓｔ：ｎに周期律表ｖ
ｂ族の元素をドーピングしたものが、電気伝導に寄与す
る電子を発生する活性化エネルギーが小さくまた導電率
が高いなどの点から好ましい。しかし前記ｎ型半導体層
、ｎ型半導体層およびｎ型半導体層に使用される物質は
前記のものに限定されるものではない。a-Si:H doped with an element in Group MB of the periodic table is preferable because it has a small activation energy for generating holes that contribute to electrical conduction and a small light absorption loss. Also, regarding the n-type semiconductor layer, a-8l
c: Hs μc-81: H% a-st: n in the periodic table v
A material doped with a group b element is preferable because it has low activation energy for generating electrons that contribute to electrical conduction and has high electrical conductivity. However, the materials used for the n-type semiconductor layer, the n-type semiconductor layer, and the n-type semiconductor layer are not limited to those described above.
またｐ型半導体用不純物として周期律表ｍｂ族の元素（
Ｂ、 ＃％ ０８％ ｌｎｘ Ｔｌなど）を使用しま
たｎ型半導体用不純物として周期律表ｖｂ族の元素（Ｎ
％ｐ、 Ａｓ、 ９ｂなど）を使用するばあいを示した
が、ドーピングすることにより半導体がｐ型あるいはｎ
型の導電性を示すものであればこれらに限定されるもの
ではない。In addition, as an impurity for p-type semiconductors, elements of group mb of the periodic table (
B, #% 08% lnx Tl, etc.), and elements of group Vb of the periodic table (N
%p, As, 9b, etc.), but by doping the semiconductor becomes p-type or n-type.
The material is not limited to these as long as it exhibits the conductivity of the mold.
また本発明における非晶質を含む半導体とは非晶質のみ
からなる半導体または非晶質の半導体中に微細な粒状の
結晶半導体が分散する半導体または大きな粒状の結晶半
導体の間に非晶質半導体が分散する半導体のことである
。In addition, in the present invention, a semiconductor containing an amorphous substance is a semiconductor consisting only of an amorphous substance, a semiconductor in which fine grains of crystalline semiconductor are dispersed in an amorphous semiconductor, or an amorphous semiconductor between large grains of crystalline semiconductor. It refers to a semiconductor in which ions are dispersed.
本発明においてｎ型半導体層とｐ層側電極の間および／
またはｎ型半導体層とｎ層側電極の間に設けられた高濃
度ｎ型半導体層および／または高濃度ｎ型半導体層の不
純物濃度は通常の不純物濃度の２倍以上であり、好まし
くは４倍以上である。そしてその不純物濃度は上限はな
いが通常ｌＯ原原子量以下している。またこれらの高濃
度半導体層の厚みは１０〜３００人であり、好ましくは
３０〜１５０人８ある。In the present invention, between the n-type semiconductor layer and the p-layer side electrode and/or
Alternatively, the impurity concentration of the high concentration n-type semiconductor layer and/or the high concentration n-type semiconductor layer provided between the n-type semiconductor layer and the n-layer side electrode is twice or more, preferably four times the normal impurity concentration. That's all. Although there is no upper limit to the impurity concentration, it is usually below the original atomic weight of 1O. Moreover, the thickness of these high concentration semiconductor layers is 10 to 300, preferably 30 to 150.
実施例１
以下本発明による半導体装置の実施例を図によって説明
する。Example 1 An example of a semiconductor device according to the present invention will be described below with reference to the drawings.
第１図は本発明による半導体装置の実施例１を示ルてお
り、３層型のｐｉｎ型半導体装置を示している。第１図
において第２図と同一符号は同一のものを示す。第１図
においてｐ層側電極（２）とｎ型半導体層（４）との間
にはこれらの各々上面および下面に固着して高濃度ｎ型
半導体層（３）が形成されている。FIG. 1 shows a first embodiment of a semiconductor device according to the present invention, and shows a three-layer pin type semiconductor device. In FIG. 1, the same reference numerals as in FIG. 2 indicate the same parts. In FIG. 1, a high concentration n-type semiconductor layer (3) is formed between the p-layer side electrode (2) and the n-type semiconductor layer (4), fixed to the upper and lower surfaces of these layers, respectively.
また本発明においてｐｉｎ型半導体層の構造は非晶質半
導体系の光起電力素子やフォトダイオードなどに一般的
に用いられている構造と同じである。Further, in the present invention, the structure of the pin type semiconductor layer is the same as that commonly used in amorphous semiconductor photovoltaic elements, photodiodes, and the like.
つぎに実施例１に係る半導体装置の製造方法について説
明する。Next, a method for manufacturing a semiconductor device according to Example 1 will be described.
まずガラス基板（１）上に透明電極であるｐ層側電極（
２）をスパッタ法により蒸着して形成する。First, place the p-layer side electrode (transparent electrode) on the glass substrate (1).
2) is formed by vapor deposition using a sputtering method.
透明電極材料としては５ｎ０２を使用する。形成される
ｐ層側電極（２）の厚さは５０００人である。5n02 is used as the transparent electrode material. The thickness of the formed p-layer side electrode (2) is 5000 mm.
つぎにｐ層側電極（２）上にプラズマＣＶＤ法によりＳ
ＩＣ：ｔｌの半導体にホウ素をドーピングした高濃度ｎ
型半導体層（３）を形成する。高濃度ｎ型半導体層（３
）の形成において使用する原料ガスは５ｔＨ４、Ｃ１１
ａ、Ｂ２Ｈ６／Ｈ２（８２Ｈ６濃度が１０００ｐｐＩＩ
ｌである）であり、各ガスの流量は各々ＩＯ３ＣＣＭ、
３０ＳＣＣＭ、２００ＳＣＣＭである。形成される高濃
度ｎ型半導体層（３）の厚さは１００人であり、この層
の不純物濃度は４％となる。Next, S is deposited on the p-layer side electrode (2) using the plasma CVD method.
IC: high concentration n doped with boron in tl semiconductor
A type semiconductor layer (3) is formed. High concentration n-type semiconductor layer (3
) The raw material gas used in the formation is 5tH4, C11
a, B2H6/H2 (82H6 concentration is 1000 ppII
), and the flow rates of each gas are IO3CCM,
30SCCM, 200SCCM. The thickness of the high concentration n-type semiconductor layer (3) to be formed is 100 mm, and the impurity concentration of this layer is 4%.
つぎに高濃度ｎ型半導体層（３）上にこれと同様にＳｉ
Ｃ：ｆｌの半導体にホウ素をドーピングしたｎ型半導体
層（３）をプラズマＣＶＤ法により形成する。Next, Si is similarly placed on the high concentration n-type semiconductor layer (3).
C: An n-type semiconductor layer (3) in which a fl semiconductor is doped with boron is formed by plasma CVD.
このばあいにおいては８２Ｈ６／＋１２のガスの流量を
５０３ＣＣＨに変化させる以外は前記高濃度ｐ型半導体
層（３）の形成のばあいと同様の方法でｐ型半導体層（
４）の形成をおこなう。そして形成されるｐ型半導体層
（４）の厚さは１００人であり、この層の不純物濃度は
１％となる。In this case, the p-type semiconductor layer (
4) Formation is performed. The thickness of the formed p-type semiconductor layer (4) is 100 mm, and the impurity concentration of this layer is 1%.
つぎに原料ガスとして５ＩＨａを使用してグロー放電に
よりｐ型半導体層（４）上にａ−８１：Ｉｆのｎ型半導
体層（５）を形成する。形成されるｎ型半導体層（５）
の厚さは５０００人である。Next, an n-type semiconductor layer (5) of a-81:If is formed on the p-type semiconductor layer (4) by glow discharge using 5IHa as a raw material gas. N-type semiconductor layer (5) formed
Its thickness is 5,000 people.
そしてつぎにｎ型半導体層（５）上に、原料ガスとして
５ｉＨａ、ＰＨ３／Ｈ２（Ｐ１１３濃度が１０００ｐｐ
ｌである）を使用しグロー放電分解法によりｎ型半導体
層（６）を形成する。５ＩＨ４ガスおよびＰＨｓ／Ｈｚ
ガスの流量は各々ＩＯ８ＣＣＭおよび５０ＳＣＣＭであ
る。Then, on the n-type semiconductor layer (5), 5iHa and PH3/H2 (P113 concentration of 1000 pp) are applied as source gas.
An n-type semiconductor layer (6) is formed by a glow discharge decomposition method using 1. 5IH4 gas and PHs/Hz
The gas flow rates are IO8CCM and 50SCCM, respectively.
形成されるｎ型半導体層（６）の厚さは３００人であり
、この層の不純物濃度は０．５％となる。The thickness of the n-type semiconductor layer (6) to be formed is 300 mm, and the impurity concentration of this layer is 0.5%.
さらにｎ型半導体層（６）上に真空蒸着法によりＡｇを
蒸着してｎ層側電極（７）を形成した。形成されたｎ層
側電極（７）の厚さは１０００人である。Further, Ag was deposited on the n-type semiconductor layer (6) by vacuum evaporation to form an n-layer side electrode (7). The thickness of the formed n-layer side electrode (7) is 1000 mm.
そしてこのようにして作製される本実施例に係る半導体
素子（ｐｉｎ型半導体層）の面積は１ｃｉ程度のもので
あるが、１〜５００ ｃｄのものが作製できる。しかし
かかる面積は本発明において限定されるものではない。The area of the semiconductor element (pin-type semiconductor layer) according to this example thus manufactured is about 1 ci, but a semiconductor element with a size of 1 to 500 cd can be manufactured. However, such area is not limited in the present invention.
以上のように構成された本実施例に係る半導体装置にお
いては光が第１図で示す矢符方向にそって進み第２図で
示す半導体装置におけるばあいと同様にして第１図で示
す各半導体層（３）、（４）、（５）、（６）に電子と
正孔の対が生じｐ層側電極（２）に正、ｎ層側電極（７
′）に負の電荷が生じる。そして本実施例においてはｐ
層側電極（２）が高濃度ｐＩＪ！！半導体層（３）と接
触しているためにこれらの間の接触抵抗が著しく低下す
るとともに高濃度ｐ型半導体層（３）の厚さが薄いため
これによる不純物部分での光の吸収損失は大きくならな
い。In the semiconductor device according to this embodiment configured as described above, light travels along the direction of the arrow shown in FIG. Pairs of electrons and holes are generated in the semiconductor layers (3), (4), (5), and (6);
′) a negative charge is generated. In this example, p
Layer side electrode (2) has high concentration pIJ! ! Since it is in contact with the semiconductor layer (3), the contact resistance between them is significantly reduced, and since the high concentration p-type semiconductor layer (3) is thin, the absorption loss of light in the impurity portion is large. No.
比較例１
前記実施例１における半導体装置おいて、高濃度ｐ型半
導体層（３）に代えてｐ型半導体層（４）と同材質の半
導体を１００人の厚さで前記実施例１のｐ型半導体層（
４）の形成方法と同様の方法で形成した以外は前記実施
例と同様にして作製した半導体装置を比較例１の半導体
装置とした。前記実施例１および比較例１に係る半導体
装置について １００ｍＷ／ｃ−のソーラーシミュレー
ターとして出力電圧−電流特性を測定した。その結果が
第３図に示されている。Comparative Example 1 In the semiconductor device of Example 1, a semiconductor made of the same material as the p-type semiconductor layer (4) was used in place of the high concentration p-type semiconductor layer (3) at a thickness of 100 mm. type semiconductor layer (
A semiconductor device of Comparative Example 1 was a semiconductor device manufactured in the same manner as in the above example except that it was formed by the same method as the formation method of 4). The output voltage-current characteristics of the semiconductor devices according to Example 1 and Comparative Example 1 were measured using a 100 mW/c solar simulator. The results are shown in FIG.
第３図に基づいて、
短絡電流×開放電圧
により曲線因子を計算すると、比較例１については曲線
因子が８０％程度であるのに対し実施例１については曲
線因子が７０％程度であった。Based on FIG. 3, when the fill factor was calculated by short circuit current x open circuit voltage, the fill factor for Comparative Example 1 was about 80%, whereas the fill factor for Example 1 was about 70%.
なお前記実施例１おいてはｐ層側電極（２）とｐ型半導
体層（４）の間に高濃度ｐ型半導体層（３）を設けたば
あいについて示したが、これはｎ型半導体層（６）とｎ
層側電極（７）の間に高濃度ｎ型半導体層を設けたもの
であってもよい。In Example 1, the case where the high concentration p-type semiconductor layer (3) is provided between the p-layer side electrode (2) and the p-type semiconductor layer (4) is shown, but this is not an n-type semiconductor layer. Layer (6) and n
A highly doped n-type semiconductor layer may be provided between the layer side electrodes (7).
また前記実施例１おいてはｐ層側電極（２）側から光が
入るように構成したがこれはｎ層側電極（７）を透明電
極としここから光が入るように構成してもよい。Furthermore, in the first embodiment, the light enters from the p-layer side electrode (2) side, but the structure may be such that the n-layer side electrode (7) is a transparent electrode and the light enters from there. .
また前記実施例１おいてはｐ型半導体層（４）、ｎ型半
導体層（５）およびｎ型半導体層（６）を各々１層づつ
設けたばあいについて示したがこれは第１図下方からｐ
層ｉ層ｎ層ｐ層ｉ層ｎ層・・・・・・の順に６〜１５層
積層したものであってもよく、また第１図下方からｎ層
ｉ Ｊｉ！Ｉｐ層またはｎ層ｉ層ｐ層ｎ層ｉ層ｐ層・・
・・・・のように積層してもよいことはもちろんである
。Furthermore, in the first embodiment, the case where one layer each of the p-type semiconductor layer (4), the n-type semiconductor layer (5), and the n-type semiconductor layer (6) are provided is shown, but this is shown in the lower part of FIG. From p
It may be a layer laminated in the order of 6 to 15 layers: i-layer, n-layer, p-layer, i-layer, n-layer, etc., and the n-layer i Ji! from the bottom in FIG. Ip layer or n layer i layer p layer n layer i layer p layer...
It goes without saying that they may be laminated as shown in the following.
また前記実施例１においては透明電極の材料として５ｎ
０２を使用したばあいについて示したがこれはＩＴＯな
ど他のものであってもよく、またｎ層側電極（７）の材
料としてＡｇを使用したがこれはＭＳＡｕなどの他の導
電性金属またはシリコンと他の金属の化合物であるシリ
サイドなどの導体またはこれらを積層したようなもので
あってもよい。In addition, in Example 1, 5n was used as the material for the transparent electrode.
02 is shown, but it may be made of other materials such as ITO. Also, although Ag was used as the material for the n-layer side electrode (7), it may be made of other conductive metals such as MSAu or It may also be a conductor such as silicide, which is a compound of silicon and other metals, or a laminate of these.
また前記実施例１においては高濃度ｐ型半導体層（３）
がｐ型半導体層（４）と同一材料であるばあいを示した
が、これは同じｐ型のものであれば前記実施例で使用さ
れた真性半導体（ＳＩＣ：Ｈ）と異なる半導体（例えば
Ｓｌ：１１）を使用しこれに前記実施例で使用された不
純物（ホウ素）または他の不純物を入れたものであって
もよく、また前記高濃度ｐ型半導体層（３）とｐ型半導
体層（４）の不純物のみが異なるものにしてもよいこと
はもちろんである。そしてこれは高濃度ｎ型半導体層と
ｎ型半導体層との関係においても同様である。Furthermore, in the first embodiment, the high concentration p-type semiconductor layer (3)
The case is shown in which the material is the same as that of the p-type semiconductor layer (4), but if it is of the same p-type, it may be made of a semiconductor different from the intrinsic semiconductor (SIC:H) used in the previous example (for example, Sl :11) and may contain the impurity (boron) used in the above embodiment or other impurities, or the high concentration p-type semiconductor layer (3) and the p-type semiconductor layer Of course, only the impurity in 4) may be different. This also applies to the relationship between the high concentration n-type semiconductor layer and the n-type semiconductor layer.
また前記実施例１においてはｐ型半導体層（４）から高
濃度ｐ型半導体層（３）へ不純物濃度が不連続的に変化
するばあいについて示したがこれはｐ型（またはｎ型）
半導体層から高濃度ｐ型（またはｎ型）半導体層へ不純
物濃度が連続的にしだいに増加していくようなものであ
ってもよい。Further, in the first embodiment, the case where the impurity concentration changes discontinuously from the p-type semiconductor layer (4) to the high concentration p-type semiconductor layer (3) is shown, but this is not a p-type (or n-type).
The impurity concentration may gradually increase continuously from the semiconductor layer to the high concentration p-type (or n-type) semiconductor layer.
また前記実施例１においては半導体装置の各層の作製方
法としてスパッタ法、真空蒸着法、プラズマＣＶＤ法な
どが使用されているがこれらに限定されるものではなく
薄層を形成できる方法であればよい。また使用される各
種ＣＶＤ装置としでは平行平板容量結合型プラズマＣＶ
Ｄ装置、導結合型プラズマＣＶＤ装置、熱ＣＶＤ装置、
ＥＣＲプラズマＣＶＤ装置、光ＣＶＤ装置、励起種ＣＶ
Ｄ装置などがある。Further, in the first embodiment, sputtering, vacuum evaporation, plasma CVD, etc. are used as methods for manufacturing each layer of the semiconductor device, but the method is not limited to these, and any method that can form a thin layer may be used. . In addition, various types of CVD equipment used include parallel plate capacitively coupled plasma CVD.
D device, conductively coupled plasma CVD device, thermal CVD device,
ECR plasma CVD equipment, optical CVD equipment, excited species CV
There are devices such as D.
また各層の形成に使用される原料についても前記実施例
のものに限定される必要はない。Furthermore, the raw materials used for forming each layer are not limited to those of the above embodiments.
［発明の効果］
以上のように本発明に係る半導体装置はｐ型半導体層と
ｐ層側電極との間および／またはｎ型半導体層とｎ層側
電極との間に各々前記ｐ型半導体層と同じ導電型であり
かつ不純物濃度が高い高濃度ｐ型半導体層および／また
は前記ｎ型半導体層と同じ導電型でありかつ不純物濃度
が高い高濃度ｎ型半導体層を介装しているのでｐ型半導
体層とｐ層側電極との間および／またはｎ型半導体層と
ｎ層側電極との間の接触抵抗を小さくできるとともに半
導体層における光の吸収損失が大きくならないようにで
き、従来の半導体装置と比較して光電変換効率を向上で
きる効果がある。[Effects of the Invention] As described above, the semiconductor device according to the present invention has the p-type semiconductor layer between the p-type semiconductor layer and the p-layer side electrode and/or between the n-type semiconductor layer and the n-layer side electrode. A high concentration p-type semiconductor layer having the same conductivity type and high impurity concentration as the n-type semiconductor layer and/or a high concentration n-type semiconductor layer having the same conductivity type and high impurity concentration as the n-type semiconductor layer is interposed. It is possible to reduce the contact resistance between the type semiconductor layer and the p-layer side electrode and/or between the n-type semiconductor layer and the n-layer side electrode, and also to prevent the light absorption loss in the semiconductor layer from increasing, which is different from conventional semiconductors. This has the effect of improving photoelectric conversion efficiency compared to other devices.
第１図は本発明の実施例１に係る半導体装置の断面図、
第２図は従来の半導体装置の断面図、第３図は本発明の
実施例１および比較例１に係る半導体装置の出力電圧−
電流特性を示す図である。
（図面の主要符号）
（２）：ｐ層側電極
（３）：高濃度ｐ型半導体層
（４） ： ｐ型半導体層
（５）、ｉ型半導体層
（６） ： ｎ型半導体層
（７）、ｎ層側電極
（８）二層導体装置
特許出願人 鐘淵化学工業株式会社
代理人弁理士 朝日奈宗太 ほか１名１ｒ−’、’、
・：Ｆ：、ｉ、ｂ、！−ユ：
才１ 図FIG. 1 is a cross-sectional view of a semiconductor device according to Embodiment 1 of the present invention;
FIG. 2 is a sectional view of a conventional semiconductor device, and FIG. 3 is an output voltage of semiconductor devices according to Example 1 of the present invention and Comparative Example 1.
FIG. 3 is a diagram showing current characteristics. (Main symbols in the drawing) (2): P-layer side electrode (3): High concentration p-type semiconductor layer (4): P-type semiconductor layer (5), i-type semiconductor layer (6): N-type semiconductor layer (7) ), N-layer side electrode (8) Double-layer conductor device Patent applicant Kanebuchi Chemical Industry Co., Ltd. Patent attorney Sota Asahina and one other person 1r-', ',
・:F:,i,b,! -Yu: Sai1 figure
Claims (1)
該半導体中のｐ型半導体層に接続されたｐ層側電極と前
記半導体中のｎ型半導体層に接続されたｎ層側電極とが
設けられた半導体装置においてｐ型半導体層とｐ層側電
極との間および／またはｎ型半導体層とｎ層側電極との
間に各々前記ｐ型半導体層と同じ導電型でありかつ不純
物濃度が高い高濃度ｐ型半導体層および／または前記ｎ
型半導体層と同じ導電型でありかつ不純物濃度が高い高
濃度ｎ型半導体層を介装している半導体装置。 ２ 前記高濃度ｐ型半導体層および高濃度ｎ型半導体層
の厚さが各々１０〜３００Åである特許請求の範囲第１
項記載の半導体装置。 ３ 前記ｐ型半導体層および／またはｎ型半導体層がα
−ＳｉＣ：Ｈに不純物をドーピングした半導体からなる
特許請求の範囲第１項または第２項記載の半導体装置。 ４ 前記ｐ型半導体層および／またはｎ型半導体層がα
−Ｓｉに不純物をドーピングした半導体からなる特許請
求の範囲第１項または第２項記載の半導体装置。 ５ 前記高濃度ｐ型半導体層および高濃度ｎ型半導体層
の不純物濃度が各々前記ｐ型半導体層およびｎ型半導体
層の不純物濃度の２倍以上である特許請求の範囲第１項
、第２項、第３項または第４項記載の半導体装置。 ６ 前記高濃度ｐ型半導体層および高濃度ｎ型半導体層
の不純物濃度が各々前記ｐ型半導体層およびｎ型半導体
層の不純物濃度の４倍以上である特許請求の範囲第５項
記載の半導体装置。[Claims] 1. A semiconductor containing nip type or pin type amorphous;
A p-type semiconductor layer and a p-layer side electrode in a semiconductor device provided with a p-layer side electrode connected to a p-type semiconductor layer in the semiconductor and an n-layer side electrode connected to an n-type semiconductor layer in the semiconductor. and/or between the n-type semiconductor layer and the n-layer side electrode, a high-concentration p-type semiconductor layer having the same conductivity type as the p-type semiconductor layer and having a high impurity concentration, and/or the n-type semiconductor layer and/or the n-layer side electrode.
A semiconductor device in which a high-concentration n-type semiconductor layer having the same conductivity type as a type semiconductor layer and having a high impurity concentration is interposed. 2. Claim 1, wherein the high concentration p-type semiconductor layer and the high concentration n-type semiconductor layer each have a thickness of 10 to 300 Å.
1. Semiconductor device described in Section 1. 3 The p-type semiconductor layer and/or the n-type semiconductor layer is α
3. The semiconductor device according to claim 1 or 2, comprising a semiconductor in which -SiC:H is doped with an impurity. 4 The p-type semiconductor layer and/or the n-type semiconductor layer is α
3. A semiconductor device according to claim 1 or 2, comprising a semiconductor in which -Si is doped with an impurity. 5. Claims 1 and 2, wherein the impurity concentration of the high concentration p-type semiconductor layer and the high concentration n-type semiconductor layer is twice or more the impurity concentration of the p-type semiconductor layer and the n-type semiconductor layer, respectively. , the semiconductor device according to item 3 or 4. 6. The semiconductor device according to claim 5, wherein the impurity concentration of the high concentration p-type semiconductor layer and the high concentration n-type semiconductor layer is four times or more the impurity concentration of the p-type semiconductor layer and the n-type semiconductor layer, respectively. .
Priority Applications (13)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP61099939A JPS62256481A (en) | 1986-04-30 | 1986-04-30 | Semiconductor device |
| CA000521602A CA1321660C (en) | 1985-11-05 | 1986-10-28 | Amorphous-containing semiconductor device with high resistivity interlayer or with highly doped interlayer |
| AU64619/86A AU600453B2 (en) | 1985-11-05 | 1986-10-31 | Semiconductor device |
| DE3650012T DE3650012T2 (en) | 1985-11-05 | 1986-11-01 | Semiconductor device. |
| EP86115170A EP0221523B1 (en) | 1985-11-05 | 1986-11-01 | Semiconductor device |
| EP92104628A EP0494088B1 (en) | 1985-11-05 | 1986-11-01 | Photovoltaic device |
| DE3650712T DE3650712T2 (en) | 1985-11-05 | 1986-11-01 | Photovoltaic device |
| EP19920104633 EP0494090A3 (en) | 1985-11-05 | 1986-11-01 | Photovoltaic device |
| CN86106353A CN1036817C (en) | 1985-11-05 | 1986-11-05 | Semiconductor device |
| KR860009364A KR870005477A (en) | 1985-11-05 | 1986-11-05 | Semiconductor devices |
| CN89104797A CN1018310B (en) | 1985-11-05 | 1989-07-14 | Semiconductor device |
| US07/477,138 US5032884A (en) | 1985-11-05 | 1990-02-07 | Semiconductor pin device with interlayer or dopant gradient |
| AU65966/90A AU636677B2 (en) | 1985-11-05 | 1990-11-09 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP61099939A JPS62256481A (en) | 1986-04-30 | 1986-04-30 | Semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS62256481A true JPS62256481A (en) | 1987-11-09 |
Family
ID=14260685
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP61099939A Pending JPS62256481A (en) | 1985-11-05 | 1986-04-30 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS62256481A (en) |
Cited By (6)
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|---|---|---|---|---|
| JPH0296380A (en) * | 1988-09-30 | 1990-04-09 | Kanegafuchi Chem Ind Co Ltd | Semiconductor device |
| JPH0296382A (en) * | 1988-09-30 | 1990-04-09 | Kanegafuchi Chem Ind Co Ltd | Semiconductor device |
| JPH02164079A (en) * | 1988-12-19 | 1990-06-25 | Hitachi Ltd | Amorphous silicon solar cell |
| JPH03155680A (en) * | 1989-08-25 | 1991-07-03 | Fuji Electric Corp Res & Dev Ltd | Manufacture of thin film solar cell |
| JP2002083984A (en) * | 2000-09-08 | 2002-03-22 | National Institute Of Advanced Industrial & Technology | Solar battery and its manufacturing method |
| JP2012134541A (en) * | 2009-02-17 | 2012-07-12 | Korea Inst Of Industrial Technology | Solar cell manufacturing method making use of inductive coupling plasma chemical vapor deposition method |
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| JPS55162275A (en) * | 1979-06-04 | 1980-12-17 | Konishiroku Photo Ind Co Ltd | Manufacture of solar battery |
| JPS5996775A (en) * | 1982-11-25 | 1984-06-04 | Agency Of Ind Science & Technol | Amorphous silicon photoelectric conversion device |
| JPS59163876A (en) * | 1983-03-08 | 1984-09-14 | Agency Of Ind Science & Technol | Amorphous silicon solar cell |
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| JPS55162275A (en) * | 1979-06-04 | 1980-12-17 | Konishiroku Photo Ind Co Ltd | Manufacture of solar battery |
| JPS5996775A (en) * | 1982-11-25 | 1984-06-04 | Agency Of Ind Science & Technol | Amorphous silicon photoelectric conversion device |
| JPS59163876A (en) * | 1983-03-08 | 1984-09-14 | Agency Of Ind Science & Technol | Amorphous silicon solar cell |
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0296380A (en) * | 1988-09-30 | 1990-04-09 | Kanegafuchi Chem Ind Co Ltd | Semiconductor device |
| JPH0296382A (en) * | 1988-09-30 | 1990-04-09 | Kanegafuchi Chem Ind Co Ltd | Semiconductor device |
| JPH02164079A (en) * | 1988-12-19 | 1990-06-25 | Hitachi Ltd | Amorphous silicon solar cell |
| JPH03155680A (en) * | 1989-08-25 | 1991-07-03 | Fuji Electric Corp Res & Dev Ltd | Manufacture of thin film solar cell |
| JP2002083984A (en) * | 2000-09-08 | 2002-03-22 | National Institute Of Advanced Industrial & Technology | Solar battery and its manufacturing method |
| JP2012134541A (en) * | 2009-02-17 | 2012-07-12 | Korea Inst Of Industrial Technology | Solar cell manufacturing method making use of inductive coupling plasma chemical vapor deposition method |
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