JPH0594384A - Bus monitor circuit for information processor - Google Patents

Abstract

PURPOSE:To easily obtain information required for investigating the cause of occurring a fault and to execute a countermeasure against the fault in a short time. CONSTITUTION:When the fault is detected at an input/output bus B2 by a fault detection circuit D3, data turning a bit corresponding to the fault to '1' are outputted. A register R5 holds data turning the bit corresponding to the fault to the '1' to output a stop signal to a memory control circuit M7, and an AND circuit A8 ANDs the data from the detection circuit D3 and the data from the register R5 for each bit. When there is only one pair of bits establishing the AND, an OR circuit 09 outputs the stop signal to the control circuit M7. The memory control circuit M7 always fetches an address, data and control signal from the bus B2 and stores them and when the stop signal is inputted, however, the circuit M7 stops fetching signals and holds an information processor fetched from the input/output bus B2 during a fixed period before the generation of the fault.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a bus monitoring circuit of an information processing device.

[0002]

2. Description of the Related Art A conventional bus monitoring circuit of this type has been designed to report the occurrence of a failure on a bus to a central processing unit by means of an interrupt. Further, the bus monitoring circuit holds information indicating the type of fault that has occurred in a predetermined register, and the central processing unit recognizes the type of fault that has occurred by reading the contents of that register. It was

[0003]

However, such a conventional bus monitoring circuit does not hold information such as the ID of a device that has caused a bus failure and the type of access by that device, and the bus monitoring circuit before the failure occurs. ID of the device that accessed the
It also does not hold information such as access type. That is, the conventional bus monitoring circuit cannot obtain the above-mentioned ID and information necessary for investigating the cause of the failure occurrence. Therefore, in order to investigate the cause, an external measuring device is connected and the bus It was necessary to prepare a monitoring environment and reproduce the failure to obtain detailed information about the bus failure. Further, since it is difficult to reproduce a failure in a device that is in operation, it is necessary to separately prepare a device for reproducing a failure. Therefore, it took a long time to take countermeasures after a failure occurs. In addition, it is often difficult to reproduce the failure, and in such a case, it was impossible to take measures.

An object of the present invention is to solve the above problems, to easily obtain the information necessary for investigating the cause of a failure, and to take countermeasures in a short time.

[0005]

A bus monitoring circuit of an information processing apparatus according to the present invention includes a failure detection circuit for detecting a failure of a bus and a signal transmitted through the bus, which is fetched and stored at any time, and a stop signal is given. When the fault detection circuit detects a fault in the bus, the memory stops the approach of the signal from the bus, and the trace control circuit outputs the stop signal to the memory when the fault detection circuit detects the fault in the bus. And a first register for holding information indicating the detected failure.

[0006]

Embodiments of the present invention will now be described with reference to the drawings. FIG. 1 shows an example of a bus monitoring circuit of an information processing device according to the present invention. The fault detection circuit D3 is the input / output bus B2
When a failure occurs, the failure is detected and the failure detection data indicating the type of the failure is output. The detection circuit D3 detects a maximum of 32 types of failures. The fault detection data output by the detection circuit D3 is 32-bit data, and each bit of the data corresponds to the fault type. Then, the detection circuit D3 sets the bit corresponding to the detected fault to logic "1".

The error register R4 is a 32-bit register, receives fault detection data from the fault detection circuit D3, and holds it. A central processing unit (not shown) can read the contents of this register R4 through the memory bus B1 and vice versa. The stop condition register R5 is a 32-bit register, and data is written by the central processing unit through the memory bus B1. Each bit of the data corresponds to the type of bus failure, like the data output by the failure detection circuit D3.

The AND circuit A8 calculates the bitwise logical product of the fault detection data from the fault detection circuit D3 and the data held in the register R5, and outputs the result to each of the 32 signal lines. The stop register R6 is an AND circuit A8.
The 32-bit data output by the CPU can be fetched and held, and the central processing unit can read the data through the memory bus B1. The OR circuit O9 is a 32-input OR circuit, which obtains a 32-bit data logical sum from the AND circuit A8 and outputs the result as a stop signal.

The memory control circuit M7 fetches and stores addresses, data, and control signals from the input / output bus B2 at any time and stores them. When a stop signal is given, the bus B2 is used.
Stop capturing signals from. The central processing unit can read the contents of the memory control circuit M7 through the memory bus B1. The memory control circuit M7 initializes the address and overwrites the newly fetched signal from the address 0 when the signal is written in the entire storage area.

Next, the operation will be described. The central processing unit first writes all "0" data to the register R4,
initialize. In addition, the register R5 is written with data indicating which kind of failure has caused the memory control circuit M7 to stop writing data. For example, when there are a plurality of faults for which writing should be stopped, data in which each bit corresponding to the plurality of faults is a logical "1" is written.

When a failure occurs in the input / output bus B2 in this state and the failure detection circuit D3 detects it, the failure detection data in which the bit corresponding to the failure is set to logic "1" is output. The register R4 receives and holds the data, while the AND circuit A8 obtains a bitwise logical product of the fault detection data from the fault detection circuit D3 and the data held by the register R5, and the result is a 32-bit result. Output as data. Then, the OR circuit O9
The logic wheel of each bit of the 2-bit data is obtained, and if even one bit of logic "1" is included, the signal of logic "1" is output to the memory control circuit M7 as a stop signal. The data output from the AND circuit A8 is held in the register R6.

The memory control circuit M7 always fetches and stores the address, data, and control signal from the input / output bus, but when the stop signal is inputted from the OR circuit O9, the fetching of the signal is stopped. As a result, the information transmitted through the input / output bus B2 is held in the memory control circuit M7 during a certain period before the bus failure occurs.

Therefore, in the bus monitoring circuit of this embodiment, the data held in the registers R4 and R6 is stored in the memory bus B1.
It is possible to know what kind of failure has occurred by reading through the memory B. Further, by reading the information held in the memory control circuit M7 through the memory address B1, the bus B2 is transmitted during a certain period before the occurrence of the failure. It is possible to know the address, data, and control signal.

[0014]

As described above, the bus monitoring circuit of the information processing apparatus according to the present invention incorporates a fault detection circuit for detecting a fault in the bus and a signal transmitted through the bus, stores and stores the signal at any time, and outputs a stop signal. Is given, a memory that stops capturing signals from the bus, a trace control circuit that outputs a stop signal to the memory when the fault detection circuit detects a fault in the bus, and a fault detection circuit And a first register that holds information indicating a failure. Therefore, in the bus monitoring circuit of the information processing apparatus according to the present invention, the signal transmitted through the bus is stored in the memory during a certain period before the occurrence of a failure. It is possible to know whether the cause of the failure occurred. Further, the type of fault that has occurred can be known from the information held in the first register. Therefore, it is not necessary to connect a measuring device to reproduce the fault and acquire information about the bus fault as in the conventional case, and it is not necessary to separately prepare a device for fault reproduction. As a result, it becomes possible to take measures against the failure within a short time. Furthermore, since necessary information can be obtained even for a failure that has occurred only once in the operating device, it is possible to take countermeasures.

[Brief description of drawings]

FIG. 1 is a block diagram showing an example of a bus monitoring circuit of an information processing device according to the present invention.

[Explanation of symbols]

 A8 AND circuit B1 Memory bus B2 I / O bus D3 Fault detection circuit M7 Memory control circuit O9 OR circuit R4 Error register R5 Stop condition register R6 Stop register

Claims (3)

[Claims] 1. A fault detection circuit for detecting a fault in a bus, and a memory for fetching and storing a signal transmitted through the bus at any time and stopping the approach of the signal from the bus when a stop signal is given. A trace control circuit that outputs the stop signal to the memory when the fault detection circuit detects a bus fault; and a first register that holds information indicating the fault detected by the fault detection circuit. A bus monitoring circuit of an information processing device, which is provided. 2. The trace control circuit includes a second register that holds information indicating one or more specific bus faults, and the fault detected by the fault detection circuit is stored in the second register. Signal generation means for outputting the stop signal when included in the fault represented by the held information, wherein the first register is the second one of the faults detected by the fault detection circuit. Holding information on a failure included in the failure represented by the information held in the register
2. The bus monitoring circuit for an information processing apparatus according to claim 1, further comprising: 3. The bus monitoring circuit for an information processing apparatus according to claim 1, wherein the bus is an input / output bus.