JPS6397146U - - Google Patents
Info
- Publication number
- JPS6397146U JPS6397146U JP19276786U JP19276786U JPS6397146U JP S6397146 U JPS6397146 U JP S6397146U JP 19276786 U JP19276786 U JP 19276786U JP 19276786 U JP19276786 U JP 19276786U JP S6397146 U JPS6397146 U JP S6397146U
- Authority
- JP
- Japan
- Prior art keywords
- bus
- signals
- ram
- monitor device
- system bus
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000010586 diagram Methods 0.000 description 4
Landscapes
- Debugging And Monitoring (AREA)
Description
第１図はこの考案の一実施例を示すブロツク図
、第２図はバスモニタ装置本体の内部構成を示す
回路図、第３図はコンソールＣＲＴの一表示例を
示す図、第４図は従来のバスモニタ装置の構成を
示すブロツク図である。
１……主記憶装置、２……ＣＲＴ、３……チヤ
ネル、４……バスモニタ装置本体、５……ＳＶＰ
、６……ＣＲＴ、７……システムバス、８……バ
ス、２１……ＲＡＭ、２２……制御回路。尚、図
中同一符号は同一又は相当部分を示す。
Fig. 1 is a block diagram showing an embodiment of this invention, Fig. 2 is a circuit diagram showing the internal configuration of the main body of the bus monitor device, Fig. 3 is a diagram showing an example of a display on a console CRT, and Fig. 4 is a conventional one. FIG. 2 is a block diagram showing the configuration of a bus monitor device according to the present invention. 1... Main memory device, 2... CRT, 3... Channel, 4... Bus monitor device body, 5... SVP
, 6...CRT, 7...System bus, 8...Bus, 21...RAM, 22...Control circuit. Note that the same reference numerals in the figures indicate the same or corresponding parts.
Claims (1)
タするバスモニタ装置において、 バスクロツク単位でサンプルしたシステムバス
上の信号を一時的に格納するためのＲＡＭと、こ
のＲＡＭの動作を制御する制御回路とを一枚のボ
ード上に構成したバスモニタ装置本体をシステム
バスに接続し、上記信号をバスクロツク順に上記
ＲＡＭのアドレス順にかつ最終アドレスから最初
のアドレスに戻るようにして順次かつ循環的にＲ
ＡＭに格納し、トリガ条件が発生した場合これ以
降の信号の格納を中止し、それまでに上記ＲＡＭ
に格納されたシステムバス上の信号状態をこの計
算機システムに付属するＳＶＰ（サービスプロセ
ツサ）により編集してＣＲＴ上に表示することを
特徴とするバスモニタ装置。[Claim for Utility Model Registration] A bus monitor device that monitors signals on a system bus of a computer system includes a RAM for temporarily storing signals on the system bus sampled in bus clock units, and a RAM for temporarily storing signals on the system bus that are sampled in bus clock units. The main body of the bus monitor device, which has a control circuit and a control circuit configured on one board, is connected to the system bus, and the above signals are sequentially and cyclically sent in the order of the bus clock, in the order of the addresses of the RAM, and from the last address to the first address. R
AM, and if a trigger condition occurs, the storage of subsequent signals will be stopped, and the above RAM will be stored by then.
A bus monitor device that edits signal states on a system bus stored in a computer system by an SVP (service processor) attached to the computer system and displays the edited signals on a CRT.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP19276786U JPS6397146U (en) | 1986-12-15 | 1986-12-15 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP19276786U JPS6397146U (en) | 1986-12-15 | 1986-12-15 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS6397146U true JPS6397146U (en) | 1988-06-23 |
Family
ID=31148161
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP19276786U Pending JPS6397146U (en) | 1986-12-15 | 1986-12-15 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6397146U (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0594384A (en) * | 1991-10-01 | 1993-04-16 | Nec Corp | Bus monitor circuit for information processor |
-
1986
- 1986-12-15 JP JP19276786U patent/JPS6397146U/ja active Pending
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0594384A (en) * | 1991-10-01 | 1993-04-16 | Nec Corp | Bus monitor circuit for information processor |
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