JPS60108946A - Bus monitoring device - Google Patents

Abstract

PURPOSE:To make the change of a program and the spare of an analog output unnecessary and to monitor optional data ccessed by a CPU by utilizing the bus access timing of the CPU to monitor the contents accessed by the CPU. CONSTITUTION:A bus monitoring device 5 is connected to a bus B connected to the CPU1 and data from the CPU1 are inputted to the device 5 and outputted as an analog data to a data decoder 4. An interface 5b in the device 5 reads data from the bus B and separates the bus B from the main body 5a of the device 5. Conversion gain to memory data stored in an address necessary for monitoring and the output terminal number of the data are inputted from an operation panel 6 to a converting circuit 7. A detecting circuit 8 detects the coincidence of the set address with an address from the bus 5 and the data from the bus 5 are stored in a storage circuit on the basis of a coincidence detecting signal from the circuit 8. The conversion circuit 7 controls respective parts and the output of the conversion circuit 7 is converted into an analog value by a D/A conversion circuit 10 to output the analog signal.

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to a bus monitor device that monitors data when a central processing unit (CPU) accesses a node.

[Prior art]

2. Description of the Related Art Conventionally, there has been a device shown in FIG. 1 as a device for monitoring in real time the contents of a memory specified by an address accessed by a CPU.

In FIG. 1, reference numeral 1 indicates a central processing unit (CPU);
2 is a program memory that stores a program to control the CPU 1; 3 is an analog output section (card) that converts data output by the CPU 1 into an analog signal; 4 is a data recorder that records the analog signal from the analog output section 3; B is a bus that transfers addresses and data.

Next, the operation will be explained using FIG. Data at an address in a memory (not shown) that the CPU 1 is accessing is monitored by being output to the data recorder 4 via the bus B and the analog output section 3. A monitor program for realizing this is stored in the program memory 2. Similarly, when displaying multiple partial pressures at the same time, the monitor program corresponding to the number of partial pressures is stored in the program memory 2.
will be added to.

In order to store such a monitor program in the program memory 2, K needs to temporarily stop the original processing being executed by the CPU and add the program. However, if the CPUI is running continuously online, the C
It may not be permissible to stop the PUI, and it is also impossible if the analog output section 3 does not have a spare monitor output.

Furthermore, when the number of data points to be monitored, that is, the number of monitor points is increased, there is also a drawback that the monitoring program cannot adapt to the sampling time of data by the original processing.

[Summary of the Invention] The present invention has been made in order to eliminate the drawbacks of such conventional devices. The purpose is to provide a monitoring device.

[Explanation of Examples]

Embodiments of the present invention will be described below with reference to the drawings.

In FIG. 2, reference numeral 5 denotes a bus monitor device according to the present invention that takes in data at the CPUI address via bus B based on the bus access signal of CPU 1, and outputs it in analog form to data recorder 4, as shown in FIG. It has a configuration like this. In FIG. 3, 5a is a main body of a bus monitor device 50 that takes in data specified by an address and performs analog conversion, and 5b reads addresses and data required by the main body 5a from a bus B, and connects the bus B and the main body 5a. This is an interface for separating the two. 6
In the interface 5a, 7 is an operation panel having keys for setting data necessary for the monitor and a display for displaying the set data, and 7 is for controlling the operation panel 6, managing the main body 5a, and converting coefficients of monitored data. A processing circuit 8 has n columns of registers for storing addresses, and also compares the address specified by the operation panel 6 with the address on bus B, and generates an address match signal when a match is obtained. 9 is a storage circuit that stores the data on the bus B output from the CPU 1 in response to the address match signal output from the detection circuit 8, and stores the bit instruction when the designated address has a bit instruction. , 10 is a digital-to-analog conversion circuit for analog-converting data held after coefficient conversion by the processing circuit 7, and has a plurality of output terminals designated by numbers.

Next, the operation will be explained using FIG. The address to be monitored, the conversion gain for data in a memory (not shown) stored at that address, and the number of the output terminal for that data are input to the processing circuit 71C via the operation panel 6. The input address is transferred to the detection circuit 8 and stored in the register in column i corresponding to the number of the output terminal that should output data, and the conversion gain between the output terminal number and the data is transferred to the processing circuit 7. be remembered. Further, if there is a seven bit instruction among the data to be monitored, the bit extraction is transferred to the storage circuit 9 and stored.

Next, when the detection circuit 8 detects a match between the contents of the i-column register and the address from the interface 5b, it outputs an address match signal corresponding to the i-column.

Word? Storage circuit 9 stores the data on bus B in the memory location specified by this address match signal. The processing circuit T reads data from the storage circuit 9, performs data conversion based on the data conversion gain stored for each output terminal number, and stores it in its internal register corresponding to the output terminal number.

“1” if the data is bit-extracted
Or convert it into a value corresponding to '0' and store it in the internal register.The data stored in the internal register of the processing circuit 7 is as follows.
The signal is converted into an analog signal by the digital-to-analog conversion circuit 10 and supplied to the data recorder 4.

Nao, if the interface processing between the main body 5a and the bus B is for a specific CPU, the interface 5b may be removed. It is not necessary to provide an external CRT terminal or a system typewriter.It is also possible to include a register for storing data to be converted to analog in the digital-to-analog conversion circuit 10 instead of in the processing circuit 7. .

〔Effect of the invention〕

As described above, according to the present invention, since the content of the address accessed by the CPU is monitored using the CPU bus access timing, there is no need to change the program, and there is no need for a backup analog output. This has the effect of making it possible to monitor any data accessed by the CPU without affecting the sampling time of the program.

[Brief explanation of drawings]

FIG. 1 is a block diagram of a conventional bus monitor device, FIG. 2 is a block diagram of a bus monitor device according to an embodiment of the present invention, and FIG. 3 is a block diagram showing details of the bus monitor device shown in FIG. It is. 1...CPU, 2...Program memory, 6...
Operation panel, 7... Conversion circuit, 8-... Detection circuit, 9
...Memory circuit, 10...Digital-to-analog conversion circuit. In addition, in the figures, the same reference numerals indicate the same or equivalent parts. Patent applicant: Mitsubishi Electric Co., Ltd. Procedural amendment (voluntary) ↑, 1. Indication of the case: Japanese Patent Application No. 58-216352 2. Name of the invention: bus monitor device: 3. Representative of the person making the amendment Hitoshi Katayama Department 4, Agent Postal code: 105 Address: 1-4-10 Nishi-Shinbashi, Minato-ku, Tokyo Column for detailed explanation of the invention in the specification to be amended Details of the contents of the amendment as shown below correct.

Claims (1)

[Claims] An operation panel that specifies the address sent from the central processing unit, the conversion gain for the memory data accessed by this address, and the number of the output terminal that outputs this data, and the address sent by the central processing unit via the bus. and a detection circuit that detects a match between the address and the address set by the operation panel, and the data on the bus is recorded based on the address match signal output from this detection circuit.
a processing circuit that performs gain conversion processing of the data stored in the storage circuit using a set conversion gain and control of various parts including the operation panel and the storage circuit; A bus monitor device comprising a digital-to-analog conversion circuit that converts the data into an analog signal and outputs the signal from the output terminal of the number mentioned above.