JPH0590571A - Turn-off thyristor with insulating gate - Google Patents

Abstract

PURPOSE:To improve the turn-OFF power of a turn-OFF thyristor added with an insulating gate. CONSTITUTION:In a turn-OFF thyristor with an insulating gate, an N-channel MOSFET, which uses the surface of a P-type base layer 4 as a channel region, is formed on the side on one side of sides holding each gate electrode 8 between them and the layer 4 and a contact electrode 10 brought into contact to the layer 4 are arranged on the other side to oppose to the region of this MOSFET in a section formed with the MOSFET.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a turn-off thyristor with an insulated gate, and more particularly to a turn-off thyristor with an insulated gate for preventing local current concentration generated at turn-off.

[0002]

2. Description of the Related Art A thyristor with an insulated gate is a thyristor that turns on when a voltage is applied to a gate electrode thereof, and an n-type cathode / emitter layer and an n-type base layer are short-circuited by a MOSFET. Since this operation is voltage controlled, it requires only small gate power. However, this configuration alone does not allow self-turn-off. For this reason, a control electrode is provided on the p-type base layer, and a negative bias is applied to the control electrode to discharge a part of the anode current as a base current to the outside, so that the insulated gate is self-turned off. A turn-off thyristor with is proposed.

FIG. 8 is a sectional view showing a main structure of a thyristor with an insulated gate capable of self-turn-off. 1 is p
Type emitter layer, 2 is n ⁺ A type buffer layer, 3 is an n-type base layer, 4 is a p-type base layer, and 5 is an n-type emitter layer. p
An anode electrode 6 is ohmicly attached to the type emitter layer 1, and a cathode electrode 12 is ohmicly attached to the n type emitter layer 5. A gate insulating film 7 is formed on the surface of the p-type base layer 4 sandwiched between the n-type emitter layer 5 and the n-type base layer 3.
The gate electrode 8 is formed through the gate electrode 8 and the n-channel MOSFET for turn-on is constituted by this.

Reference numeral 10 is a control electrode which makes ohmic contact with the p-type base layer 4, and 11 is a p-type base layer 4 and the control electrode 1.
P ⁺ provided to reduce the contact resistance with 0 It is a mold layer. Reference numeral 9 is an insulating film that insulates the gate electrode 8 from the control electrode 10 and the cathode electrode 12, and 13 is an insulating film that separates the control electrode 10 from the cathode electrode 12.

FIG. 9 is a plan view showing a more specific conventional element structure, and FIG. 10 is a sectional view taken along the line AA 'of FIG.
1 shows the BB ′ cross section of FIG. 9, and FIG. 12 shows the CC ′ cross section of FIG. 9. In this device structure, the gate electrodes 8 are arranged in a stripe shape and covered with the first insulating film 9, and the first insulating film 9 is formed on the first insulating film 9 in a plurality of first regions between the gate electrodes 8.
The opening 15 is provided, and the control electrode 10 is connected to the p-type base layer 4 here. The control electrode 10 is the gate electrode 8
It is laid over the first insulating film 9. The control electrode 10 is covered with the second insulating film 13, and the second openings 14 are provided in the first insulating film 9 and the second insulating film 13 in the plurality of second regions between the gate electrodes 8. , Cathode electrode 12
Are connected to the n-type emitter layer 5 here. The cathode electrode 12 is formed over the entire element region.

The operation of this element is as follows. When a positive voltage is applied to the gate electrode 8, the n-type emitter layer 5 is short-circuited with the n-type base layer 3 via the channel formed on the surface of the p-type base layer 4 below the gate electrode 8. By this, n
Electrons are injected from the type emitter layer 5 into the n-type base layer 3. From the p-type emitter layer 1, an appropriate amount of holes are injected into the n-type base layer 3, and as a result, the thyristor is turned on.

When turning off the thyristor, a negative bias is applied to the control electrode 10. Then, a part of the anode current flowing through the n-type emitter layer 5 to the cathode electrode 12 is discharged from the control electrode 10 to the outside as a base current. As a result, the thyristor turns off.

The control electrode 10 can be used even when it is turned on. At the time of turn-on, if a positive voltage is applied to the gate electrode 8 and at the same time a positive voltage is applied to the control electrode 10 to send a base current to the p-type base layer 4,
Turn-on progresses from both sides of the n-type emitter layer 5, and the turn-on time can be shortened.

In the turn-off thyristor with an insulated gate shown in FIGS. 9 to 12, since the control electrode 10 is laid on the stripe-shaped gate electrode 8, the resistance of the control electrode 10 is reduced. High turn-off ability is obtained. Further, by alternately providing the contact position 15 of the control electrode 8 and the contact position 14 of the cathode electrode 12 which is the second main electrode in the longitudinal direction of the gate electrode 8, the effective energization area of the element is increased. A low on-voltage can be obtained.

However, in the conventional element as described above, in the rectangular n-type emitter regions, the control electrodes are formed adjacent to the opposite pair of opposite sides, but the other pair of opposite sides. Is an n-channel MOSFET for turn-on
Therefore, the base current cannot be efficiently drawn from the control electrode in the n-type emitter region in that portion. As a result, at the time of turn-off, there is a problem that the anode current concentrates on that portion and the element is destroyed.

[0011]

As described above, in the conventional turn-off thyristor with an insulated gate, when the thyristor is turned off, current concentration occurs in the portion of the n-type emitter region which constitutes the n-channel MOSFET, and the element is concentrated. There was a problem of destruction.

An object of the present invention is to solve such problems and to provide a turn-off thyristor with an insulated gate that realizes a high turn-off capability while maintaining excellent ON characteristics.

[0013]

A turn-off thyristor with an insulated gate according to the present invention has a second conductive type base layer in contact with a first conductive type emitter layer, and a second conductive type base layer having a second conductive type base layer on a surface thereof. A first conductivity type base layer and a second conductivity type emitter layer are diffused and formed, and a gate is formed on the surface of the first conductivity type base layer sandwiched between the second conductivity type emitter layer and the second conductivity type base layer via an insulating film. An electrode is provided, and a first main electrode is formed on the first conductivity type emitter layer, a second main electrode is formed on the second conductivity type emitter layer, and a control electrode is formed on the first conductivity type base layer. A turn-off thyristor,
Second conductive channel MOS on one side with the gate electrode sandwiched
In the cross section in which the FET is formed, the first conductive type base layer and the control electrode in contact with the first conductive type base layer are arranged on the other side facing the MOSFET region.

[0014]

In the device structure of the present invention, the turn-on second conductive channel MOSFE on one side of the gate electrode is sandwiched.
A first conductivity type base layer and a control electrode in contact with the first conductivity type base layer are disposed on the other side facing the region where T is formed.
In other words, the control electrode is connected to the first conductivity type base layer adjacent to any position around the second conductivity type emitter region. As a result, the base current is efficiently drawn at the time of turn-off, and a high turn-off ability is obtained.

In the structure of the present invention, by applying a negative bias to the gate electrode at the time of turn-off, the surface of the second conductivity type base layer immediately below the gate electrode sandwiched between the adjacent first conductivity type base layers is removed. First as channel region
Conducting the conductive channel MOSFET is also effective. As a result, the number of paths for drawing the base current can be effectively increased, and the turn-off capability can be improved.

[0016]

The details of the present invention will be described below with reference to the illustrated embodiments. In this embodiment, p is used as the first conductivity type layer.
Type and n-type are used as the second conductivity type.

FIG. 1 is a sectional view showing the element structure of one embodiment of the present invention. n ^{+ in contact} with the p-type emitter layer 1 The type buffer layer 2 and the n-type base layer 3 are formed on the type buffer layer 2.
The p-type base layer 4 is diffused and formed in the mold base layer 3. An n-type emitter layer 5 is selectively diffused in the p-type base layer 4 to form a pnpn structure.

The region between the n-type emitter layer 5 and the n-type base layer 3 of the p-type base layer 4 is used as a channel region.
A gate electrode 8 is formed on this via a gate insulating film 7 to form a turn-on n-channel MOSFET. The control electrode 10 is also directly connected to the p-type base layer 4. Between the control electrode 10 and the p-type base layer 4, p ⁺ The mold layer 11 is formed. An anode electrode (first main electrode) 6 is formed on the p-type emitter layer 1, and a cathode electrode (second main electrode) 12 is formed on the n-type emitter layer 5. In the p-type base layer 4 on the side facing the n-type emitter layer 5 with the gate electrode 8 interposed therebetween, p ⁺ A mold layer 11 and a control electrode 10 in contact with the mold layer 11 are formed.

The operation of this device is as follows. When a positive voltage is applied to the gate electrode 8, the n-type emitter layer 5 short-circuits the n-type emitter layer 5 and the n-type base layer 3 via the channel formed on the surface of the p-type base layer 4 below the gate electrode 8. Then, electrons are injected into the n-type base layer 3. From the p-type emitter layer 1, holes in an amount corresponding to the number of holes are n-type base layer 3
Injected into the thyristor, which turns on. By applying a positive voltage to the control electrode 10, the p-type base layer 4
The turn-on time can be shortened by sending the base current to the.

When the thyristor is turned off, a negative bias is applied to the control electrode 10. Then, n
A part of the anode current flowing through the mold emitter layer 5 to the cathode electrode 12 is discharged as a base current from the control electrode 10 to the outside, and as a result, the thyristor is turned off. At that time, from the n-type base layer 3 immediately below the gate electrode 8 to p near the channel of the turn-on n-channel MOSFET.
A part of the anode current flowing to the cathode electrode 12 through the n-type base layer 4 and the n-type emitter layer 5 is a p-type base layer formed at a position facing the n-type emitter layer 5 with the gate electrode 8 interposed therebetween. 4 and p ⁺ It passes through the mold layer 11 and is discharged to the outside from the control electrode 10 as a base current.

As a result, the anode current is drawn out to the control electrode 10 substantially uniformly over the entire circumference of the n-type emitter layer 5, and local current concentration on a part of the n-type emitter layer 5 at the time of turn-off is prevented. To be done. Therefore, the turn-off ability is improved as compared with the conventional device. Since the turn-on channel width is the same as that of the conventional device, the on-characteristic is not impaired.

Further, in this structure, by applying a negative bias to the gate electrode 8 at the time of turn-off, the surface of the n-type base layer 3 immediately below the gate electrode 8 sandwiched between the adjacent p-type base layers 4 is removed. Turn on the p-channel MOSFET used as the channel region to turn on the n-channel MO.
It is also possible to improve the turn-off capability by drawing the base current directly from the p-type base layer 4 near the channel of the SFET. FIG. 2 is a plan view of an embodiment in which the device structure of the present invention is further embodied, and FIGS. 3, 4, and 5 are cross-sectional views taken along lines AA ′, BB ′, and CC ′ of FIG. 2, respectively. ..
Arranging the gate electrodes 8 in a stripe shape, laying the control electrodes 10 on the gate electrodes 8 via the first insulating film 9, and contact positions 14 of the cathode electrodes 12.
The contact position 15 of the control electrode 10 with the gate electrode 8
It is the same as the conventional example that they are provided alternately in the longitudinal direction.

In this embodiment, p ⁺ is formed at a position facing the n-type emitter layer 5 with the gate electrode 8 interposed therebetween. The mold layer 11 is arranged so as to come. Accordingly, the gate electrode 8
A contact position 15 of the control electrode 10 is provided at a position facing the contact position 14 of the cathode electrode 12 with the electrode sandwiched therebetween. In other words, the arrangement of the n-type emitter layer 5 and the p-type base layer contact position 15 on one side of the striped gate electrode 8 and the n-type emitter layer 5 and the p-type base layer contact position on the other side. And the array of 15
It is out of alignment.

With this structure, no matter which cross section is taken in the direction crossing the gate electrode 8, the p-type base layer 4 has a p-type layer on the side facing the n-type emitter layer 5 with the gate electrode 8 interposed therebetween.
⁺ Thus, the mold layer 11 and the control electrode 10 in contact with it are formed. At the time of turn-off, part of the anode current flowing to the cathode electrode 12 through the p-type base layer 4 and the n-type emitter layer 5 near the channel of the turn-on n-channel MOSFET immediately below the gate electrode 8 sandwiches the gate electrode 8. And p ⁺ on the other side It is discharged to the outside as a base current through the mold layer 11 and the control electrode 10.

FIG. 6 shows a device structure of another embodiment of the present invention.
7 is a plan view, and FIG. 7 is a sectional view taken along line AA ′ of FIG.
The sectional view taken along the line BB ′ of FIG. 6 is similar to that of FIG. In this example
Is adjacent to the three sides around the n-type emitter layer 5, and p⁺ Type
A layer 11 and a control electrode 10 in contact therewith are arranged
It In the layout of FIG. 2 of the previous embodiment, this is
Omitting every other gate electrode 8, the n-type emitter layer 5
There is no turn-on channel for the three sides of
P⁺ The mold layer 11 and the control electrode 10 are adjacent to each other.
It This will further improve the turn-off ability.
Be done.

According to the above-described embodiments, the effective conduction area of the device, the wiring resistance of the control electrode, etc. are kept at the same level as those of the conventional device, and the vicinity of the channel of the turn-on n-channel MOSFET which is generated at turn-off. It is possible to prevent local current concentration on the n-type emitter layer and realize a high turn-off capability.

[0027]

As described above, according to the present invention, the turn-on second conductive channel MOS is sandwiched with the gate electrode interposed therebetween.
By forming the first conductivity type base layer and the control electrode in contact with the first conductivity type base layer on the side facing the FET, it is possible to realize a turn-off thyristor with an insulated gate having high turn-on and turn-off capabilities.

[Brief description of drawings]

FIG. 1 is a cross-sectional view showing a main element structure of a first embodiment of the present invention.

FIG. 2 is a plan view showing an element structure of a second specific example of the present invention.

FIG. 3 is a sectional view taken along the line AA ′ of FIG.

4 is a sectional view taken along line BB ′ of FIG.

5 is a cross-sectional view taken along the line CC ′ of FIG.

FIG. 6 is a plan view showing an element structure according to a third embodiment of the present invention.

7 is a cross-sectional view taken along the line AA ′ of FIG.

FIG. 8 is a sectional view showing an element structure of a conventional example.

FIG. 9 is a plan view showing an element structure of a conventional example.

10 is a cross-sectional view taken along the line AA ′ of FIG.

11 is a cross-sectional view taken along the line BB ′ of FIG.

FIG. 12 is a sectional view taken along line CC ′ of FIG.

[Explanation of symbols]

1 ... p-type emitter layer, 2 ... n ⁺ Type buffer layer, 3 ... N type base layer, 4 ... P type base layer, 5 ... N type emitter layer, 6 ... Anode electrode, 7 ... Gate insulating film, 8 ... Gate electrode, 9 ... First insulating film, 10 … Control electrode, 11… p ⁺ Mold layer, 12 ... Cathode electrode, 13 ... Second insulating film, 14, 15 ... Contact hole.

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Ichiro Omura 1 Komukai Toshiba-cho, Sachi-ku, Kawasaki City, Kanagawa Prefecture Toshiba Research Institute Co., Ltd.

Claims (1)

[Claims] 1. A first conductivity type base layer is provided in contact with the first conductivity type emitter layer, and a first conductivity type base layer and a second conductivity type emitter layer are diffused and formed on a surface portion of the second conductivity type base layer. And a gate electrode is provided on the surface of the first conductive type base layer sandwiched between the second conductive type emitter layer and the second conductive type base layer via an insulating film, and the first conductive type emitter layer is provided with a gate electrode. A first main electrode is formed on one side of the gate electrode in a turn-off thyristor with an insulated gate, in which a second main electrode is formed on a second conductivity type emitter layer and a control electrode is formed on a first conductivity type base layer. Second conductive channel MO
A turn-off thyristor with an insulated gate, wherein a first conductivity type base layer and a control electrode in contact with the first conductivity type base layer are arranged on the other side facing the SFET region.