JP3110077B2 - Thyristor with insulated gate - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

 [Object of the invention]

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a thyristor with an insulated gate.

[0002]

2. Description of the Related Art A conventional thyristor with an insulated gate is an element which is turned on at a high speed by an insulated gate.
However, this element has a disadvantage that it cannot turn off itself.

As a solution to this difficulty, there is known a turn-off thyristor with an insulated gate to which a control electrode for turning off is added. This is because a p-type base layer is selectively formed on the surface of the n-type base layer, an n-type emitter layer is formed in the p-type base layer, and a region sandwiched between the n-type emitter layer and the n-type base layer. A gate electrode is formed on the p-type base layer via a gate insulating film. The p-type base layer is provided with a control electrode that is in direct contact, in addition to the gate electrode.

In this turn-off thyristor with an insulated gate, a positive voltage is applied to the gate electrode with respect to the cathode at the time of turn-on. As a result, electrons are injected from the n-type emitter layer into the n-type base layer through the channel below the gate electrode. The thyristor is turned on when holes corresponding to the electron injection are injected from the p-type emitter layer into the n-type base layer. At the time of turn-off, a negative voltage is applied to the control electrode with respect to the cathode. As a result, the hole current in the device is sucked out to the control electrode, and the injection of electrons from the n-type emitter layer stops and the device is turned off.

[0005] Such a turn-off thyristor with an insulated gate is excellent in that it has high switching characteristics.
The need for two control terminals creates a new problem. When the power element is applied to an actual circuit, it is preferable that the number of external control terminals be one in order to simplify the driving circuit and the driving method.

[0006]

As described above, the turn-off thyristor with the insulated gate has high switching characteristics, but has a problem that it has two external control terminals.

The present invention has been made in view of the above circumstances, and has as its object to provide a thyristor with an insulated gate having a single external control terminal while maintaining excellent turn-on and turn-off characteristics. [Configuration of the Invention]

[0008]

The gist of the present invention is that the thyristor with the insulated gate has two electrodes out of the three electrodes of the insulated gate electrode, the control electrode, and the first main electrode on the same side as these. The drive is performed by short-circuiting the electrodes.

A preferred structure of the thyristor with an insulated gate according to the present invention is a high-resistance first conductivity type base layer and a lattice pattern having a predetermined opening on one surface of the first conductivity type base layer. A diffusion-formed second conductivity type base layer and a ring-shaped diffusion-formed second conductivity type base layer surrounding the first conductivity type base layer at a predetermined distance from an edge of the opening in the second conductivity type base layer. A first conductivity type emitter layer, a second conductivity type emitter layer formed on the other surface of the first conductivity type base layer, the first conductivity type base layer exposed to the opening, and the second conductivity type outside the base layer A gate electrode formed via a gate insulating film so as to cover the surface of the base layer; a first main electrode formed by simultaneously contacting the first conductivity type emitter layer and the gate electrode; Conductive Emi It has a second main electrode formed by contact with the data layer, and a control electrode formed by contact with the second conductivity type base layer.

[0010]

According to the driving method and the device structure of the present invention in which the first main electrode and the gate electrode are short-circuited, M is caused by the substrate bias effect during the initial turn-on by the control electrode.
The threshold voltage of the OSFET fluctuates. As a result, although no special voltage is applied to the gate electrode, a parasitic channel is induced to promote turn-on. The turn-off is performed by the current sink by the control electrode.

Further, according to the driving method and the element structure in which the gate electrode is short-circuited to the control electrode, the turn-on by the ordinary thyristor mode and the turn-on by the drive of the MOSFET are performed simultaneously. Turn-off can be performed by this short-circuited electrode. The above two methods use a single external control terminal while maintaining high switching characteristics of a turn-off thyristor with an insulated gate.

Finally, according to the driving method and the element structure in which the first main electrode and the control electrode are short-circuited, the structure becomes the same as that of a normal IGBT, and the gate electrode can be turned on and off with low driving power. .

[0013]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The details of the present invention will be described below with reference to the illustrated embodiments. In the following embodiments, the first conductivity type is n
A p-type is used as the mold and the second conductivity type.

FIG. 1 is a cathode side layout showing a thyristor with an insulated gate according to a first embodiment of the present invention.
FIG. 2 is a sectional view taken along line AA 'of FIG. A p-type base layer 2 is selectively formed by diffusion on one surface of a high-resistance n-type base layer 1, and an n-type emitter layer 3 is formed by diffusion in the p-type base layer 2. On the other surface of the n-type base layer 1, a p-type emitter layer 5 is formed via a high-concentration n-type buffer layer 4.

As shown in FIG. 1, the p-type base layer 2 is formed in a lattice pattern having an opening of a predetermined size, and the n-type emitter layer 3 is formed at a predetermined distance from the opening edge of the p-type base layer. It is formed in a ring-shaped pattern at a distance. A gate electrode 8 is formed on a p-type base layer 2 and an n-type base layer 1 in an island region surrounded by each of the ring-shaped n-type emitter layers 3 via a gate insulating film 7. A high-concentration p-type layer 12 for electrode contact is formed at the center of the p-type base layer 2, and a control electrode 11 having a lattice pattern is provided in contact with the high-concentration p-type layer 12. The surface on which the gate electrode 8 and the control electrode 11 are formed is covered with insulating films 10 and 14, and the contact hole 1
5 is opened, and the cathode electrode 13 that contacts the n-type emitter layer 3 and the gate electrode 8 at the same time.
Are formed. An anode electrode 6 is formed on the p-type emitter layer 5 on the other surface. Thus, in this embodiment, one external control terminal G is provided as a structure in which the gate electrode 8 and the cathode electrode 13 are short-circuited.

With such a configuration, at turn-on, a positive voltage is applied to the external control terminal G, that is, the control electrode 11, with respect to the cathode terminal K. This gives p
An n-type channel is induced on the surface of the p-type base layer 2 below the gate electrode 8 by a substrate bias effect caused by supplying a base current to the p-type base layer 2 and simultaneously applying a positive voltage to the p-type base layer 2. Then, electrons are injected from the n-type emitter layer 3 into the n-type base layer 1, and the device is turned on. At the time of turn-off, a negative voltage is applied to the external control terminal G with respect to the cathode terminal K. As a result, a part of the anode current is discharged from the p-type base layer 2 to the outside via the control electrode 11, and the device is turned off. As described above, according to this embodiment, turn-on and turn-off can be controlled at a high speed with one external control terminal.

In the above embodiment, the cathode and the gate electrode were short-circuited as a first driving method for unifying the external control terminals. In addition, as a second driving method, a method in which the control electrode and the cathode electrode are short-circuited to make the external control terminal one,
As a third driving method, a method in which the control electrode and the gate electrode are short-circuited to make one external control terminal possible.

FIG. 3 shows a second driving method. At the time of turn-on, the external control terminal G, that is, the control electrode 11
And a positive voltage is applied to the gate electrode 8. This allows
At the same time when a base current is supplied to the p-type base layer 2, electrons are injected from the n-type emitter layer 3 into the n-type base layer 1 through a channel formed below the gate electrode 8. At the time of turning off, a negative voltage is applied to the control electrode 11. As a result, a part of the anode current is discharged from the p-type base layer to the outside and is turned off.

FIG. 4 shows a third driving method. In this method, a positive voltage is applied to the gate electrode 8 at the time of turn-on, and electrons are injected from the n-type emitter layer 3 to the n-type base layer 1. At the time of turn-off, the positive voltage of the gate electrode 8 may be removed. Also, if you latch up, MO
The same use as the S thyristor becomes possible.

FIG. 5 is a cathode layout showing a device structure of another embodiment employing the first driving method.
(a) and (b) are cross-sectional views taken along lines AA 'and BB' in FIG. 5, respectively.
FIGS. 7A and 7B are cross-sectional views taken along the lines CC 'and DD' of FIG. 5, respectively. In this embodiment, the p-type base layer 2 is formed in a striped pattern, and the n-type emitter layer is formed therein in a striped pattern with a window opened in the control electrode contact portion. The gate electrode 8 is formed in a stripe pattern along the longitudinal direction of the p-type base layer 1, and the control electrode 11 is formed in a stripe pattern crossing the gate electrode 8. An opening is provided on the gate electrode 8 without the control electrode 11, where the gate electrode 8 and the cathode electrode 1 are provided.
3 is short-circuited. According to this embodiment, as in the embodiment of FIG. 1, turn-on and turn-off can be performed at a high speed with one external control terminal.

FIG. 8 is a layout on the cathode side showing the element structure of the embodiment according to the second driving method described with reference to FIG. FIGS. 9 (a) and 9 (b) are AA 'and BB' of FIG. 8, respectively.
10 (a) and 10 (b) are cross-sectional views of FIG.
It is C ', DD' sectional drawing. In this embodiment, the layout of the diffusion layer and the layout of the gate electrode 8 and the control electrode 11 are the same as those of the previous embodiment. An opening is provided on the gate electrode 8 intersecting with the control electrode 11, and the gate electrode 8
And the control electrode 11 are short-circuited. This realizes one drive terminal.

FIG. 11 is a layout on the cathode side showing the element structure of the embodiment according to the second driving method described with reference to FIG. FIGS. 12 (a) and 12 (b) show AA 'and B-
13 (a) and 13 (b) are CC 'and DD' sectional views of FIG. 11, respectively. Also in this embodiment, the layout of the diffusion layer and the layout of the gate electrode 8 and the control electrode 11 are basically the same as those in the embodiments of FIGS.
Also in this embodiment, the gate electrode 8 and the control electrode 11 are arranged so as to intersect in the form of a stripe, but the control electrode 11 in the form of a stripe is further connected on the gate electrode 8, so that the insulating film 10 on the gate electrode 8 An opening is provided so that the gate electrode 8 and the control electrode 11 are short-circuited. This realizes one drive terminal while reducing the wiring resistance of the control electrode 11. The present invention is not limited to the above-described embodiment, and can be variously modified and implemented without departing from the gist thereof.

[0023]

As described above, according to the present invention, it is possible to provide a thyristor with an insulated gate having a single external control terminal while maintaining high speed.

[Brief description of the drawings]

FIG. 1 is a cathode side layout diagram showing an element structure according to a first embodiment of the present invention.

FIG. 2 is a sectional view taken along line AA ′ of FIG. 1;

FIG. 3 is a diagram showing a second driving method for reducing the number of external control terminals.

FIG. 4 is a diagram showing a third driving method for reducing the number of external control terminals.

FIG. 5 is a layout diagram on the cathode side showing an element structure according to a second embodiment of the present invention.

FIG. 6 is a sectional view taken along line AA ′ and BB ′ of FIG. 5;

FIG. 7 is a sectional view taken along the line CC ′ and DD ′ of FIG. 5;

FIG. 8 is a layout diagram on the cathode side showing an element structure according to a third embodiment of the present invention.

FIG. 9 is a sectional view taken along the lines AA ′ and BB ′ of FIG. 8;

FIG. 10 is a sectional view taken along the line CC ′ and DD ′ of FIG. 8;

FIG. 11 is a cathode-side layout diagram showing a device structure according to a fourth embodiment of the present invention.

FIG. 12 is a sectional view taken along the lines AA ′ and BB ′ of FIG. 11;

FIG. 13 is a sectional view taken along the line CC ′ and DD ′ of FIG. 11;

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 ... High resistance n-type base layer, 2 ... P-type base layer, 3 ... N-type emitter layer, 4 ... N-type buffer layer, 5 ... P-type emitter layer, 6 ... Anode electrode, 7 ... Gate insulating film, 8 ... Gate electrode, 10, 14 insulating film, 11 control electrode, 12 high-concentration p-type layer, 13 cathode electrode.

Claims (1)

(57) [Claims] A first conductive type base layer having a high resistance;
A second conductivity type base layer diffused and formed in a lattice pattern having a predetermined opening on one surface of the conductivity type base layer;
A first-conductivity-type emitter layer formed in the second-conductivity-type base layer in a ring shape at a predetermined distance from an edge of the opening and surrounding the first-conductivity-type base layer; A second conductive type emitter layer formed on the other surface of the mold base layer, a gate insulating layer covering the first conductive type base layer exposed to the opening, and a surface of the second conductive type base layer outside the first conductive type base layer. A gate electrode formed through a film, a first main electrode formed by simultaneously contacting the first conductivity type emitter layer and the gate electrode, and a second electrode formed by contacting the second conductivity type emitter layer. A thyristor with an insulated gate, comprising: a second main electrode; and a control electrode formed in contact with the second conductivity type base layer.