JPH0590359A - Semiconductor wafer and its probe card - Google Patents

Abstract

PURPOSE:To bring probe needles into contact with probe test electrodes accurately and improve the reliability and the throughput of the probe test by a method wherein alignment electrodes are formed on a semiconductor wafer and alignment needles are provided on a probe card. CONSTITUTION:A plurality of alignment electrodes 20, 21 and 22 are provided on a position which is not hidden by probe needles 44 at the time of a probe test, for instance on a street positioned between corresponding corners of respective chips 12 on a semiconductor wafer 10 and, further, electrode wirings 30 which connect the respective alignment electrodes 21 and 22 to each other are provided on the street 11. Alignment needles 50 which correspond to the alignment electrodes 20 are provided on a probe card 40. With this constitution, the respective probe test electrodes of the chips 12 can be aligned with the respective probe needles 44 of the probe card 40 simply by aligning the alignment electrodes 20 with the alignment needles 50. Therefore, an alignment process can be simplified and accurate.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor wafer and a probe card used for a probe test of the semiconductor wafer.

[0002]

2. Description of the Related Art In a semiconductor manufacturing process, a semiconductor wafer is usually subjected to a pre-process to form a plurality of chips,
A probe test is performed to inspect the electrical characteristics of each chip. In the probe test, a probe card is mounted on a wafer prober, and a plurality of probe needles of the probe card are brought into contact with corresponding probe test electrodes of a chip to be probe-tested to inspect the electrical characteristics of the chip.

The semiconductor wafer will be described with reference to a plan view of FIG. 5 and an enlarged view of a portion A in FIG. 5 shown in FIG. As shown in the figure, a single semiconductor wafer 80 has a plurality of chips 1 divided by streets 11 for normal dicing.
2 are arranged vertically and horizontally. A plurality of probe test electrodes 13 for performing a probe test are arranged in the peripheral portion of each chip 12.

Next, the probe card will be described with reference to the plan view of FIG. As shown in the figure, the printed wiring board 41 is provided with a substantially circular hole 42. An annular mounting portion 43 is provided on the printed wiring board 41 around the hole 42. A plurality of probe needles 44 are supported on the annular mounting portion 43 substantially at right angles to the arrangement direction of the probe test electrodes 13 (see FIG. 6) of the tip 12 and toward the outer side of the tip 12. The tip of each probe needle 44 is arranged in a one-to-one correspondence with the probe test electrode 13 (see FIG. 6) of the chip 12 to be inspected (see FIG. 6). Further, the ends of the probe needles 44 are connected to one ends of probe wires 45 made of, for example, printed wires in a one-to-one correspondence. Furthermore, each probe wiring 4
On the other end of 5, a connector connecting contact portion 46 is formed. The probe card 90 is configured as described above.

Next, the chip 1 having the semiconductor wafer 80
A method of aligning the probe test electrodes 13 of No. 2 with the probe needles 44 of the probe card 90 will be described. Each probe test electrode 13 is attached to each probe needle 44.
In order to make one-to-one contact with each other, the semiconductor wafer 80 is moved while observing it with a microscope (not shown) installed in a wafer prober (not shown) and used as a reference for alignment. The probe test electrodes 13 corresponding to the probe needles 44 are brought into contact with some of the probe needles 44.

[0006]

However, the inspection items of the probe test increase as the elements formed on the chip become highly integrated and have high performance. For this reason,
The number of probe test electrodes also increases, and the electrodes are miniaturized. Therefore, since the number of probe needles also increases, the probe needles are arranged in a dense state. Therefore, since the probe needle hides the probe test electrode,
The probe needle and the probe test electrode cannot be aligned reliably. As a result, contact failure between the probe needle and the probe test electrode is likely to occur, and yield loss in which a good product is determined to be a defective product is likely to occur. Therefore, the reliability of the probe test is reduced. Therefore, trying to accurately align the probe needles takes a very long time, and the throughput of the probe test is reduced.

An object of the present invention is to provide a semiconductor wafer and a probe card for the semiconductor wafer, which are excellent in reliability and throughput of a probe test.

[0008]

SUMMARY OF THE INVENTION The present invention is a semiconductor wafer and a probe card therefor, which are made to achieve the above object. That is, in a semiconductor wafer having a plurality of chips partitioned by streets, in a state in which the plurality of alignment electrodes are not hidden by the probe needles at the time of the probe test on the streets around the chips or on the chips. In addition, the electrode wiring for connecting the respective positioning electrodes is formed on the street or the chip. A probe card in which probe needles are arranged corresponding to the arrangement of a plurality of probe test electrodes formed on a chip of a semiconductor wafer to be probe tested, and which corresponds to each of a plurality of alignment electrodes formed on a semiconductor wafer. The probe card is formed with a plurality of alignment needles and alignment wirings connected to the alignment needles.

[0009]

In the semiconductor wafer having the above structure, the plurality of alignment electrodes are provided on the streets around each chip or on the chips in such a state that the alignment electrodes are not hidden by the probe needles, so that the alignment electrodes are hidden by the probe needles. And the positioning electrode becomes easy to see. Also, since each positioning electrode is connected by electrode wiring, it is possible to detect whether or not each positioning needle is accurately in contact with each positioning electrode by passing a current between each positioning electrode. It In the probe card having the above configuration, since the positioning needles corresponding to the plurality of positioning electrodes formed on the semiconductor wafer are provided, each positioning needle does not overlap with the probe needle and become difficult to see. Moreover, since the wiring for positioning that connects to each positioning needle is formed, by connecting an ammeter between each wiring for positioning,
The conduction between the positioning electrodes can be confirmed. For this reason,
It is indirectly confirmed whether or not the probe needle is accurately in contact with the probe test electrode.

[0010]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of a semiconductor wafer and a probe card according to the present invention will be described with reference to FIG. The same components as those explained in FIGS. 5 to 7 of the prior art are designated by the same reference numerals. Also semiconductor wafer 1
The probe test electrode 13 forming the 0, the printed wiring board 41 forming the probe card 40, the hole 42, the annular mounting portion 43, the probe needle 44, the probe wiring 45, the connector connecting contact portion 46, etc. Since it was explained above, the explanation is omitted here. As shown in the figure, the semiconductor wafer 10 is, for example, each chip 1 at a position that is not hidden by the probe needles 44 during the probe test.
Street 11 (11a, 1
1b) is provided with a plurality of alignment electrodes 20 (21, 22), and each alignment electrode 21, 21 is provided on the street 11.
The electrode wiring 30 for connecting the two 22 is provided.

The probe card 40 has a position corresponding to the positioning electrodes 20 formed on the streets 11 of the semiconductor wafer 10 in a one-to-one correspondence with the probe card (90) described with reference to FIG. Aligning needle 50
And each end of the positioning needle 50 is connected to one end of a positioning wiring 60 made of a printed wiring. An ammeter (not shown) for confirming whether or not a current flows when each of the positioning needles 50 is brought into contact with each of the positioning electrodes 20 at the other end of the positioning wiring 60.
A terminal 70 that can be connected to is formed.

The positioning electrodes 20 on the semiconductor wafer 10 are not limited to the above arrangement. For example, if the position is not hidden by the probe needles 44 (see FIG. 1), as shown in FIG.
a, 11b, 11c). Also in this case, the respective positioning electrodes 20 (21 to 23) are connected by the electrode wiring 30 (31, 32).
It is also possible to form the positioning electrodes 20 at four or more positions. Further, although the alignment electrode 20 is provided on the street 11 in the above-described embodiment, the alignment electrode 20 is located in a region other than the pattern forming region 14 (diagonally shaded region) in the chip 12 and the probe needle at the time of the probe test. It is also possible to form it in a position that is not hidden by. Although the drawing shows a state in which the positioning electrodes 20 are formed on one chip 12, normally, the positioning electrodes 20 are formed on all the chips 12.
Is formed.

Further, for example, when the alignment electrodes 20 are provided at three places on the street 11, as shown in FIG. 3, the alignment electrodes 21 to 23 are arranged in one-to-one correspondence with each other. The probe card 40 is provided with three alignment needles 50 (51 to 53). Positioning wirings 60 (61 to 63) made of printed wirings are connected to the respective positioning needles 51 to 53.
Terminals 70 (71 to 73) for connecting an ammeter are formed on each of the alignment wires 60 (61 to 63). When the positioning electrodes 20 are formed at four or more locations (not shown), the positioning needles are provided on the probe card at the positions corresponding to the positioning electrodes as described above. A positioning wire is connected to each positioning needle, and a terminal is formed on each positioning wire.

Next, a method for aligning the probe test electrode 13 of the chip 12 with each probe needle 50 of the probe card 40 will be described with reference to the schematic configuration diagrams of the wafer prober shown in FIGS. 1 and 4.

First, the probe card 40 is previously attached to a predetermined position of the wafer prober 100. Further, the wafer chuck 1 provided on the stage 110 of the wafer prober 100
A semiconductor wafer 10 to be subjected to a probe test is placed on 15. Then, the stage 110 is moved in the x-axis direction (vertical direction with respect to the drawing), the y-axis direction (horizontal direction), the z-axis direction (height direction), the θ direction (arrow direction) or the like to move the probe card 40. The positioning electrode 20 of the chip 12 is positioned and brought into contact with the positioning needle 50. At this time, the fine adjustment of the alignment is performed by observing with the microscope 120 of the wafer prober 100, for example, the joystick 13
The stage 110 is moved by operating 0.

The alignment needle 50 is attached to the alignment electrode 2
After aligning with the position of 0, a current is passed between the alignment electrodes 20 to align the alignment electrode 20 and the alignment needle 50.
Check if and are in good contact. At this time,
If no current flows, the contact between the positioning electrode 20 and the positioning needle 50 is incorrect, and the positioning is performed again. If the value of the flowing current is small or unstable, the contact between the positioning electrode 20 and the positioning needle 50 is not sufficient, and the contact resistance increases. In this case, the position of the positioning needle 50 to be brought into contact with the positioning electrode 20 is changed to perform the positioning again, or the pressing force of the positioning needle 50 is increased.
In this way, the positioning electrode 20 and the positioning needle 5
By confirming the contact with 0, the contact state between the probe needle 44 and the probe test electrode 13 is indirectly confirmed.

As described above, by forming the positioning electrodes 20 on the semiconductor wafer 10 and providing the positioning needles 50 on the probe card 40, the number of the probe needles 44 is increased, and the probe needles 44 are used for the probe test. Even when the electrode 13 is hidden, each probe needle 44 can be accurately brought into contact with each probe test electrode 13.

[0018]

As described above, according to the present invention,
A plurality of alignment electrodes for aligning the probe needles were provided on the semiconductor wafer. Further, the probe card was provided with a positioning needle corresponding to the positioning electrode. For this reason,
Simply align the positioning electrode with the positioning needle,
Each probe test electrode of the chip is aligned with each probe needle of the probe card. As a result, the alignment process is simplified and accurate. Therefore, the reliability of the probe test can be improved. In addition, the throughput of the alignment process can be significantly improved.

[Brief description of drawings]

FIG. 1 is a partially omitted plan view of an embodiment.

FIG. 2 is a plan view of a main part of a semiconductor wafer according to another embodiment.

FIG. 3 is a partially omitted plan view of a probe card according to another embodiment.

FIG. 4 is a schematic configuration explanatory view of a wafer prober.

FIG. 5 is a plan view of a conventional semiconductor wafer.

FIG. 6 is an enlarged view of part A in FIG.

FIG. 7 is a plan view of a conventional probe card.

[Explanation of symbols]

 10 Semiconductor Wafer 11 Street 12 Chip 13 Probe Test Electrode 20 Positioning Electrode 30 Electrode Wiring 40 Probe Card 44 Probe Needle 50 Positioning Needle 60 Positioning Wiring

Claims (2)

[Claims] 1. In a semiconductor wafer having a plurality of chips partitioned by streets, a plurality of alignment electrodes may be hidden by the probe needles at the time of a probe test on the streets around the respective chips or on the chips. A semiconductor wafer, characterized in that it is provided in a non-existing state, and electrode wirings that connect the respective positioning electrodes are formed on the streets or the chips. 2. A probe card having probe needles arranged corresponding to the arrangement of a plurality of probe test electrodes formed on a chip of a semiconductor wafer to be probe tested, wherein a plurality of probe needles formed on the semiconductor wafer are provided on the probe card. 2. A probe card in which a positioning needle corresponding to each of the positioning electrodes and a positioning wire connected to each positioning needle are formed.