JPH0587020B2 - - Google Patents
Info
- Publication number
- JPH0587020B2 JPH0587020B2 JP16400485A JP16400485A JPH0587020B2 JP H0587020 B2 JPH0587020 B2 JP H0587020B2 JP 16400485 A JP16400485 A JP 16400485A JP 16400485 A JP16400485 A JP 16400485A JP H0587020 B2 JPH0587020 B2 JP H0587020B2
- Authority
- JP
- Japan
- Prior art keywords
- integrated circuit
- hybrid integrated
- lead
- lead terminals
- circuit board
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
- 230000017525 heat dissipation Effects 0.000 claims description 3
- 239000000758 substrate Substances 0.000 claims description 3
- 239000004020 conductor Substances 0.000 claims description 2
- 239000003989 dielectric material Substances 0.000 claims 1
- -1 resistor Substances 0.000 claims 1
- 238000004519 manufacturing process Methods 0.000 description 7
- 238000000034 method Methods 0.000 description 4
- 229910000679 solder Inorganic materials 0.000 description 3
- 238000010586 diagram Methods 0.000 description 2
- 229910000906 Bronze Inorganic materials 0.000 description 1
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 1
- 229910000990 Ni alloy Inorganic materials 0.000 description 1
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 1
- 239000010974 bronze Substances 0.000 description 1
- 239000003990 capacitor Substances 0.000 description 1
- 239000010949 copper Substances 0.000 description 1
- 229910052802 copper Inorganic materials 0.000 description 1
- KUNSUQLRTQLHQQ-UHFFFAOYSA-N copper tin Chemical compound [Cu].[Sn] KUNSUQLRTQLHQQ-UHFFFAOYSA-N 0.000 description 1
- 238000004070 electrodeposition Methods 0.000 description 1
- 239000003822 epoxy resin Substances 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 238000009434 installation Methods 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 229920000647 polyepoxide Polymers 0.000 description 1
- 238000003825 pressing Methods 0.000 description 1
- 229920005989 resin Polymers 0.000 description 1
- 239000011347 resin Substances 0.000 description 1
- 238000007650 screen-printing Methods 0.000 description 1
- 238000005476 soldering Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/495—Lead-frames or other flat leads
- H01L23/49541—Geometry of the lead-frame
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
- H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
- H05K3/34—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
- H05K3/3405—Edge mounted components, e.g. terminals
Description
【発明の詳細な説明】
〔発明の利用分野〕
本発明は混成集積回路装置にかかわり、特に、
多数のリード端子を容易に出せるようにした混成
集積回路装置に関するものである。DETAILED DESCRIPTION OF THE INVENTION [Field of Application of the Invention] The present invention relates to a hybrid integrated circuit device, and in particular,
The present invention relates to a hybrid integrated circuit device in which a large number of lead terminals can be easily taken out.
従来の混成集積回路装置は、絶縁性基板上に、
スクリーン印刷手法により、導体、抵抗体、誘電
体厚膜ペーストを印刷し、高温空気雰囲気中で焼
成して所定の回路パターンを形成し、その後、ト
ランジスタ、コンデンサ等の電気部品をはんだ付
けして搭載し、リード端子を絶縁性基板端面にあ
るリード端子取付用電極に挿入し、はんだ付けし
て混成集積回路基板としている。最近は、混成集
積回路装置の高機能化に伴い、リード端子数が増
加したり、スルーホールを利用して両面実装をす
る等、その高密度化が図られている。これらの混
成集積回路装置におけるリード端子の取付構造と
しては、特開昭59−33858号公報、実開昭59−
72745号公報に見られるように、混成集積回路基
板の２辺にリード端子を別々に挿入し、その後は
んだ付けしたものや、あるいは特開昭59−44856
号公報に見られるように、該回路基板の周囲に、
リード端子とは別に、特定のジヤンパー線を取り
付けているものがある。しかし、これらはいずれ
も、リード端子の接続を同時に行うことができな
いものであり、最近の高密度化した混成集積回路
装置のように、多数のリード端子を出したり、表
裏のパターンを接続したりすることが必要なもの
では、工数が増加して、製造工程の簡略化が図れ
ない等の問題があつた。
Conventional hybrid integrated circuit devices are built on an insulating substrate.
Conductors, resistors, and dielectric thick film pastes are printed using screen printing methods, and baked in a high-temperature air atmosphere to form a predetermined circuit pattern.Electric components such as transistors and capacitors are then soldered and mounted. Then, the lead terminals are inserted into the lead terminal attachment electrodes on the end face of the insulating substrate and soldered to form a hybrid integrated circuit board. Recently, as hybrid integrated circuit devices have become more sophisticated, efforts have been made to increase their density by increasing the number of lead terminals and implementing double-sided mounting using through holes. The mounting structure of lead terminals in these hybrid integrated circuit devices is disclosed in Japanese Patent Application Laid-open No. 59-33858 and Japanese Utility Model Application No. 59-33858.
As seen in Publication No. 72745, lead terminals are inserted separately on two sides of a hybrid integrated circuit board and then soldered, or Japanese Patent Application Laid-Open No. 59-44856
As seen in the publication, around the circuit board,
Some have a specific jumper wire attached in addition to the lead terminal. However, with all of these, it is not possible to connect lead terminals at the same time, and as in the case of recent high-density hybrid integrated circuit devices, it is difficult to connect multiple lead terminals or connect patterns on the front and back sides. In the case of products that require additional processing, there are problems such as an increase in the number of man-hours and the inability to simplify the manufacturing process.
本発明の目的は、上記従来技術の欠点を除き、
リード端子を混成集積回路基板の２辺以上に接続
したり、該回路基板の表裏パターンを接続したり
することが同時にでき、製造効率の向上を図つた
混成集積回路装置を提供することにある。
The purpose of the present invention is to eliminate the drawbacks of the above-mentioned prior art,
To provide a hybrid integrated circuit device capable of simultaneously connecting lead terminals to two or more sides of a hybrid integrated circuit board, connecting front and back patterns of the circuit board, and improving manufacturing efficiency.
本発明は、多数のリード端子を備えたフープ状
のリードフレームを用い、これに混成集積回路基
板を搭載し、該基板のリード端子取付用電極上を
一方向から押圧して、リード端子の接続を行うも
ので、これによつて、該回路基板の２辺以上から
リード端子を同時に引き出したり、表裏パターン
を同時に接続できるように図つたものである。
The present invention uses a hoop-shaped lead frame equipped with a large number of lead terminals, mounts a hybrid integrated circuit board on this, and connects the lead terminals by pressing the lead terminal mounting electrodes of the board from one direction. This allows lead terminals to be pulled out from two or more sides of the circuit board at the same time, and front and back patterns can be connected simultaneously.
以下、本発明の実施例を図面に従つて説明す
る。第１図〜第３図はそれぞれ本発明を実施した
混成集積回路装置の外観を示したものである。こ
のうち、第１図は、混成集積回路基板１の２辺以
上に表面接続用リード端子２を接続した多数のリ
ード端子を備えた装置を示し、第２図は、混成集
積回路基板１に表面接続用リード端子２と裏面接
続用リード端子３とを備えた装置を示し、第３図
は、混成集積回路基板１の表裏パターン（図示せ
ず）を、隣接リード端子を連結して一体とした表
裏接続用一体リード端子４によつて接続した装置
を示す。
Embodiments of the present invention will be described below with reference to the drawings. 1 to 3 each show the appearance of a hybrid integrated circuit device embodying the present invention. Of these, FIG. 1 shows a device equipped with a large number of lead terminals in which surface connection lead terminals 2 are connected to two or more sides of a hybrid integrated circuit board 1, and FIG. FIG. 3 shows a device equipped with connection lead terminals 2 and rear connection lead terminals 3, in which the front and back patterns (not shown) of the hybrid integrated circuit board 1 are integrated by connecting adjacent lead terminals. The device is shown connected by an integral lead terminal 4 for connecting the front and back sides.
第４図は、第１図に示す混成集積回路装置を形
成するためのリードフレーム５の平面図であり、
リードフレーム５の内側に、多数の表面接続用リ
ード端子２と、該リード端子を接続するとき混成
集積回路基板（図示せず）を支持する支持板部６
と、混成集積回路装置の放熱特性を向上させるた
めの放熱板部７とを備えている。第５図は、第４
図の応用例で、第４図ではリードフレーム５の中
央にあつた放熱板部７を除外し、支持板部６だけ
を備えているものである。第６図は第５図のＡ−
A′断面図である。図において、支持板部６また
は放熱板部７（ただし、第４図に示すリードフレ
ームの場合）の上に混成集積回路基板（図示せ
ず）を入れ、上方に突出しかつ曲げ加工された表
面接続用リード端子２で該基板を押さえ込むよう
になつている。 FIG. 4 is a plan view of the lead frame 5 for forming the hybrid integrated circuit device shown in FIG.
Inside the lead frame 5, there are a large number of surface connection lead terminals 2 and a support plate part 6 that supports a hybrid integrated circuit board (not shown) when connecting the lead terminals.
and a heat dissipation plate portion 7 for improving the heat dissipation characteristics of the hybrid integrated circuit device. Figure 5 shows the fourth
In the application example shown in FIG. 4, the heat sink part 7 located at the center of the lead frame 5 is excluded, and only the support plate part 6 is provided. Figure 6 is A- of Figure 5.
It is an A′ cross-sectional view. In the figure, a hybrid integrated circuit board (not shown) is placed on the support plate part 6 or the heat sink part 7 (in the case of the lead frame shown in FIG. 4), and the surface connection is protruded upward and bent. The board is held down by the lead terminals 2.
第７図は、第２図に示す混成集積回路装置を形
成するためのリードフレーム５の平面図、第８図
はそのＢ−B′断面図であり、多数の表面接続用
リード端子２と、曲げ加工のない裏面接続用リー
ド端子３と、支持板部６および放熱板部７とを備
えている。 FIG. 7 is a plan view of the lead frame 5 for forming the hybrid integrated circuit device shown in FIG. It includes a lead terminal 3 for connection on the back side that is not bent, a support plate part 6, and a heat sink part 7.
また、第９図は、第３図に示す混成集積回路装
置を形成するためのリードフレーム５の平面図、
第１０図はそのＣ−C′断面図であり、多数の表面
接続用リード端子２と、該リード端子に隣接しか
つ回路基板のリード端子取付用電極位置に対応し
た表裏接続用一体リード端子４と、裏面接続用リ
ード端子３と、支持板部６および放熱板部７とを
備えている。 9 is a plan view of a lead frame 5 for forming the hybrid integrated circuit device shown in FIG.
FIG. 10 is a cross-sectional view taken along the line C-C', showing a large number of lead terminals 2 for surface connection, and integrated lead terminals 4 for front and back connections adjacent to the lead terminals and corresponding to the electrode positions for attaching lead terminals on the circuit board. , a backside connection lead terminal 3 , a support plate section 6 , and a heat sink section 7 .
次に、本発明による混成集積回路装置の製法に
ついて述べる。第１１図は製造工程の説明図であ
る。リードフレーム５は表面接続用リード端子２
および裏面接続用リード端子３を備え、フープ状
で加工されており、材質としてはリン青銅、Fe
−Ni合金等を使い、公知の技術であるプレス加
工によつて所定パターンに抜き、曲げ加工を行
い、その後、厚さ２〜5μmの銅めつき、厚さ３〜
7μmのはんだめつきを行い、第１１図ａに示す断
面構成とする。混成集積回路基板１の取付けは、
表面接続用リード端子２を押し上げ（同図ｂ）、
支持板部６あるいは放熱板部７の上に前記回路基
板１を入れ、ばね性を備えた表面接続用リード端
子２と裏面接続用リード端子３とではさみ込む。
その後、リード端子接続部をレーザあるいは熱風
加熱方式により矢印方向から加熱し、混成集積回
路基板１のリード端子取付用電極上に形成されて
いるはんだ８を溶融させてはんだ付け接続する
（同図ｃおよびｄ）。その後、混成集積回路基板１
の全体を、耐湿向上、外力保護を兼ねて、エポキ
シ系の樹脂９で被覆し（同図ｅ）、必要な前記リ
ード端子の抜き、曲げ加工を行つて、混成集積回
路装置とする（同図ｆ）。 Next, a method for manufacturing a hybrid integrated circuit device according to the present invention will be described. FIG. 11 is an explanatory diagram of the manufacturing process. Lead frame 5 has surface connection lead terminal 2
It is equipped with a lead terminal 3 for connection on the back side, and is processed into a hoop shape, and the material is phosphor bronze, Fe
-Using Ni alloy etc., it is punched into a predetermined pattern by a known technique of press working and bent, then copper plated to a thickness of 2 to 5 μm, and then plated to a thickness of 3 to 5 μm.
A 7 μm thick solder is applied to create the cross-sectional configuration shown in FIG. 11a. The installation of the hybrid integrated circuit board 1 is as follows:
Push up the surface connection lead terminal 2 (b in the same figure),
The circuit board 1 is placed on the support plate part 6 or the heat sink part 7, and is sandwiched between the front surface connection lead terminal 2 and the back surface connection lead terminal 3 having spring properties.
Thereafter, the lead terminal connection portion is heated in the direction of the arrow using a laser or hot air heating method to melt the solder 8 formed on the lead terminal attachment electrode of the hybrid integrated circuit board 1 and connect it by soldering (c in the same figure). and d). After that, the hybrid integrated circuit board 1
The whole is coated with epoxy resin 9 to improve moisture resistance and protect it from external forces (see figure e), and the necessary lead terminals are removed and bent to form a hybrid integrated circuit device (see figure e). f).
本発明によれば、フープ状のリードフレーム内
に、混成集積回路基板と接続するための表面接続
用、裏面接続用の各リード端子および表裏接続用
一体リード端子を種々の組み合わせで設けること
により、回路基板の２辺以上からリード端子を出
した高機能混成集積回路装置や、表裏パターンの
接続を容易にできる高密度混成集積回路装置を、
容易にかつ量産に適した製法で得ることができ
る。
According to the present invention, by providing various combinations of lead terminals for front surface connection, back surface connection, and integrated lead terminals for front and back connection for connection to a hybrid integrated circuit board in a hoop-shaped lead frame, We offer high-performance hybrid integrated circuit devices with lead terminals extending from two or more sides of the circuit board, and high-density hybrid integrated circuit devices that can easily connect front and back patterns.
It can be easily obtained by a manufacturing method suitable for mass production.
第１図〜第３図はそれぞれ本発明による混成集
積回路装置の実施例の外観を示す斜視図、第４図
〜第１０図は上記実施例で用いるリードフレーム
の平面図および断面図、第１１図は該実施例の製
造工程説明図である。
符号の説明、１……混成集積回路基板、２……
表面接続用リード端子、３……裏面接続用リード
端子、４……表裏接続用一体リード端子、５……
リードフレーム、６……支持板部、７……放熱板
部、８……はんだ、９……樹脂。
1 to 3 are perspective views showing the appearance of embodiments of the hybrid integrated circuit device according to the present invention, FIGS. 4 to 10 are plan views and cross-sectional views of lead frames used in the above embodiments, and FIG. The figure is an explanatory diagram of the manufacturing process of this example. Explanation of symbols, 1... Hybrid integrated circuit board, 2...
Lead terminal for surface connection, 3...Lead terminal for back connection, 4...Integrated lead terminal for front and back connection, 5...
Lead frame, 6... Support plate section, 7... Heat sink section, 8... Solder, 9... Resin.
Claims (1)
料で回路を形成し、その後電気部品を搭載してな
る混成集積回路基板に、その２辺以上においてリ
ード端子を接続して構成される混成集積回路装置
において、前記混成集積回路基板上のリード端子
取付用電極に対応する位置にそれぞれリード端子
を備えたフープ状のリードフレームを用い、該リ
ードフレーム上に前記混成集積回路基板を載置
し、前記リード端子取付用電極上を一方向から押
圧して、これと前記リードフレームのリード端子
とを接続したことを特徴とする混成集積回路装
置。 ２ リードフレームの複数のリード端子が、混成
集積回路基板の裏面で接続できるようにしたリー
ド端子を含むことを特徴とする特許請求の範囲第
１項に記載の混成集積回路装置。 ３ リードフレームの複数のリード端子が、隣接
リード端子間で混成集積回路基板の表面と裏面と
を同時に接続できるようにしたリード端子を含む
ことを特徴とする特許請求の範囲第１項に記載の
混成集積回路装置。 ４ リードフレームが、そのリード端子よりも内
側の位置に、混成集積回路基板の部品搭載側と反
対側の面と接触できる放熱板部を備えたことを特
徴とする特許請求の範囲第１項ないし第３項のい
ずれか１項に記載の混成集積回路装置。[Claims] 1. A circuit is formed on an insulating substrate using conductor, resistor, and dielectric materials, and then lead terminals are attached to two or more sides of the hybrid integrated circuit board on which electrical components are mounted. In a hybrid integrated circuit device constructed by connecting the hybrid integrated circuit, a hoop-shaped lead frame is provided with lead terminals at positions corresponding to electrodes for attaching lead terminals on the hybrid integrated circuit board, and the hybrid integrated circuit is mounted on the lead frame. 1. A hybrid integrated circuit device, wherein an integrated circuit board is mounted, and the lead terminal attachment electrodes are pressed from one direction to connect the lead terminals of the lead frame. 2. The hybrid integrated circuit device according to claim 1, wherein the plurality of lead terminals of the lead frame include lead terminals that can be connected on the back side of the hybrid integrated circuit board. 3. The device according to claim 1, wherein the plurality of lead terminals of the lead frame include lead terminals that are capable of simultaneously connecting the front and back surfaces of the hybrid integrated circuit board between adjacent lead terminals. Hybrid integrated circuit device. 4. Claims 1 to 4, characterized in that the lead frame is provided with a heat dissipation plate portion located inside the lead terminal and capable of contacting the surface of the hybrid integrated circuit board opposite to the side on which the components are mounted. The hybrid integrated circuit device according to any one of Item 3.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP16400485A JPS6225443A (en) | 1985-07-26 | 1985-07-26 | Hybrid integrated circuit device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP16400485A JPS6225443A (en) | 1985-07-26 | 1985-07-26 | Hybrid integrated circuit device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS6225443A JPS6225443A (en) | 1987-02-03 |
| JPH0587020B2 true JPH0587020B2 (en) | 1993-12-15 |
Family
ID=15784929
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP16400485A Granted JPS6225443A (en) | 1985-07-26 | 1985-07-26 | Hybrid integrated circuit device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6225443A (en) |
Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2541465B2 (en) * | 1993-07-31 | 1996-10-09 | 日本電気株式会社 | Hybrid integrated circuit device |
| JP3990837B2 (en) * | 1999-03-03 | 2007-10-17 | 木谷電器株式会社 | Press parts for electrical equipment |
-
1985
- 1985-07-26 JP JP16400485A patent/JPS6225443A/en active Granted
Also Published As
| Publication number | Publication date |
|---|---|
| JPS6225443A (en) | 1987-02-03 |
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