JPH0583643A - Image pickup device - Google Patents

Abstract

PURPOSE:To provide a simple image signal processing part to an image pickup parts including plural solid state image pickup elements arranged at the optical positions where the image pickup areas different optically from each other are received relatively and adjacently and the optical image transmitted through an image pick-up lens set on the optical axis of the lens is divided and reflected by a reflector having plural reflecting faces and therefore to read the images at high image resolution. CONSTITUTION:The single screen image data storage circuits 6 are provided in the number corresponding to the number of solid state image pickup elements. The output image signals outputted from the solid state image pickup elements by an interlace system are simultaneously stored in the odd or even fields for each line corresponding circuit 6. Meanwhile a storage circuit control circuit 13 includes the input/output switch control parts 9 and 10 which read the single screen image signals out of the fields different from the working field storing the image signals. In such a constitution, an image signal processing part is secured to synthesize the image signals outputted from the circuits 6. Then these processes image signals are outputted through a single screen.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION The present invention relates to, for example, an electronic camera and a T
The present invention relates to an imaging device used for a V camera or the like.

[0002]

2. Description of the Related Art In recent years, research and development of high-definition imaging devices of this type have been advanced, and for example, they are in the stage of practical application as an imaging method based on the high-definition TV standard mainly by the Japan Broadcasting Corporation. According to this, the used frequency band is 20 to 3
It has a very high characteristic such as 0 MHz band.

On the other hand, along with the high definition of such an image pickup system, solidification of the image pickup element is being promoted. However, considering a solid-state image sensor capable of supporting the above high-definition image capturing method, the number of pixels is required to be 1 million or more and the clock frequency is required to be 30 MHz or more. At present, such a solid-state image sensor is not in a practical stage.

Therefore, a method for realizing high definition by the current solid-state image pickup device and driving method is being studied, for example, there is one disclosed in Japanese Patent Laid-Open No. 60-213178. This is a reflector, such as a quadrangular pyramid, which has an optical image obtained through an image pickup lens arranged at the pupil position of the optical system.
For example, four solid-state image pickup elements are arranged so that each of the structures, which are divided and reflected by one reflecting surface, are imaged at positions optically shifted by a predetermined pitch from each other on each light receiving surface. is there.

However, when looking at the structure of the solid-state image pickup device of this system, each pixel of each image pickup device is not optically separated due to the size of the light receiving portion with respect to each pixel pitch, and all the pixels are Since they partially overlap, the actual resolution cannot be increased. In particular, in order to increase the area of the light receiving portion and the transfer CCD, in a solid-state image sensor of a type in which an amorphous Si photoelectric conversion film is laminated,
Due to the size of the light receiving portion, further substantial improvement in resolution cannot be expected. Further, it is not easy to accurately arrange the reflector at the pupil position.

[0006]

From the above,
An image pickup lens and a reflector having a plurality of reflecting surfaces arranged on the optical axis of the image pickup lens to divide and reflect an optical image transmitted through the image pickup lens are provided, and each light divided and reflected by the reflector is provided. Japanese Patent Application No. Hei 1 (1999) -1104 discloses a device in which a plurality of solid-state image pickup devices are arranged at optical positions where light-receiving regions that are optically different from each other are relatively adjacent to each other with respect to an image.
Proposed by the applicant as No. 331971.

According to this, each solid-state image pickup device receives the light image divided and reflected by each reflecting surface of the reflector.
Since each solid-state image pickup element is located at an optical position where the light-images of some optically different image pickup areas are relatively adjacent to each other for each light image, each solid-state image pickup element is read after reading. An image for one screen is reproduced by synthesizing the read image signals of the reading area. Therefore, regardless of the size of the light receiving portion of the solid-state image sensor, it is possible to read with high resolution, which is twice as many as that of the solid-state image sensor, as compared with the case of reading with a single solid-state image sensor.

However, there is no mention of how to combine the image signals obtained from such a plurality of solid-state image pickup devices by an image processing unit having a low cost and a simple structure and control.

[0009]

According to a first aspect of the present invention, there is provided an image pickup lens, and a plurality of reflecting surfaces arranged on the optical axis of the image pickup lens for dividing and reflecting an optical image transmitted through the image pickup lens. Imaging with a reflector and a plurality of solid-state image sensors arranged at optical positions to receive image areas that are optically different from each other and are optically received by the reflector in a relatively adjacent state. And a single-screen image data storage circuit of a number corresponding to the number of each solid-state image sensor,
An image signal output from each solid-state image sensor in the interlace system is simultaneously stored in an odd field or an even field on a line-by-line basis in a corresponding one-screen image data storage circuit, but different from the field during storage operation. It is composed of a storage circuit control means having an input / output switching control section for reading out a one-screen image signal from the other field in units of lines, and the image signals from these one-screen image data storage circuits are combined to process one screen image. An image signal processing unit for outputting as a signal is provided.

In this case, according to the second aspect of the invention, an addition circuit for adding all the one-screen image signals from each one-screen image data storage circuit to the image signal processing section and one screen corresponding to the corresponding read effective pixel. A control means for causing the addition circuit to output the image signal of the one-screen image data storage circuit other than the image data storage circuit as zero is provided.

According to the third aspect of the invention, the storage circuit control means has a sequence control means for reversing the image signal sequence in the horizontal direction at the time of storing or reading the one-screen image data storage circuit, According to a fourth aspect of the invention, the storage circuit control means has a sequence control means for reversing the image signal sequence in the vertical direction when storing or reading the one-screen image data storage circuit.

Further, in the invention according to claim 5, the arrangement of the read effective pixel portions of each solid-state image pickup device in the image pickup portion is partially overlapped with each other in the connection portion having the optical positional relationship, and at least in the horizontal direction. A reflector having two or more reflecting surfaces, a 1/2 division circuit for multiplying the image signal added by the addition circuit by 1/2 in the image signal processing unit, and 1 /
A switching circuit for selectively switching between the output of the divide-by-2 circuit and the output of the adder circuit is provided, and the output of the adder circuit is selected in a single solid-state image pickup device alone.
A switching circuit control means for selecting the output of the 1/2 division circuit is provided in the connection portion which partially overlaps, and in the invention according to claim 6, the read effective pixel portion of each solid-state image pickup element in the image pickup portion is arranged respectively. Of the optical position relationship, and the reflector is a quadrangular pyramid prism mirror, and the image signal added by the adder circuit is multiplied by 1/2 in the image signal processing unit. A division circuit, a 1/4 division circuit that multiplies the image signals added by the addition circuit by 1/4, an output of the 1/2 division circuit, an output of the 1/4 division circuit, and an output of the addition circuit are selected. And a switching circuit for switching output is provided to select the output of the adder circuit in a single solid-state image pickup device alone, and a 1/2 division circuit in a connection part that partially overlaps in the horizontal and vertical directions. Select the output of In connection portion having a partially overlap in horizontal direction and the vertical direction is provided a switching circuit control means for selecting the output of the 1/4 dividing circuit.

[0013]

According to the first aspect of the present invention, one screen necessary for synthesizing the output images from the solid-state image pickup devices with respect to the image pickup unit capable of reading at a high resolution, which is a multiple of the number of the solid-state image pickup devices. Utilizing an image data storage circuit and utilizing an interlace method when storing / reading an image signal to / from these one-screen image data storage circuits, to make the currently stored field and the output field different between odd and even fields. This makes it possible to combine images for one screen with a simple control structure.

In particular, according to the second aspect of the present invention, regarding the corresponding read effective pixel, only the image signal of its own solid-state image pickup device is made effective, and those by other solid-state image pickup devices are treated as zero, whereby the adder circuit is added. The simple processing by

Here, a mirror image is output in such processing, but according to the third or fourth aspect of the present invention, the order of storing or reading is reversed in the horizontal direction or the vertical direction. A normal image output can be easily obtained. The structure for that purpose only needs to utilize the one-screen image data storage circuit and the interlace system originally required for each solid-state image pickup device, and to add the sequence control means for converting the mirror image data to the normal image.

Further, according to the invention of claim 5 or 6, since the arrangement of the read effective pixel portions of the respective solid-state image pickup elements is made to overlap with each other, the mutual positional relationship need not be accurately adjusted. However, at this time, a 1/2 division circuit or a 1/4 division circuit is provided for the output of the addition circuit, and in the overlapping read portion in the horizontal direction and the vertical direction, or in the overlapping read portion in the horizontal direction and the vertical direction, these By outputting the averaged image signal by the division circuit of (1), it is possible to perform the unobtrusive synthesizing process of the boundary portion.

[0017]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS A first embodiment of the present invention will be described with reference to FIGS. The image pickup apparatus of this embodiment includes an image pickup section 1 as shown in FIG. 2 and an image signal processing section 2 as shown in FIG. First, the image pickup unit 1 will be described. In this example, four solid-state image pickup devices 3A to 3D are used to read an image for one screen, and the optical arrangement relationship of these four solid-state image pickup devices 3A to 3D is shown in FIG. here,
In each of the solid-state image pickup devices 3A to 3D, the number of effective read pixels is 512 in the horizontal direction (H) and 490 in the vertical direction (V). In FIG. Only the part is shown in a rectangular shape. The arrow S in the figure indicates the reading and scanning direction of each of the solid-state image pickup devices 3A to 3D. Therefore, in the present embodiment, the image pickup area for one screen area is optically divided into four, and each image pickup area is assigned to the read effective pixel portions of the four solid-state image pickup elements 3A to 3D, and optically viewed from each other. They are arranged so that they can be read in an adjacent state.

Such four solid-state image pickup devices 3A to 3D
As shown in FIG. 2, the image pickup unit 1 that realizes the optical arrangement relationship of (1) includes an image pickup lens (zoom lens) 4 that forms an optical image of reflected light from a subject (original), and on the optical axis at the subsequent stage. A quadrangular pyramid prism 5 as a reflector with the apex placed on the
It is configured with. That is, the quadrangular pyramid prism 5 has reflecting surfaces 5A to 5D composed of four triangular conical surfaces, and reflects an optical image corresponding to a subject in four divisions with the reflecting surfaces 5A to 5D as the center. Here, each of the reflecting surfaces 5A to 5D is arranged in a state of being rotated by 45 ° around the optical axis with respect to the subject. Further, the inclination angles of the reflecting surfaces 5A to 5D are also formed to be 45 ° with respect to the optical axis. At this time, the inclination angles of the reflecting surfaces 5A to 5D are 45 ° with respect to the optical axis.
Therefore, the reflected optical axis is orthogonal to the optical axis of the imaging lens 4,
The light receiving surfaces of the solid-state image pickup devices 3A to 3D are parallel to the optical axis of the image pickup lens 4, and the arrangement around the quadrangular pyramid prism 4 becomes easy. In addition, since the divided light image is received by the quadrangular pyramid prism 4 and forms a rectangular area image, it can be read by a normal solid-state image sensor having a rectangular effective pixel portion. At this time, the solid-state image pickup devices 3A to 3D have their respective reflection surfaces 5A to 5D.
It is arranged at a position to receive a reflected light image by 5D, that is, a light image of only a different imaging region obtained by dividing one screen region into quarters as shown in FIG. Therefore, by performing a combining process on the image signals divided and read by each of the solid-state image pickup devices 3A to 3D, the entire one screen can be read.

According to the structure of the image pickup section 1 as described above, one image pickup area is expanded four times as much as one screen area as compared with the case where one screen receives light only by one solid-state image pickup element. Thus, the light is received by, which means that the image can be read with a resolution of 4 times. At this time, since there is no overlap at the level of one pixel in each image pickup region, it is not affected by the size of the light receiving portion of each solid-state image pickup device 3A to 3D.

Now, the image signal processing unit 2 for performing the combining process will be described. First, prior to the configuration of the image signal processing unit 2 of the present embodiment, an image signal obtained by this type of image pickup unit will be examined. For example, according to Japanese Patent Laid-Open No. 63-131465 as an image pickup apparatus of this type, an optical image obtained through an image pickup lens is divided into a plurality of images, and the image of the divided object image is received by each solid-state image pickup device. An image signal indicating a subject image formed by the combining unit is output, and the image combining unit processes the two storage units and the time delay (shift) at the time of reading. However, in the case of the configuration of the image pickup unit 1 as in the present embodiment, for example, on the solid-state image pickup devices 3A to 3D, the reflection surfaces 5A to 5D of the quadrangular pyramid prism 5 make an odd number of reflections (here, left and right). (Or inverted upside down) is imaged, so if such an image signal is output as it is, a left-right or upside-down image is obtained. In particular, in the four solid-state image pickup devices 3A to 3D as in the present embodiment, the image composition output of one screen is not sufficient only with the time delay of the data at the time of reading, but there is nothing about the image composition processing. It is not mentioned.

Here, a general theory will be considered. Normally, Fig. 5 (a)
In order to convert the image signal of the mirror image as shown in Fig. 2 to the normal image as shown in Fig. 2B, the output order of the images is reversed in the horizontal direction (the line data output from the solid-state imaging device is changed within 1 line). , The output is started from the last image data side, and the first data is output last). Such a reversal process requires a line data memory for two lines or more.

On the other hand, an image signal of a mirror image as shown in FIG. 5 (a) can be formed into a normal image by reversing the output order in the vertical direction as shown in FIG. In the case of the reply signal, an image data memory of one frame or more is required, and the increase in the device cost and the increase in the circuit scale cannot be ignored.

Therefore, when the image signal processing unit 2 of the present embodiment is constructed, in consideration of such a point, in order to synthesize and output the image signals of the four solid-state image pickup devices 3A to 3D, originally, Since an image data memory of one screen or more is required, a portion for converting a mirror image signal into a normal image by using the one-screen image data storage circuits (frame memories) 6A to 6D prepared for each of the solid-state imaging devices 3A to 3D. Is added so that an increase in device cost and an increase in circuit scale can be avoided.

In the image signal processing unit 2, basically, the solid-state image pickup devices 3A to 3 are stored in the frame memories 6A to 6D, respectively.
The image output from D is simultaneously output and stored. At this time, the image combining process is performed at the time of writing or reading.

The frame memory 6 (6A to 6D) for this purpose
2 is the same, and A to D are omitted and shown) will be described with reference to FIG. Each frame memory 6 is divided into an odd-numbered field memory 7 and an even-numbered field memory 8, and an input data selector (SEL = input / output switching control unit) for switching which of the outputs of the solid-state imaging device 3 is stored on the input side. 9 is provided, and the memory 7,
An output data selector (SEL = input / output switching control unit) 10 for switching which content of 8 is read is provided. Further, for each of the memories 7 and 8, an address counter 1 for odd and even field memories which serves as sequence control means.
1 and 12 are connected and manage the memory addresses so that they are stored in reverse order in the horizontal direction when storing data. A frame memory control circuit 13 is provided as a storage circuit control means for controlling the selectors 9 and 10 and the counters 11 and 12.

In such a structure, the solid-state image pickup device 3
, The image data is output by the interlace system. When this image signal is in the even field, the input data selector 9 selects the even field memory 8 side and stores it in the even field memory 8. At this time, since the even field memory address counter 12 is controlled so as to sequentially decrease from the set value for each line, the image signals of each line in the even field memory 8 are in the reverse order in the address direction in the horizontal direction. It will be remembered. In parallel with such a storage operation, the output data selector 10 selects the odd field memory 7 side, the address of the odd field memory 11 is controlled in the ascending order, and the odd field memory 7 shifts to the odd field memory. The image signal is output as normal image data.

As described above, when storing / reading the image signal from / to the frame memory 6, since the fields of the image signal currently being stored and the image signal being read and output are odd and even, they are different from each other. Has a simple structure that is easy to control.

Such operation is performed by each frame memory 6
The output of the four frame memories 6A to 6D is selectively controlled by the selector 15 under the control of the image signal processing control circuit 14 as shown in FIG. It is output as output.

FIG. 6 is a timing chart showing how necessary image signals are sequentially output in the block diagram structure shown in FIG. In the figure, each frame memory 6A-
Inputs and outputs for 6D are indicated by Ain to Din and Aout to Dout. As shown in the figure, in the first half of the frame image (upper half of the 4-split screen), the frame memory 6A outputs the first half data and the frame memory 6B outputs the latter half data in the same line. In the latter half (lower half of the 4-split screen), the frame memory 6C in the same line
Outputs the first half data and the frame memory 6D outputs the second half data, and the image signal processing control circuit 14 controls the outputs of the frame memories 6A to 6D.

As described above, according to the present embodiment, the four required for synthesizing the output images from the four solid-state image pickup devices 3A to 3D.
A normal image can be obtained with a simple configuration in which one frame memory 6A to 6D is used and the portions 11 and 12 for converting the mirror image output data from the solid-state image pickup devices 3A to 3D into a normal image are added thereto. Will be things.

In the above description, the storage address order of the image signals is reversed in the horizontal direction in order to make the mirror image a normal image (the reading address order may be reversed).
The storage order of the image signals may be reversed in the vertical direction.
For example, even field memory address counter 12
Means that the line address (usually using the upper bits of the address counter) decreases from the predetermined value by one line for each line. When storing line data, the address counter is sequentially incremented to increase the even field memory. In parallel with this, the odd-numbered field memory 7 controls the memory addresses in ascending order and reads the same to output a normal image.

Next, a second embodiment of the present invention will be described with reference to FIGS. The same parts as those shown in the above-mentioned embodiment are designated by the same reference numerals. As shown in FIG. 7, this embodiment is applied to an image pickup unit 1 having an optical arrangement in which the reading effective pixel portions of the four solid-state image pickup devices 3A to 3D are partially overlapped with each other at their connecting portions. It is a thing. In order to avoid overlapping of images in the connecting portions shown by hatching in the configuration of the image capturing unit 1 at the time of reading, basically, all of one or both of the connecting portions when synthesizing image signals are used. It is possible to secure the geometric continuity at the connection portion by cutting off each part of the above and performing relative shift correction on the cut-off pixels as an image signal. Connect the horizontal, vertical, and horizontal / vertical connections to 3'A + B, 3 '.
C + D, 3'A + C, 3'B + D, 3'A + B + C + D
Shall be represented by.

As described above, when the connection portions of the optical arrangements of the solid-state image pickup devices 3A to 3D are partially overlapped and read, the end portions of the read effective pixel portions of the solid-state image pickup devices 3A to 3D are accurately aligned. Even if it is not adjusted, the correction can be made in pixel units after reading. Even in this case, since the divided light image is received from each of the reflection surfaces 5A to 5D of the quadrangular pyramid prism mirror 5, and a rectangular area image is formed, a normal solid-state image sensor having a rectangular effective pixel section is used. Readable,
No complicated image processing is required.

By the way, in the case of the structure having such an overlapping connection portion, in the image synthesizing process of simply discarding one image signal as described above, the change of the image signal between the solid-state image pickup elements, especially the hue. As a result, the combined portion, that is, the boundary line is conspicuous. In this embodiment, the image signal processing unit 2 having a function of making the boundary line in such an overlapping connection portion inconspicuous is configured as shown in FIG.

That is, the same image is displayed at the connecting portion as 3'A +
A plurality of solid-state image pickup devices 6A as indicated by B, 3'C + D, etc.
6D, the output signal between the adjoining connecting portions, especially the horizontal connecting portion 3'A + B,
By averaging 3'C + D to obtain a composite output, the image of the boundary portion is improved and the boundary portion is made inconspicuous. Therefore, in the present embodiment, as shown in FIG. 8, an adder circuit 16 for adding all the image signals of the solid-state image pickup devices 6A to 6D is provided on the output side. Also, to the output side of the adder circuit 16 is connected a 1/2 divider circuit 17 which divides this output by 1/2.
A switching circuit 18 for selectively switching between the output of the / 2 division circuit 17 and the output of the addition circuit 16 is provided. Further, each frame memory 6A to 6D and this switching circuit 18
An image signal processing control circuit 19 for controlling the and is provided.

In such a configuration, the operation will be described with reference to FIG. 7, for example, in the read effective pixel section of the solid-state image sensor 3A alone, the image signal (contents of the frame memory 6A) of the solid-state image sensor 3A and zero. The data (the solid-state image sensor 3B is outside the effective image area and its reading is controlled so that the output of the frame memory 6B becomes zero) is added by the adder circuit 16, and the solid-state image sensor is directly passed through the switching circuit 18. The image signal of the 3A single portion is output. In the connection section 3'A + B, both the solid-state image pickup elements 3A and 3B are read effective pixel sections, and the image signals of the frame memories 6A and 6B are input to the adder circuit 16. The output of the adder circuit 16 is averaged to 1/2 by the division processing in the 1/2 divider circuit 17, and the image signal of the overlapping portion is output through the switching circuit 18. In the read effective pixel section of the solid-state image sensor 3B alone, the image signal of the solid-state image sensor 3B (contents of the frame memory 6B) and zero data (the solid-state image sensor 3A is outside the effective image area, and the output of the frame memory 6A is zero). (The reading is controlled so that the above) is added by the adding circuit 16 and the image signal of the single portion of the solid-state image pickup device 3B is output as it is through the switching circuit 18. Image processing on the solid-state image pickup devices 3C and 3D side is similarly performed. In this way, since the image signal subjected to the averaging process is output for the overlapping read portion in the horizontal direction, the boundary line becomes inconspicuous.

A portion to be read in duplicate in the vertical direction,
Regarding 3'A + C and 3'B + D, the contents of the frame memories 6A, 6C, 6B and 6D are added by the adder circuit 16 in each area and averaged by 1/2 by the 1/2 divider circuit 17. , Are sequentially output.

By the way, with only the above-mentioned structure, the portion 3'A + B + C + for overlapping reading in the horizontal and vertical directions is used.
Averaging processing cannot be performed on D. To perform the averaging, as shown by a broken line in FIG. 8, a 1/4 division circuit 20 is added to the output side of the addition circuit 16 and a switching circuit 18 is used to output the addition circuit 16 and the 1/2 division circuit 17. Either the output or the 1/4 division circuit 20 output may be selected.

As a result, the output of the adder circuit 16 is selected in the individual reading portion of each of the solid-state image pickup devices 3A to 3D, and is set to 1 in the overlapping reading portion in only one of the horizontal direction and the vertical direction.
By selecting the output of the / 2 division circuit 17 and the output of the 1/4 division circuit 20 in both the horizontal and vertical overlapping reading portions, a composite image for one screen in which the borderline is inconspicuous is obtained. Will be used.

FIG. 8 shows an example of the circuit configuration of the adder circuit 16 and the subsequent circuits including the 1/4 divider circuit 20. This is 1
1/2 division circuit 17 divides 1/2 by 1 bit shift,
The 1/4 division circuit 20 is realized by 1/4 division by 2-bit shift, and is configured integrally with the switching circuit 18, and is configured by three gate circuits 21, 22, and 23. These gate circuits 21, 22,
An output signal 23 is made valid or invalid by a switching signal from the image signal processing control circuit 19. At this time, the first gate circuit 21 outputs the upper 8 bits (D9 to D) of the input data (10 bits) from the adder circuit 16.
By making 2) an 8-bit output signal, 2-bit shift is executed and it becomes responsible for ¼ division. Similarly, the next gate circuit 22 receives bits (D8 to D8) other than the most significant bit (D9) and the least significant bit (D0) of the input data.
By shifting D1) to an 8-bit output signal, 1-bit shift is executed, and it becomes responsible for 1/2 division. The gate circuit 23 receives the lower 8 bits (D7 to D) of the input data.
(0) is directly used as an 8-bit output signal, so that the output of the adder circuit 16 is directly output.

Here, the output signals of the solid-state image pickup devices 3A to 3D are 8 bits, three of the output signals of the frame memories 6A to 6D are zero in the normal single reading effective pixel portion, and the adder circuit 16 is provided. The maximum output is a signal of 8 bits or less. Similarly, the horizontal or vertical duplication reading unit has a maximum of 9 bits or less, and the horizontal or vertical duplication reading unit has a maximum of 10 bits or less, which can handle all cases.

[0042]

Since the present invention is configured as described above, according to the invention of claim 1, the solid-state image pickup units for the solid-state image pickup devices capable of reading with high resolution, which is a multiple of the number of the solid-state image pickup devices, are used. The number of one-screen image data storage circuits necessary for synthesizing the output image from the element and the interlace method are used, and when the image signals are stored / read out to / from these one-screen image data storage circuits By combining the fields and the field being output by different image signal processing units for odd / even fields, an image signal processing unit having a simple control configuration can be used to enable proper image composition for one screen. be able to.

In particular, according to the second aspect of the invention, regarding the image combining processing, only the image signal of its own solid-state image pickup device is valid for the corresponding read effective pixels, and zero is obtained by other solid-state image pickup devices. By handling, it is possible to complete the simple combining process by the adder circuit.

Here, although a mirror image is output in such processing, according to the invention of claim 3 or 4, according to the invention in the horizontal direction or the vertical direction, the sequence control means stores the image in the one-screen image data storage circuit. Alternatively, the normal image output can be easily performed only by controlling the reading order in the reverse direction, and the configuration therefor is originally required for each solid-state imaging device.
Utilizing the screen image data storage circuit and interlace system,
It is only necessary to add a sequence control means for converting mirror image data to a normal image.

According to the fifth or sixth aspect of the present invention, since the read effective pixel portions of the solid-state image pickup elements are arranged so as to overlap each other, the mutual positional relationship need not be accurately adjusted. However, at this time, a 1/2 division circuit or a 1/4 division circuit is provided for the output of the addition circuit, and in the overlapping read portion in the horizontal direction and the vertical direction, or in the overlapping read portion in the horizontal direction and the vertical direction, these By outputting the averaged image signal by the division circuit of (1), it is possible to perform the inconspicuous synthesizing process of the boundary portion.

[Brief description of drawings]

FIG. 1 is a block diagram showing one frame memory configuration of a first embodiment of the present invention.

FIG. 2 is a perspective view showing a configuration of an image pickup unit.

FIG. 3 is a block diagram showing a configuration of an image signal processing unit.

FIG. 4 is a layout diagram showing a relative optical layout relationship of solid-state image pickup devices.

FIG. 5 is a schematic diagram showing a mirror image-normal image relationship.

FIG. 6 is a timing chart showing the operation of the image signal processing unit.

FIG. 7 is a layout diagram showing a relative optical layout relationship of the solid-state imaging device of the second embodiment of the present invention.

FIG. 8 is a block diagram showing a configuration of an image signal processing unit.

FIG. 9 is a block diagram showing a specific configuration example of the output side.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Image pick-up part 2 Image signal processing part 3A-3D Solid-state image pick-up element 4 Imaging lens 5 Reflector = 4-sided pyramid prism 5A-5D Reflective surface 6A-6D 1 screen image data storage circuit 9,10 Input / output switching control part 11,12 Sequence Control means 13 Storage circuit control circuit 14 Control means 16 Addition circuit 17 1/2 division circuit 18 Switching circuit 19 Switching circuit control means 20 1/4 division circuit

Claims (6)

[Claims] 1. An image pickup lens, a reflector having a plurality of reflecting surfaces arranged on an optical axis of the image pickup lens and dividing and reflecting an optical image transmitted through the image pickup lens, and the reflector is divided and reflected. The number of each solid-state image sensor corresponds to the number of each solid-state image sensor by providing an image pickup unit consisting of a plurality of solid-state image sensors that are arranged at optical positions that receive the optically different image areas in relatively adjacent states for each optical image. The same number of one-screen image data storage circuits and the image signals output from each solid-state image sensor in the interlace method are simultaneously applied to the corresponding one-screen image data storage circuits in an odd or even field in line units. The storage circuit control means has an input / output switching control unit for storing one screen image signal in a line unit from the other field different from the field in which the storage operation is being performed. An image pickup apparatus, comprising: an image signal processing section for synthesizing image signals from these one-screen image data storage circuits and outputting the resultant as a one-screen image signal. 2. An addition circuit for adding all 1-screen image signals from each 1-screen image data storage circuit to the image signal processing section, and a 1-screen image other than the 1-screen image data storage circuit corresponding to the corresponding read effective pixels. The image pickup apparatus according to claim 1, further comprising: a control unit that outputs the image signal of the data storage circuit to the addition circuit as zero. 3. The storage circuit control means has sequence control means for reversing the image signal sequence in the horizontal direction at the time of storing or reading the one-screen image data storage circuit. Imaging device. 4. The storage circuit control means has an order control means for reversing the image signal order in the vertical direction when storing or reading in each one-screen image data storage circuit. Imaging device. 5. The reading effective pixel section of each solid-state image pickup element in the image pickup section is partially overlapped by the connection section having an optical positional relationship, and at least two or more reflecting surfaces are provided in the horizontal direction. As a reflector, in the image signal processing unit,
The image signal added by the adding circuit is multiplied by 1/2
A division circuit for dividing by 2 and a switching circuit for selectively switching between the output of the 1/2 division circuit and the output of the adder circuit;
The output of the adder circuit is selected in the part of one solid-state image pickup device alone, while it is set to 1 in the connection part which partially overlaps.
4. The image pickup apparatus according to claim 2, further comprising switching circuit control means for selecting an output of the / 2 division circuit. 6. The image signal processing, wherein the arrangement of the reading effective pixel portions of each solid-state image pickup element in the image pickup portion is partially overlapped with each other in the connection portion of each optical positional relationship, and the reflector is a quadrangular pyramid prism mirror. In the unit, a 1/2 division circuit for multiplying the image signal added by the addition circuit by 1/2, a 1/4 division circuit for multiplying the image signal added by the addition circuit by 1/4, and a 1/2 division A switching circuit for selectively switching and outputting the output of the circuit, the output of the 1/4 division circuit, and the output of the addition circuit is provided, and the output of the addition circuit is selected in the portion of one solid-state image pickup device alone. The output of the 1/2 divider circuit is selected at the connection portion that partially overlaps in the horizontal and vertical directions, and the output of the 1/4 division circuit is selected at the connection portion that partially overlaps in the horizontal and vertical directions. Switching circuit control hand to select The image pickup device according to claim 2, 3 or 4, wherein a step is provided.