JP2964502B2 - Video processing equipment - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a video processing apparatus that generates a video signal for enlarged display by performing line interpolation.

[Prior Art] In recent years, a small-sized imaging device can be realized by using a solid-state imaging device such as a CCD as an imaging unit.

Also, the image signal from the imaging device is processed by the video processing device.
It is converted to a standard video signal and displayed on a color monitor.

Some of the image processing apparatuses have an enlargement processing function of performing line interpolation and enlarging the image to be displayed on a monitor screen.

FIG. 9 shows an imaging system 1 having a conventional video processing device.
Is shown.

An optical image of the object is formed on the CCD 3 by the imaging lens 2, photoelectrically converted, and stored as signal charges. The video signal (image signal) read from the CCD 3 by the drive signal from the drive circuit 4 is input to a pre-processing circuit 5, where the luminance signal Y and the color difference signal C are demodulated. A / D for digital signal
Is converted. The digital luminance signal data is input to the first memory block 6 and the digital chrominance signal data is input to the second memory block 7. After the processing such as freeze or enlargement is performed according to the selection by the freeze switch 8 or the enlargement switch 9, Are input to the post-processing circuit 11. Luminance signal data input by the post-processing circuit 11,
The color difference signal data is modulated to generate an NTSC signal, which is output to a color monitor (not shown).

The first and second memory blocks 6 and 7 have the same configuration, and one of the first memory blocks 6 will be described.

At this time, the input signal is input to the A field memory 12 if it is an A field and to the B field memory 13 if it is a B field memory.

These field memories 12, 13 are controlled by a memory controller 14.

The output signals of the A field memory 12 and the B field memory 13 are delayed by a 1H (one horizontal) period by a 1H delay circuit 15.
, An adder 16 and a multiplexer 17, and the output of the 1H delay circuit 15 is added to a signal not delayed by the adder 16 and input to the other terminal of the multiplexer 17. The output of the multiplexer 17 is input to the post-processing circuit 11.

As the output of the adder 16, signal data of the upper 8 bits including Carry is input to the multiplexer 17.

The memory controller 14 of the system 1 has a configuration shown in FIG.

The field discrimination signal ▼ is applied as an output control signal ▼ to the A field memory 12 via the inverter 18, and the output control signal ▼ is applied to the B field memory 13 without passing through the inverter 18. . That is, the A and B field memories 12, 13 output signal data alternately.

Further, a freeze instruction signal ▲ ▼ output based on the operation of the freeze switch 8 and an enlargement instruction signal ▲ ▼ output based on the operation of the enlargement switch 9 are input to the memory driver 19, and the chip select from the memory driver 19 is performed. (CS), write select (WS), write enable (WE), read enable (RE), address (ADR), and other signals are controlled, and signals corresponding to freeze operation and enlargement operation are output from memory blocks 6 and 7. Output. Note that the output signal of the memory controller 14 is also used to control switching of the multiplexer 17.

In the memory controller 14 having the configuration shown in FIG. 10, the memory driver 19 controls the A-field memory 12 and the B-field memory 13 in response to the enlargement instruction signal ▼, so that two lines of the signal data are the same as shown in FIG. While reading things, line interpolation is performed to enlarge.

That is, the signal A1n along the first scanning line of the A field
And the signal A2n along the next scan line in this A field
An intermediate signal (A1n + A2n) / 2 between these is generated by the average value of

Similarly, in the B field, the signal B1n along the first scanning line
And the signal B2n along the next scanning line is averaged to generate an interpolation signal (B1n + B2n) / 2.

[Problems to be Solved by the Invention] For this reason, as shown in FIG.
Points a, b, c, and d representing oblique lines become jagged (stepped) due to this interpolation.

In other words, in this conventional example, the interpolation is performed in each field, so that the interpolation becomes coarse, and the interpolation of the oblique line cannot be performed so as to become a smooth oblique line because the positions in the A field and the B field are slightly shifted.

If the interpolation method of the B field is slightly changed and interpolation is performed by adding 1/4 and 3/4, this point can be solved, but there is a disadvantage that the interpolation circuit in that case becomes complicated.

It should be noted that Japanese Patent Application Laid-Open No. 1-109972 discloses a conventional example in which signals of a plurality of lines are read out for each field and enlarged. This conventional example cannot solve the above-mentioned disadvantage.

The present invention has been made in view of the above points, and has as its object to provide a video processing apparatus capable of obtaining a high-quality enlarged image at the time of enlargement with a simple circuit configuration.

[Means for Solving the Problem and Action] The video processing apparatus according to the present invention has memory means for storing a video signal, performs interpolation processing on the video signal read from the memory means, and expands the image signal to the display means. A video signal processing apparatus capable of displaying a moving image and an enlarged still image, comprising: a memory means capable of storing a video signal for at least one frame including even fields and odd fields; Display image instructing means capable of selecting and instructing an enlarged moving image mode for displaying the expanded moving image and an enlarged still image mode for displaying the enlarged still image, and adjacent images in the even field in the enlarged moving image mode. Moving image supplementation is performed based on a signal between signal lines or between adjacent video signal lines in the odd field. An interpolation signal for generating a still image interpolation signal based on a signal between adjacent video signal lines in a video signal of one frame including the even field and the odd field in the enlarged still image mode. Generating means, and signal processing means for processing the moving image interpolation signal or the still image interpolation signal output from the interpolation signal generating means and displaying an enlarged image on the display means. And

EXAMPLES Hereinafter, the present invention will be described specifically with reference to the drawings.

1 to 6 relate to a first embodiment of the present invention, FIG. 1 is a configuration diagram of a memory controller in the first embodiment, and FIG. 2 is a configuration diagram showing an imaging system having the first embodiment. FIG. 3 is an explanatory view showing how two field memories perform writing / reading alternately in a normal mode;
FIG. 4 is an explanatory view showing video signal data of each part in the enlargement mode, FIG. 5 is an explanatory view showing video signal data of each part in the enlargement freeze mode, and FIG. 6 is enlarged by line interpolation in the enlargement freeze mode. FIG. 11 is an explanatory diagram of a state of being displayed.

2. Imaging system provided with the first embodiment as shown in FIG.
21 is configured using a memory controller 22 having a configuration different from the memory controller 14 in the conventional example of FIG.

 Other components have the same configuration and are denoted by the same reference numerals.

FIG. 1 shows the configuration of the memory controller 22 used in the first embodiment.

Freeze instruction signal ▲ ▼ and enlargement instruction signal ▲
▼ is input to the same memory driver 19 as in the conventional example shown in FIG.
The address of the field memory 13 is controlled.

The horizontal synchronizing signal ▼ is input to the T-type flip-flop 23, and a signal which is alternately inverted from the output terminal Q and the inverted output terminal is output to the multiplexer 24 every 1H by the signal ▲.

The T-type flip-flop 23 outputs a vertical synchronizing signal ▲ ▼
Is cleared.

The multiplexer 24 supplies a field discrimination signal ▲
▼ is also entered.

That is, a field discrimination signal ▼ is applied to the contact a1 of the multiplexer 24 via the inverter 25, and a field discrimination signal 接点 is applied to the contact a2 which is switched in conjunction with the contact a1. The output terminal Q and the inverted output terminal of the T-type flip-flop 23 are connected to the contacts b1 and b2 of the multiplexer, respectively. When the signal applied to the switching control terminal is "H" (or "1"), the multiplexer 24 turns on the contacts b1 and b2 as shown in FIG.
In this state, the A field memory 12 and the B field memory 13 output control each 1H.
▼ is output. Accordingly, adjacent line signal data is output from the A field 12 and the B field 13 for each line.

On the other hand, when the switching control signal is "L" (or "0"), the contacts a1 and a2 are turned on, and the output control signal ▲ ▼ is output to the A field memory 12 and the B field memory 13 for each field. You. Therefore, A field memory 12 or B field memory
Thirteen signal data are output.

The field discrimination signal 信号, the freeze instruction signal ▼, and the enlargement instruction signal 入 力 are input as address signals to the P-ROM 26, and data corresponding to various modes are output from the two output terminals D0 and D1 according to these three signals. Is output. The data output from the output terminal D0 is output as a signal for controlling the multiplexer 17, and the output terminal D1
Is output to the switching control terminal of the multiplexer 24 as a switching control signal.

The relation between the address data to the address end of the P-ROM 26 and the output data is shown in a table.

As can be seen from the remarks column of this table, when both the address data A1 and A2 are "1", the normal moving image mode is set. In this mode, the signal of "0" is applied to the multiplexer 24 from the output terminal D1. And the contacts a1 and a2 are turned on. In this state, the signal data is sequentially output from the A field memory 12 and the B field memory 13 for each field.

This is shown in FIG. FIG. 3 (a) shows that an output control signal
Is input, and in this state, the written signal data is read from the B field memory 13.

On the other hand, a write enable signal is applied to the A field memory 12 (in the field at this time), and input signal data is written to the A field memory 12.

In the next field, the states of the A field memory 12 and the B field memory 13 are switched as shown in FIG. 3 (b), signal data is read from the A field memory 12, and the B field memory 13 is stored in the B field memory 13. The input signal data is written.

In the moving image mode, a signal of "1" is output from the output terminal D0 to the control terminal of the multiplexer 17, and the contact b is turned on.
Therefore, in the normal mode (moving image mode), video signal data is read from the A field memory 12 and the B field memory 13 for each field, and output to the post-processing circuit 11 via the contact b. That is, a normal interlaced video signal is output, and interlaced display is performed.

In the table, in the freeze mode when the address signal A1 is "0" and the address signal A2 is "1", the P-ROM 26
Is the same as that in the moving image mode, but the memory driver 19 deactivates the write enable WE by the freeze instruction signal ▲ ▼.

Therefore, writing to the A-field memory 12 and the B-field memory 13 is prohibited, and the reading is alternately read from the A-field memory 12 and the B-field memory 13 for each field as in the case of the moving image, and the monitor screen freezes. The image for one frame is repeatedly displayed in the interlaced display.

Next, in the table, the address signal A1 is “1”, and the address signal A2 is twice as large as that in the case of “0” (A0 is the same whether “0” or “1”). The data is "0" as in the normal mode, and the signal data of the A field memory 12 and the B field memory 3 is output for each field.

In this mode, the data from the output terminal D0 is "0" and the contact point a of the multiplexer 17 is turned on.

In this enlargement mode, the A field memory 12 or B
The read clock to the field memory 13 (described in FIG. 4 with the A field) is doubled, and FIG.
As shown in (2), the same horizontal line is read out two by two.

That is, in the 0th and 1st horizontal line periods, the signal data A stored in the 1st horizontal line of the A field memory 12A.
, Are read twice, and during the second and third horizontal line periods, the signal data A2 stored in the second horizontal line
1, A22, A23,... Are read twice. Thus, the signal data read from the A field memory 12 is
Since the signal is delayed by 1H period by the 1H delay circuit 15, the signal data shown in FIG. 4 (b) appears at the output terminal of this circuit 15 in time series.

The signal data shown in FIGS. 4A and 4B are added by the adder 16 to become the signal data shown in FIG. 4C (in FIG. 4C, the signal data is divided by 2). It is output to the post-processing circuit 11 via the contact a which is turned on.

Next, in the table, in the enlarged freeze mode (enlarged still image mode) when both the address signals A1 and A2 are “0”,
The output terminal D1 becomes “1”, and the multiplexer 24 connects the contacts b1 and b2
Turns on. In this state, signal data of one horizontal line is read from the A field memory 12 and the B field memory 13 every horizontal period. Accordingly, in this case, the signal data output from the output terminals of the A field memory 12 and the B field memory 13 are as shown in FIG. 5 (a).

When the signal data A11, A12, A13,... Stored in the first horizontal line of the A field memory 12 are read out in the first horizontal period, the signal data B11, B12,. B13, ... are read, and then A21, A22, A23,
, B21, B22, B23, ... are read out. In the field where the address signal A1 is “0” and the address signal A0 is “1”,
As can be seen from the table, since the signal from the output terminal D0 is "1" and the contact b of the multiplexer 17 is on, the signal data A11, A12, A13,... B11 shown in FIG. , B12, B13,
Are sequentially output to the post-processing circuit 11. Therefore,
In this field (in the mode in which the contact points a1 and a2 of the multiplexer 24 are selected, since the field is the A field, the field is described as the A field), the signal is indicated by a solid line in FIG.
A1n (representing A11, A12, ...) and B1n, A2n, ... are displayed in an interlaced manner on the monitor screen.

The signal data shown in FIG. 5A is output from the 1H delay circuit 15 to the output terminal of the circuit 15 as shown in FIG. 5B.

The signal data shown in FIGS. 5A and 5B are added by the adder 16, so that the interpolation signal data (A11 + B11) / 2, (A12 + B12) / 2,... Shown in FIG. Generated sequentially. The interpolation signal data shown in FIG. 5 (c) is not used in the A field, but in the B field, as shown in the table, the address signal A0 is "0", so that the output terminal D0 becomes "0", and the multiplexer 17 outputs. Is turned on, so that the signal data shown in FIG. 5A is used instead of the signal data shown in FIG.
Are sequentially output. That is, as shown by the dotted line in FIG. 6, (A1n + B1n) / 2, (B1n + A2n) / 2,.
Are interlaced on the monitor screen.

With respect to the points x1, x2, x3... Representing the oblique lines on the solid line in FIG. 6, the interpolation points x1 ', x2', x3 '... are (x1 + x2) /
Since it is generated by interpolation such as 2, (x2 + x3) / 2,..., Smooth interpolation can be performed. Therefore, a high-quality enlarged frozen image can be obtained with a simple configuration.

FIG. 7 shows a video processing apparatus 31 according to a second embodiment of the present invention.

The second embodiment differs from the first embodiment in the configuration of the memory blocks 6 and 7. Instead of two field memories 12, 13 in each memory block (eg 6),
A memory 32 having a storage capacity for two fields is used, and the most significant bit A14 in the memory 32 (see FIG. 8)
A field section corresponding to A and B field memories 12 and 13
Writing and reading to and from the 33 and B field portions 34 are performed.

FIG. 8 shows the configuration of the memory controller 35 for controlling the memory 32.

As in FIG. 1, the horizontal synchronizing signal ▼ is input to a T-type flip-flop 23 which is reset by the vertical synchronizing signal ▼. The output terminal Q of this T-type flip-flop 23
Is connected to the contact b of the first multiplexer 24A, and the contact a is supplied with a field determination signal
Is applied via The output terminal of the first multiplexer 24A is connected to the contact point a of the second multiplexer 24B, and the contact signal b is applied to the contact point b.

The output of the second multiplexer 24B becomes the address signal A14 of the most significant bit of the memory 32.

As in the case of FIG. 1, the discrimination signal ▲ ▼, the freeze instruction signal ▲ ▼, and the enlargement instruction signal ▲ ▼
And the output of the output terminal D0 is applied to the control terminal of the multiplexer 17. This P-ROM26
The output of the output terminal D1 is applied to the control terminal of the first multiplexer 24A, and the contact b is turned on at "1".

Both instruction signals ▲ ▼, ▲ ▼ are input to the memory driver 19, and CS, WS, WE, RE, address signals
A0 to A13 are output to the memory 32.

Note that the write enable signal WE is supplied to the second multiplexer.
It is applied to the control terminal of 24B, and the contact b is turned on at "1". The A field section 33 (or B field) on the side where this signal WE is not input
Field section 34) is read, and B
Writing is performed in the field section 34 (or the A field section 33).

 Other configurations are the same as in the first embodiment.

In the second embodiment, the most significant bit address signal A14 at the time of reading is generated instead of the output control signal ▲ ▼ to the A field memory 12A and the B field memory 13 in the first embodiment, and the same function is provided. I'm trying to do it.

 Therefore, the operation and effect are the same as those of the first embodiment.

Each of the above embodiments has been described with respect to a case where the magnification is doubled (length ratio). However, the present invention can be applied to other magnifications such as triple or quadruple.

[Effects of the Invention] As described above, according to the present invention, an interpolation signal corresponding to each of the enlarged moving image mode and the enlarged still image mode can be obtained, and a high-quality enlarged image suitable for each mode can be obtained. it can.

[Brief description of the drawings]

FIGS. 1 to 6 relate to a first embodiment of the present invention.
FIG. 2 is a configuration diagram of a memory controller according to the first embodiment,
FIG. 2 is a block diagram showing a conventional image pickup system, FIG. 3 is an explanatory diagram showing how two field memories are alternately written / read in a normal mode, and FIG. 4 is each section in an enlarged mode. FIG. 5 is an explanatory diagram showing video signal data of each part in an enlarged freeze mode, FIG. 6 is an explanatory diagram showing a state in which the image is enlarged and displayed by line interpolation in an enlarged freeze mode, and FIG. 7 is a block diagram of a second embodiment of the present invention, FIG. 8 is a block diagram of a memory controller in the second embodiment, FIG. 9 is a block diagram of a conventional imaging system, and FIG. 10 is FIG. FIG. 11 is a diagram showing a configuration of a memory controller used, and FIG. 11 is an explanatory diagram showing a state in which the image is enlarged and displayed by line interpolation according to a conventional example. 1 ... CCD, 5 ... Preprocessing circuit 6,7 ... Memory block 11 ... Post processing circuit 12,13 ... Field memory 15 ... 1H delay circuit, 16 ... Adder 17 ... Multiplexer 22 ... Memory controller 23 Flip-flop, 24 Multiplexer 26 P-ROM

Claims (1)

(57) [Claims] 1. A video signal having a memory means for storing a video signal, wherein the video signal read from the memory means is interpolated to display an enlarged moving image and an enlarged still image on a display means. In the processing device, a memory means capable of storing a video signal for at least one frame including at least an even field and an odd field; an enlarged moving image mode for displaying at least the enlarged moving image on the display means; Display image instructing means capable of selecting and instructing an enlarged still image mode for displaying a still image; and in the enlarged moving image mode, between adjacent video signal lines in the even field or between adjacent video signal lines in the odd field. And generating an interpolation signal for a moving image based on the signal of the even number. And an interpolation signal generating means for generating an interpolation signal for a still image based on a signal between adjacent video signal lines in a video signal of one frame composed of a field and the odd field; And a signal processing means for processing the interpolation signal for a moving image or the interpolation signal for a still image and displaying an enlarged image on the display means.