JPH03153297A - Video processor - Google Patents

Abstract

PURPOSE:To obtain an enlarged freeze image of high picture quality by providing an enlarged display interpolating means which performs line interpolation between adjacent video signal lines in even and odd fields. CONSTITUTION:An adder 16 adds signal data (a) and (b) to generate interpolation signal data C in order. The interpolation signal data C is not used in a field A, but in a field B, an output terminal DO becomes 'O' since an address signal AO is 'O', and then the contact (a) of a multiplexer 17 is made, so the interpolation signal data is outputted in order to make an interlaced display on a monitor screen. Namely, interpolation points X1' - X3'... are interpolated smoothly like (X1+X2)/2, (X2+X3)/2... for points X1 - X3.... Consequently, the enlarged freeze image of high picture quality is obtained with the simple constitution.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Application in IL Business] The present invention relates to a video processing device that performs line interpolation to generate a video signal for enlarged display.

[Prior art] In recent years, solid-state mechanical devices such as COD have been developed rapidly. It has become possible to realize a compact image carrying device by using this method.

Further, the image signal from the image carrier is converted into a standard video signal by a video processing device and displayed on a color monitor.

Some of the video processing devices described above are equipped with an enlargement processing function that performs line interpolation to enlarge the image and display it on a monitor screen.

FIG. 9 shows an imaging system 1 equipped with a conventional video processing device.

An optical image of the object is formed on the CCD 3 by the me lens 2, photoelectrically converted, and stored as signal charges. The video signal (image signal) read out from the CCD 3 by the drive signal from the drive circuit 4 is input to the preprocessing circuit 5, which demodulates the R degree signal Y and the color difference signal C, and further demodulates the R degree signal Y and the color difference signal C. It is A/D converted into a digital signal. This digital color difference signal data is input to the first memory block 6, the digital color difference signal data is input to the second memory block 7, and the freeze switch 8
Alternatively, after processing such as freezing and enlarging is performed according to the selection by the enlargement switch 9, the image is input to the post-processing circuit 11. The post processing circuit 11 modulates the input luminance signal data and color difference signal data to generate an NTSC signal and outputs it to a color monitor (not shown).

The first and second memory blocks 6, 7 have the same configuration, and only one of the first memory blocks 6, 6 will be described.

At that time, manually inputted No. 15 is input into the A field memory 12 if it is a Δ field, and into the B field memory 13 if it is a B field memory.

These field memories 12,13 are controlled by a memory controller 14.

1 A field memory 12 and 8 field memory 13
The output signal of
It is configured so that it can be input to the extension circuit 15, the adder/!A 16, and the multiplexer 17. The output of this multiplexer 17 is input to the post-processing circuit 11.

Incidentally, the output of the adder 16 is inputted to the multiplexer 17 as the upper 8 bits of signal data including Carry.

The memory controller 14 of the system 1 has the configuration shown in FIG. 10.

Field discrimination @FLD is applied as an output control signal OC to the A field memory 12 via the inverter 18, and an output control signal OC is applied to the B field memory 13 without passing through the inverter 18. In other words, signal data is alternately outputted to the A and 8 field memories 12 and 13.

Further, the freeze instruction signal FR outputted based on the operation of the freeze switch 8 and the enlargement instruction signal ENL outputted based on the operation of the enlargement switch 9 are input to the memory driver 19, and from the memory driver 19 the chip select (
C8), write select (WS), write enable (
WE), RE (RE), ADDRESS (ADR)
), etc., so that signals corresponding to the freeze operation and enlargement operation are output from the memory block 6.7. Incidentally, the output signal of the memory controller 14 is also used for the switching of the multiplexer 17 at -IIIl.

In the memory controller 14 having the single configuration shown in FIG. 10, the memory driver 19 controls the A field memory 12 and the B field memory 13 according to the enlargement instruction signal ENL, so that two lines of signal data are the same as shown in FIG. While reading out the object, perform line interpolation and enlarge it.

That is, the signal Q A along the first scan line of the A field
1n and the signal A2n along the next scanning line in this A field, and the intermediate interpolated signal (A1
n+A2n)/2 is generated.

Similarly, in the B field, the signal Bln along the first scanning line
An interpolation signal (B1n+82n)/2 is generated by averaging the signal j5B2n along the next scanning line.

[Problems that ye Ming attempts to solve] For this reason, as shown in the 11th WA, not only is the interpolation rough, but the points a, b, c, and d representing diagonal lines are jagged (step-like) due to this interpolation. Put it away.

That is, in this conventional example, since interpolation is performed for each field, the interpolation is rough, and the reason why it is not possible to interpolate the diagonal lines so that they become smooth diagonal lines is because the positions of the A field and the 8th field are slightly shifted.

By slightly changing the B field interpolation method, 1/4 and 374
This problem can be solved by performing interpolation that adds 1, but the disadvantage is that the interpolation circuit in that case becomes complicated.

Incidentally, Japanese Patent Laid-Open No. 1-109972 also discloses a conventional example in which signals of a plurality of lines are read out and enlarged for each field. This conventional example also cannot solve the above-mentioned drawbacks.

The present invention has been made in view of the above-mentioned points, and it is an object of the present invention to provide a video processing device that can obtain a high-quality enlarged image during enlargement using an hour wheel circuit configuration.

[Means and effects for solving the problem] In the present invention, when enlarging a still image, there is provided a means for alternately reading out video signals of two fields every horizontal period, and a means for reading out video signals of two fields alternately every horizontal period, and reading out adjacent video signals of these two fields. By providing a line interpolation means for performing line interpolation between one line of the image, it is possible to obtain a high-quality enlarged still image with an asymmetrical configuration and without any step-like appearance even in diagonal areas. .

[Example 1 Hereinafter, the present invention will be specifically explained with reference to the drawings.

Figures 1 to 6 relate to the first embodiment of the present invention.
The figure is a configuration diagram of the memory controller in the first embodiment.
FIG. 2 is a configuration diagram showing an imaging system equipped with the first embodiment, FIG. 3 is an explanatory diagram showing how two field memories are alternately read/loaded in the normal mode, and FIG.
The figure is a 112-color diagram showing the video signal data of each part in enlargement mode, Figure 5 is an explanatory diagram without showing the video signal data of each part in enlargement freeze mode, and Figure 6 is enlarged by line interpolation in enlargement freeze mode. FIG. 3 is an explanatory diagram of how it is displayed.

Imaging system 2 equipped with the first embodiment as shown in FIG.
1 is a memory controller [1-ra 1] in the conventional example shown in FIG.
The memory controller 22 is configured using a memory controller 22 having a configuration different from that of the memory controller 4.

The rest has the same configuration and is indicated by the same reference numerals.

FIG. 1 shows the configuration of the memory controller 22 used in this first embodiment.

The freeze instruction signal FR and the enlargement instruction signal ENL are the 10th
The data is input to the same memory driver 19 as in the conventional example shown in the figure, and this memory driver 19 controls the addresses of the A field memory 12 and the B field memory 13, etc.

The horizontal synchronizing signal HD is input to the T-type flip 70 tube 23, and the signal 11D outputs QQ every 11-1 (for inversion)
[An alternately inverted signal from 7G is output to the multiplexer 24.

The above Tffiff flip-flop vertical synchronization signal VD
It is cleared with .

The multiplexer 24 has a field discrimination signal FLD.
is also input.

That is, the field discrimination signal FLD is applied to the contact a1 of the multiplexer 24 via the inverter 25, and the field discrimination signal FLD is applied to the contact a2, which is switched in conjunction with the contact a1. Also, 1-type flip 70
The output end Q and the inverted output end of the knob 23 are connected to contacts b1 and b2 of the multiplexer, respectively. This multiplexer 24 is configured so that the signal applied to the switching control terminal is “H”.
” (or 1”), the contacts b1 and b are connected as shown in Fig. 1.
2 is turned on, and in this state, A field memory 12, B
Output control σ°C is outputted to LtlHf'rJ in the 7E/lzt memory 13, respectively.

Therefore, adjacent line signal data are output from the A field 12 and the B field 13 line by line.

On the other hand, when the switching control signal is "L" (or "0"), contact a1. a2 is turned on, and an output control signal σ is output to the A field memory 12 and the B field memory 13 for each field. Therefore, signal data from the A field memory 12 or the B field memory 13 is output for each field.

The above field discrimination signal FLD, freeze instruction signal FR
, enlargement instruction signal ENL are input to the P-ROM 26 as address signals, and data corresponding to various modes is output from the two output terminals Do and Dl in accordance with these three signals q. The data output from the output terminal DDO is output as a signal for controlling the multiplexer 17, and the data is output from the output terminal D1 to the switching control terminal of the multiplexer 24 as a switching control signal.

The relationship between address data and output data to the address end of the P-ROM 26 is shown in a table.

(Margins below) As can be seen from the remarks column 111a of this table, if both address data A1 or A2 are 1'', the mode is normal video mode, and in this mode, 15
signal is applied to multiplexer 24, and contacts a1. a2 is turned on. In this state, signal data is sequentially output from the A field memory 12 and the B field memory 13 for each field.

This situation is shown in FIG. In FIG. 3(a), the output control signal OC is input to the B field memory 13, and in this state, the signal data written from the B field memory 13 is read out.

On the other hand, a write enable signal is applied to the A field memory 12 (in this field), and the input signal data is written to this A field memory 12.

When the next field comes, A
The states of field memory 12 and B field memory 13 are switched, signal data is read from A field memory 12, and input signal data is written to B field memory 13.

In the video mode, a 1" signal is output from the output terminal Do to the control terminal of the multiplexer 17, turning on the contact. Therefore, in this normal mode (video mode), the A field memory 12, B field memory 12, B Video signal data is read out from the field memory 13 and outputted to the post-processing circuit 11 side through the contact point S. In other words, a normal interlaced movie signal is outputted, and is displayed in an interlaced manner.

In the table, in the 7-leads mode when the address signal A1 is "0" and the address (a) is "1H", the output data of the P-ROM 26 is the same as in the video mode, but the freeze instruction signal FR causes the memory driver 19 to disable write enable WE.

Therefore, writing to the A field memory 12 and the B field memory 13 is prohibited, and the A field memory 12 and the B field memory 13 are read out alternately for each field as in the case of moving images, and a freeze is displayed on the monitor screen. The resulting one frame image will be displayed repeatedly in an interlace display.

Next, in the table, in the double enlargement mode when the address signal A1 is "1" and the address signal A2 is 0" (AO is the same whether it is 0" or "1"), the data from the output terminal D1 is As in the normal mode, it is "O", and the signal data of the A field memory 12 and the B field memory 3 is output for each field.

In this mode, the data from the output terminal Do is O'', and the contact a of the multiplexer 17 is turned on.

Also, in this expansion mode, the A field memory 12 or B field memory 12
The read clock to the field memory 13 (described as field A in FIG. 4) is doubled, and
), the same horizontal line is read out two by two.

That is, during the O-th and first horizontal line periods, the signal data A11. △12. A13. ... is read twice, and the second
And in the third horizontal line period, the signal data A21°A22 . A23. ... is read twice. In this way, the A field memory 12
The signal data read from the 1-day delay port 15 in FIG.
Since the signal is delayed by 18 periods, the signal data shown in FIG. 4(b) appears in time series at the output terminal of this circuit 15.

Therefore, the signal data shown in Fig. 4(a) and (b) are added by addition nZ16, resulting in one signal data shown in Fig. 4(C) (in Fig. 4(C), it is divided by 2). (This is a representation.) The signal is output to the post-processing circuit 11 side via contact a, which is turned on.

Next, in the table, address signals A1. Both A2 are 0″
In the enlarged freeze mode (enlarged still image mode) in the case of , the output terminal D1 becomes "1", and the contacts bl and b2 of the multi-break 924 are turned on as in the case of the enlarged mode. In this state, △field memory 12 and B
One horizontal line of signal data is read from the field memory 13. Therefore, in this case, the A field memory 12 and the B field memory 13
The signal data outputted from the output terminal of is as shown in FIG. 5(a).

Signal data A11. stored in the first horizontal line of the A field memory 12 during the first horizontal period. Al2. A13.
. . , the signal data B11, B12 . . . are read out from the B field memory 13 in the next horizontal period. B13.・
. . are read out, and then A21, A22 . A23.
. . , 821, 822, 823, . . . are read out. Address signal A1 is “0” and address signal AO is 1
As can be seen from the table, in the field that is ``, the output end D
Since the signal from O is "1" and the contacts of the multiplexer 17 are turned on, the signal data A11, Al 2. Al 3...: B11. B1 shown in FIG. 5(a) is generated.
2. [313, . . . are sequentially output to the post-processing circuit 11. Therefore, in this field (in the mode in which the multiplexer 24 selects the contacts a1, a2 side, it is a Δ field, so it is written as the A field), the signals A1n (A11, A12, .
-Represents... >, Bln, A2n, ... are displayed in interlace on the monitor screen.

The signal data shown in FIG. 5(a) is transmitted by an 11-1''M extension circuit 15, and the signal data shown in FIG. 5(b) is outputted to the output terminal of this circuit 15.

Further, by adding the signal data shown in FIGS. 5(a) and 5(b) by the adder 16, the interpolated signal data (A11+811)/2. shown in FIG. 5(C) is obtained. (A12+B12
)/2. ... are generated sequentially. The interpolated signal data shown in FIG. 5(C) is not used in the A field, but
When it comes to the field, the address signal ΔO is activated as shown in the table.
is 0", the output terminal DO becomes "0" and the contact a of the multiplexer 17 is turned on, so instead of the 1 signal data shown in FIG. 5(a), the interpolated signal data shown in FIG. 5(C) is generated. are output sequentially.In other words, as shown by the dotted line in FIG. 6, (A1n + A2n)/2.(B1n+A2n)/2,
... is displayed in an interlaced manner on the monitor screen.

Point X1°X2. which represents the diagonal line on the solid line in FIG. X
3..., those interpolation points xi', x2'
X3'... is (x1+x2)/2. (x2+x3)/
2. ... is generated by interpolation, so smooth interpolation can be performed. Therefore, an enlarged frozen image of excellent image quality can be obtained with a simple configuration.

FIG. 7 shows video processing @[31 of the second embodiment of the present invention.

This second embodiment differs from the first embodiment in the configuration inside the memory block 6.7. Each memory block (e.g. 6
) is replaced by a memory 32 having a storage capacity for two fields, and the most significant bit A14 (the eighth
(See figure) A.

Writing and reading are performed in the A field section 33 and the 8 field section 34 corresponding to the B field memory 12.13.

The configuration of the memory controller 35 that controls the memory 32 is shown in FIG.

Similar to FIG. 1, the horizontal synchronization signal 1 is the vertical synchronization signal s v
It is input to the T-type flip-flop 23 which is reset at o. The output terminal Q of this T-type flip-flop 23 is
It is connected to the contact point A of the first multiplexer 24A, and the field discrimination signal FLD is applied to the contact point A via the inverter 25. The output end of the first multiplexer 24A is connected to the contact a of the second multiplexer 24B, and the discrimination signal "π1" is applied to the contact a.

The output of the second multiplexer 24B is the memory 32
This becomes the address signal A14 of the most significant bit.

Similar to Figure 1, the discrimination signal loco, freeze instruction signal port,
The enlargement instruction signal ENL is the address end A of the P-ROM26.
O, A1. A2, and the output of the output terminal DO is applied to υItlHm of the multiplexer 17. This P-R
The output of the output terminal D1 of OM26 is the first multiplexer'
J 24 is applied to the control W end of A, turning on the contact at 111 I+.

Further, both instruction signals FR and ENL are inputted to one memory driver, and output terminals C3, WS, WE.

RE and address signal AO-A13 are output to the memory 32.

Note that the write enable signal WE is transmitted to the second multiplexer 4.
It is applied to the control end of j24B and turns on the contact at 11111. The A field portion 33 (or B field portion 34) on the side to which this signal WE is not input is read, and writing is performed in the B field portion 34 (or A field portion 33) to which this signal WE is applied.

The other configurations are the same as in the first embodiment.

This second embodiment generates the most significant bit address signal A14 at the time of reading instead of the output control signal σ to the A field memory 12Δ and B field memory 13 in the first embodiment, and has the same function. I try to do it.

Therefore, the operation and effect are also the same as in the first embodiment.

Note that each of the embodiments described in E describes the case of expansion by a factor of 2 (length ratio), but it can also be applied to other cases of expansion, such as 3 times or 4 times.

[Effects of the Invention] As described above, according to the present invention, since an enlarged display interpolation means for performing line interpolation between adjacent video signal relines in even and odd fields is provided, high image quality can be achieved. Enlarged frozen images can be obtained.

[Brief explanation of the drawing]

Figures 1 to 6 relate to the first embodiment of the present invention.
The figure is a configuration diagram of the memory controller in the first embodiment.
Fig. 2 is a configuration diagram showing a conventional image carrier system, Fig. 3 is an explanatory diagram showing how two field memories are written/read alternately in normal mode, and Fig. 4 is an explanatory diagram showing how writing/reading is performed alternately in two field memories in normal mode. 5 is an explanatory diagram showing the video signal data of each part in the enlarged freeze mode, and FIG. 6 is an explanatory diagram showing how it is enlarged and displayed by line interpolation in the enlarged freeze mode, FIG. 7 is a block diagram of a second embodiment of the present invention, FIG. 8 is a block diagram of a memory controller in the second embodiment, FIG. 9 is a block diagram of a conventional silver image system, and FIG. FIG. 11 is a block diagram of the memory controller used in the figure, and is an explanatory diagram of the enlarged display by line interpolation according to a conventional example. 1...CCD 5...Pre-process circuit 6.7...Memory block 11...Post-process circuit 12.13...Field memory 15...IHff extension circuit 16...Sifter 17
...Multiplexer 22...Memory controller 23...Flip-flop 24...Multiplexer 26...P-ROM Fig. 1 Fig. 3 (0) Fig. 2 Fig. 2 (b) (C)

Claims (1)

[Claims] A memory that stores at least one frame of video signals;
In the video signal processing device, the video signal processing device includes a signal processing means for performing enlarged display from the video signal read from the memory, and in the enlarged still image mode, line interpolation is performed between adjacent video signal lines in even and odd fields. A video processing device characterized by being provided with interpolation means for enlarged display.