JP2000032355A - Device and method for camera control and storage medium - Google Patents

Abstract

PROBLEM TO BE SOLVED: To reduce a time in a write mode and a read-out mode by changing a writing unit and writing in accordance with a spatial position by pixel shifting between an even number field and an odd number field in the write mode and reading by a field unit in the read-out mode. SOLUTION: This device consists of an optical system 10, a CCD signal processing part 13, a memory 15, an MPU 25 and the like. Then the device has a writing mode which synthesizes plural frame pictures different in spatial positions by pixel shifting into pictures of the corresponding size to the number of the frame picture in a pixel shifting picture obtaining mode and writes them into a memory 15, and a read-out mode which splits the synthesized pictures into the size appropriate to a picture signal processing circuit and transmits them from the memory. Then the writing unit is changed and the writing performed in accordance with the spatial position by the pixel shifting between an even number field and an odd number field at the time of the writing mode and, at the same time, read-out is performed by the field unit in the read-out mode.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

[0001] 1. Field of the Invention [0002] The present invention relates to a camera control device, a camera control method, and a storage medium having a pixel shift image acquisition mode for high quality image capture.

[0002]

2. Description of the Related Art In recent years, digitization of information has become indispensable with the spread of personal computers. Among them, computerization of images is in great demand especially for homepage creation, video conferences, data conferences, and the like. At present, digital cameras are mainly used for digitizing images, but recently, pixel shift cameras capable of digitizing moving images and high-quality still images have been receiving attention.

A system of a pixel shift camera proposed by the present applicant will be described below. The pixel shift camera realizes pixel shift by using a parallel plate. FIG. 8 shows the principle of pixel shift by the parallel plate. FIG. 8A is a diagram of the optical system. FIG.
7A, reference numeral 71 denotes an X-direction parallel plate;
Is a Y-direction parallel plate, 73 is a CCD sensor, 74
Is a lens.

[0004] First, the mechanism of pixel shift using a parallel plate will be described. FIG. 8 shows the CCD sensor 73.
As shown in (b), a light insensitive portion 76 exists due to the pixel 75 and the transfer register. A pixel shift camera aims to obtain a high-quality image by collecting images in these light insensitive portions and synthesizing them by signal processing at a later stage. The parallel plates 71 and 72 are used to obtain an image in the dead area 76.

FIG. 8C shows the mechanism. For example, by tilting the parallel plate as shown in FIG. 8C, the optical axis direction can be shifted as compared to before the operation, and as a result, the incident position of the image can be shifted on the imaging surface. Now, by changing the inclination of the parallel plate, the image incident position is shifted by 2/3 pixel. That is, the image itself is shifted by 2/3 pixel. Such pixel shift is performed 18 times in total by combining the parallel plates 71 and 72 in the X and Y directions. 18 obtained by this
Are synthesized by adjusting the spatial position of the field image in the subsequent signal processing.

A specific operation of the parallel plate will be described.

[0007]

[Table 1]

In each parallel plate, the X-direction parallel plate has a shift of ± 2/3 pixels, the Y-direction parallel plate has a shift of ± 2/3 pixels, and a +1 pixel twist in the X direction. The X-direction parallel plate 71 and the Y-direction parallel plate 72 are operated in combinations shown in Table 1. FIG. 12 shows the movement of the optical axis when the X and Y parallel plates 71 and 72 are operated in the combinations shown in Table 1. The central solid line square is the position (origin) of the optical axis when the parallel plate is not operated.

The CCD is a field accumulation mode in which upper and lower lines (Mg (magenta) and Gr (green) lines and Cy (cyan) and Ye (yellow) lines) are added and read out when capturing a normal moving image. . However, when pixel shifting is performed, a frame accumulation mode is used in which each line (Mg, Gr line and Cy, Ye line) is separately output alternately for each field without performing line addition.

In FIG. 12, the operation of the parallel plate differs between the odd field and the even field because of the odd field (Mg, Gr) in the frame accumulation mode.
This is because the pixel arrangement is different between and the even field (Cy, Ye).

Also, the actual CCD pixel array and the C
FIG. 10 shows a CD pixel array. In FIG. 10, reference numeral 90 denotes a CCD pixel array, and 91 denotes a parallel plate.
Is a CCD pixel array synthesized after driving by the combination of. In this way, by shifting the pixels using the parallel plate, an image of nine times the original CCD image size, which compensates for the image of the light insensitive portion 76 of the CCD, is generated.

FIG. 9 is a block diagram showing processing of the pixel shift camera. In FIG. 9, an image picked up by the CCD 82 on the parallel plate 81 at a certain position is digitized by the AD converter 83. The memory controller 84 converts the digitized CCD signal into
The data is sequentially written into the memory for 18 fields (9 frames) in synchronization with the operation of the parallel plate (write mode). In this write mode, the memory controller 84
Writing is performed while the image is synthesized on the memory by the capture unit 84a and the synthesis unit 84b. Next, the composite image is divided into a size suitable for the subsequent CCD signal processing, and
The data is read from the memory by the reading unit 84c in synchronization with the D signal processing circuit 85 (read mode).

First, the write mode will be described. FIG. 13 shows the mutual timing between the parallel plate and the memory control device. FIG. 13 shows the CCD accumulation time / transfer time in one parallel plate operation and the timing of writing the image to the memory. V in FIG.
D indicates a vertical synchronizing signal of a video signal, and a period Tv = 1
6.7 ms. FID is an identification number of an odd / even field, and means L = odd field and H = even field. The moving period of the parallel plate is set to 1 V in consideration of the stability of vibration (i: PP moving period). In the next field where the operation of the parallel plate is stable, the image at the position of the parallel plate is CCD.
(Ii: accumulation period). Further, in the next field, the image signal accumulated in the CCD is output as a CCD signal (iii: transfer period). In the same field, the CCD signal is written to the memory (i
v: Memory Write period). FIG. 13 shows timing in an odd field (Mg, Gr) as an example. In the case of an image signal of an even field (Cy, Ye), the PP movement period: EVEN, the accumulation period: ODD,
Transfer period and memory write period: EVEN (OD
D = odd field, EVEN = even field). Pixel shift uses this parallel plate movement as ODD,
Since EVEN is alternately performed 18 times, the timing of parallel plate movement and memory writing in all pixel shifts is as shown in FIG.

Next, the read mode will be described. FIG. 11 shows a comparison between the effective pixel size 100 of the CCD and the size 101 of the CCD image synthesized by pixel shifting. As can be seen from this figure, when the parallel plate is driven by the combination of Table 1, Xc = 3 × Xs, Y
c = 3 × Ys (Xs: CCD effective number of pixels in the X direction, Y
s: the number of effective pixels in the Y direction, Xc: the number of pixels in the X direction of the combined CCD image, and Yc: the number of pixels in the Y direction of the combined CCD image. Normally, since the CCD signal processing circuit only supports the CCD pixel size (Xs × Ys), when reading out CCD image data from the memory to the CCD signal processing circuit, a composite CCD is used as shown by a broken line in FIG.
In order to divide the image 101 into nine parts and to process all the combined images, it is necessary to transmit each one nine times in total. That is, 9
(Block) × 2 (V) = 18V time is required.

[0015]

However, in the above-mentioned conventional camera control device, as can be seen from FIG. 14, a series of writing operations requires 3V × 18 =
It takes 54V ≒ 0.9s. Also, when transmitting to the CCD signal processing circuit (reading from the memory), a minimum time of 18 V is required, so that the signal processing of the entire pixel shift requires 54 + 18 V = 72 V ≒ 1.2 s, and the time is There was a problem that it would take.

[0016] Since the use of the pixel shift camera is mainly a document such as a document, the amount of time taken in does not significantly affect the operation and performance. However, when capturing an image of a moving object or from the viewpoint of user's convenience, it is desirable that the capturing time or the entire time including the CCD signal processing time after capturing be as short as possible. 18V read time from memory
Since the following is impossible (because image processing for 9 frames is required), it is necessary to shorten the writing operation as much as possible.

The present invention provides a camera control device, a camera control method, and a storage medium capable of shortening the time of such a writing mode and a reading mode when obtaining high image quality by a pixel shift camera. With the goal.

[0018]

A camera control device, a control method thereof, and a storage medium according to the present invention are configured as follows.

(1) A camera control device having a pixel-shifted image acquisition mode, wherein, in the pixel-shifted image acquisition mode, a plurality of frame images having different spatial positions due to the pixel shift are set to the number of frame images. A writing mode in which the image is synthesized into an image having a size corresponding to and written into the memory, and a read mode in which the synthesized image is divided into a size suitable for an image signal processing circuit and transmitted from the memory, In the writing mode, writing is performed by changing the writing unit according to the spatial position due to the pixel shift between the even field and the odd field, and reading is performed in each field unit in the reading mode.

(2) In the camera control device of the above (1), in the writing mode, writing is performed in field units when the spatial position due to image shift is different between the even field and the odd field, and writing is performed in the even field and the odd field. When the spatial positions due to the pixel shift are the same, writing is performed in frame units.

(3) In the camera control device according to (1) or (2), a bus is connected to a digital data line connecting the analog-to-digital converter and the image signal processing circuit.

(4) In the camera control device of the above (3), the output side of the analog-to-digital converter is controlled to have a low impedance in the writing mode, and the output signal of the analog-to-digital converter is written in the memory. The image signal from the memory is transmitted to the image signal processing circuit by controlling the output side of the analog-to-digital converter to high impedance.

(5) A method for controlling a camera having a pixel-shifted image acquisition mode, wherein in the pixel-shifted image acquisition mode, a plurality of frame images having different spatial positions due to the pixel shift are set to the number of frame images. In the write mode in which the image is synthesized into an image having a size corresponding to the size and written in the memory, the writing unit is changed according to the spatial position due to the pixel shift between the even field and the odd field, and writing is performed. In a read mode in which an image is divided into a size suitable for an image signal processing circuit and transmitted from the memory, control is performed so that reading is performed in units of fields.

(6) In the camera control method of the above (5), in the writing mode, writing is performed in field units when the spatial position due to image shift is different between the even field and the odd field, and writing is performed in the even field and the odd field. When the spatial positions due to the pixel shift are the same, writing is performed in frame units.

(7) In the camera control method of (5) or (6) above, the output side of the analog-to-digital converter is controlled to have a low impedance in the writing mode, and the output signal of the analog-to-digital converter is written to the memory. In the read mode, the output side of the analog-to-digital converter is controlled to have a high impedance to transmit the image signal from the memory to the image signal processing circuit.

(8) By the control device of the camera having the pixel-shifted image acquisition mode, in the pixel-shifted image acquisition mode, a plurality of frame images having different spatial positions due to the pixel shift according to the number of the frame images. In the write mode in which the image is combined with an image of a different size and written to the memory, writing is performed by changing the writing unit according to the spatial position of the even field and the odd field by the pixel shift, and the combined image is written. In a read mode in which the data is divided into a size suitable for an image signal processing circuit and transmitted from the memory, a program for realizing control to perform reading in units of fields is stored in a storage medium.

(9) In the storage medium of the above (8),
In the write mode, writing is performed in field units when the spatial position due to image shift is different between the even field and the odd field, and writing in frame unit is performed when the spatial position due to the pixel shift is the same in the even field and the odd field. The program for realizing is stored.

(10) In the storage medium of (8) or (9), the output side of the analog-to-digital converter is controlled to have low impedance in the write mode, and the output signal of the analog-to-digital converter is written to and read from the memory. In the mode, a program for controlling the output side of the analog-to-digital converter to high impedance and transmitting an image signal from the memory to the image signal processing circuit is stored.

[0029]

Embodiments of the present invention will be described below in detail with reference to the drawings.

FIG. 1 shows a system configuration diagram of a pixel shift camera according to the present invention. In FIG. 1, reference numeral 10 denotes an optical system including a parallel plate 17 and a lens 16;
1 is a CCD peripheral portion including a CCD and peripheral circuits, 12 is a CC
A / D converter for A / D conversion of D signal, 13 is CCD
A signal processing unit, 14 is a memory control device, 15 is a memory,
8 is an SSG for generating a synchronizing signal, 19 is a TG for driving the CCD, and 25 is an MPU for controlling the system.

In the camera having the above system configuration, the CCD image on the parallel plate 17 at a certain position is digitized by the A / D converter 12 and is stored in the memory controller 14.
Through the memory 15. At this time, the memory control device 14 controls the operation of the parallel plate 17 and the CCD.
The write control is performed while synchronizing with the drive timing of the above, and a total of 18 field images shown in FIG.

After the completion of the composite image, the memory control device 14
First, the output of the A / D converter 12 is controlled to high impedance, and the composite image is transmitted to the CCD signal processing unit 13. At this time, the memory control device 14 controls to divide the synthesized image into an appropriate size and read it out of the memory 15 while synchronizing with the CCD signal processing circuit 13. When the transmission of the image for nine frames is completed, control is performed to return the output of the A / D converter 12 to Enable. Synchronization in these processes is performed based on HD (horizontal synchronization signal), VD (vertical synchronization signal), and CLK (pixel period signal) which are all signals of SSG 18.

A control method for realizing the shortest time write and read control in the above system will be described below.

In the operation sequence of the parallel plate 17 in FIG. 12, the spatial positions (1) and (2), (3) and (4),
(5) and (6), (7) and (8), (9) and (10),
(11) and (12) are the same spatial position in the ODD field and the EVEN field, and the spatial position (1
3) to (18) are different spatial positions in the ODD field and the EVEN field. Therefore, when the parallel plate 17 is at the same spatial position in the ODD field and the EVEN field, image data of both the ODD field and the EVEN field can be written to the memory 15 by one movement of the parallel plate 17.

At this time, CC during the parallel plate operation
FIG. 3 shows the D accumulation time / transfer time and the timing of writing the image to the memory 15. (I) is a parallel plate movement period, (ii) is an ODD field pixel (Mg, G
r) transfer time, (iii) is the accumulation time of the EVEN field pixel (Cy, Ye), (iv) is the transfer period of the ODD field image (Mg, Gr), and (v) is the EVEN field image (Cy, Ye). , The transfer period of (vi) is O
The memory writing period of the DD field image (Mg, Gr), (vii) is the EVEN field image (Cy, Y)
This is the memory writing period of e).

As can be seen from a comparison with FIG. 13, the conventional method requires 3 V × 2 = 6 V.
V. When the ODD field and the EVEN field are all located at different spatial positions, the same method as the conventional method shown in FIG. 13 is used.

[0037]

[Table 2]

FIG. 2 and Table 2 show the operation sequence of the parallel plate 17 that implements the above control method, and FIG. 4 shows the overall timing of the parallel plate and the memory control device that implement the above control method.

FIG. 2 and Table 2 show the parallel plate 17.
Is a driving method in which the parallel plate moves once when the spatial position is equal in the ODD field and the EVEN field, and moves separately when the spatial position is different in the ODD field and the EVEN field. If they are satisfied, the driving order need not be limited to that shown in FIG.

In FIG. 4, VD represents a vertical synchronizing signal of a video signal, and has a period Tv = 16.7 ms. Also, F
ID is an identification number of an odd / even field, and means L = odd field and H = even field. [1]
[6] indicates a period in which the parallel plate 17 has the same spatial position in the ODD field and the EVEN field,
[7] to [12] are periods of different spatial positions in the ODD field and the EVEN field. In this manner, the memory 1 depends on the spatial position of the parallel plate 17.
By controlling the write control of No. 5 aperiodically, the write mode can be completed at 40V.

In the read mode, the minimum is 2
V (ODD / EVEN) × 9 frames = 18 V is completed. Therefore, as shown in FIG. 4, if the read mode is started from the ODD field immediately after the completion of the write mode, the processing control of the entire pixel-shifted image (write → synthesis →
Readout) is completed when 40V + 18V = 58V.

The configuration of a memory control device for realizing the above control method will be described.

FIG. 5 is a block diagram showing a configuration of a memory control device for realizing the above control method.

In the figure, reference numeral 30 denotes a timing generator,
31 is an Ena that controls the write and read periods.
ble generating unit, 32 is a write address counter, 3
Reference numeral 3 denotes a read address counter, reference numeral 34 denotes a write / read mode switching multiplexer, and reference numeral 35 denotes a data selector unit for controlling data directions and arithmetic operations.

The synchronization signal (FID, VD, HD) and clock (CLK) input to the memory controller 14 are used by the timing generator 30 to generate various timing signals necessary for memory control. The Enable generator 31 performs the following control based on the various timing signals. In the write mode, as shown in FIG. 4, an enable signal is generated such that the ODD field and the EVEN field are continuously enabled every 4 V in the first half, and the ODD field and the EVEN field are alternately enabled every 3 V in the second half. .

In the read mode, an enable signal for enabling the 18 V period continuously is generated. The address counters 32 and 33 generate control signals (address signal, write / read enable signal, write / read control clock) necessary for memory control based on the Enable signal and the various timing signals. The multiplexer 34 switches and outputs a control signal required for the memory control according to the write mode / read mode. The data selector 35 controls the direction of data, performs operations, and the like according to the write mode and the read mode.

Next, the operation in the write mode will be described.

FIG. 6 shows a control method of the memory in the write mode. 50 is an A / D converter, 51
Is a circuit (DSP) for processing a CCD signal, and 52 is a memory controller. These components are the same as a part of [FIG. 4 Pixel Shift Camera System Diagram]. Numeral 53 indicates some pixels of the CCD image when the parallel plate 17 is at a certain position. Numeral 54 indicates a part of a memory obtained by synthesizing the CCD image by adjusting its spatial position.

The CCD signal digitized by the A / D converter 50 is written in the memory at every third in the X and Y directions. The offset values (0, 1, 2) in the X and Y directions at the time of writing are set in the parallel plate 17.
Is changed according to the spatial position determined in the state of (1). The writing counter 32 is a counter that performs the above control. The present memory controller performs such a write
This is performed separately for both the D field and the EVEN field.

With the above control, the ODD field (Mg, Gr) image and the EVEN field (Cy, Y)
e) For each image, a composite image having a size nine times the original size of the CCD is formed on the memory.

Next, the operation in the read mode will be described.

FIG. 7 illustrates a control method of the memory in the read mode. Reference numeral 60 denotes a composite image, 62 denotes an effective pixel in the composite image, and 63 denotes a black level pixel in the composite pixel. Since the CCD signal processing circuit 51 shares the original circuit for moving image processing, the pixel size that can be processed is CCD
This is the original number of pixels (Xs × Ys), and the CCD signal is also a signal corresponding to a field-read CCD with line addition. Therefore, in this memory control device, FIG.
As shown by the dotted line in FIG. 2, the composite image is divided into nine sizes (which can be processed by the CCD signal processing circuit 51).
CC by ODD / EVEN (9 times each)
The signal is transmitted to the D signal processing circuit 51.

FIG. 7 shows an example in which gray blocks in a composite image are read. At this time, the black level pixel signal 63 formed at the end is also transmitted in the same manner as a normal CCD signal. The read counter 33 is a counter that performs the above control. Further, the CCD signal processing circuit 51
Corresponds to only the field accumulation mode CCD signal. Therefore, when reading the ODD field signal and the EVEN field signal from the memory, the line addition is performed and then transmitted. This control is performed by the data selector 35.

With the above control, the processing of the entire pixel-shifted image is performed by 2 (ODD / EVEN) × 9 frames = 18 V using the original CCD signal processing circuit for moving image processing.
Can be processed.

If the memory control device has the above configuration and uses the write / read method of this embodiment, the write mode (40 V) + read mode (18
The signal processing of the entire pixel-shifted image can be performed in the time V).

As described above, in the present embodiment, the memory control device includes a writing mode for combining a plurality of CCD frame images having different spatial positions into one large image when acquiring a pixel-shifted image. A read mode in which the image data is divided into a size suitable for a subsequent CCD signal processing circuit and transmitted, and the memory control device is configured to write a plurality of CCD frame images having different spatial positions into a memory when acquiring the pixel-shifted image. Has a non-periodic write control method for storing data in the shortest time and a memory read control method for each field when transmitting to the CCD signal processing circuit. When the spatial position of the pixel shift is different between the field and the odd field, writing is performed in field units and the even field is written. By spatial position of pixel shifting in the odd field to write the frame unit at the same time, the shortest time of 58V (≒ 0.97s), the CCD image writing, the spatial alignment and C
Transmission to the CD processing circuit can be performed.

Note that the present invention may be implemented as a storage medium storing a program for realizing the above-described write mode and read mode.

[0058]

As described above, according to the present invention,
In the pixel shift image acquisition mode, a writing mode in which a plurality of frame images having different spatial positions due to the pixel shift are synthesized into an image having a size corresponding to the number of the frame images and writing to a memory is performed, and A read mode in which the divided image is divided into a size suitable for an image signal processing circuit and transmitted from the memory, and in the write mode, the image is spatially shifted according to the spatial position of the even field and the odd field by the pixel shift. When the position is different, writing is performed in a field unit, and when the spatial position due to the pixel shift is the same in the even field and the odd field, writing is performed by changing the writing unit such that writing in a frame unit is performed, and in the reading mode, Control to read in each field unit Because the way, there is an effect of reducing the time to get a high-quality image becomes possible.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a system configuration of a pixel shift camera according to the present invention.

FIG. 2 is an explanatory diagram showing the operation order of a parallel plate in consideration of the shortest write time in one embodiment.

FIG. 3 is a timing chart showing the operation of the parallel plate and the timing of memory control in FIG. 2;

FIG. 4 is a timing chart showing the timing of a write operation in consideration of the shortest time in a write mode according to one embodiment;

FIG. 5 is a block diagram illustrating a configuration of a memory control device according to an embodiment;

FIG. 6 is a block diagram showing a flow in a write mode according to one embodiment;

FIG. 7 is a block diagram showing a flow in a read mode according to one embodiment;

FIG. 8 is an explanatory diagram showing pixel shifting using a parallel plate.

FIG. 9 is a block diagram showing processing of a pixel shift camera.

FIG. 10 is an explanatory diagram showing a pixel array of a composite image obtained by shifting pixels;

FIG. 11: Effective size of CCD sensor and effective size of composite image

FIG. 12 is an explanatory diagram showing an operation sequence of a conventional parallel plate.

FIG. 13 is a timing chart showing the operation of a conventional parallel plate and the timing of memory control.

FIG. 14 is a timing chart showing a conventional write operation timing;

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 10 Optical system 11 CCD peripheral part 12 A / D converter 13 CCD signal processing part 14 Memory controller 15 Memory 18 SSG 25 MPU 71 X direction parallel plate 72 Y direction parallel plate 75 Pixel 76 Dead part

Claims (10)

[Claims] 1. A control device for a camera having a pixel-shifted image acquisition mode, wherein, in the pixel-shifted image acquisition mode, a plurality of frame images having different spatial positions due to the pixel shift are reduced to the number of the frame images. A writing mode in which the image is synthesized into an image of a corresponding size and writing to the memory is performed, and a read mode in which the synthesized image is divided into a size suitable for an image signal processing circuit and transmitted from the memory, In the writing mode, writing is performed by changing the writing unit in accordance with the spatial position due to the pixel shift between the even field and the odd field, and control is performed such that reading is performed in each field unit in the reading mode. Camera control device. 2. In the writing mode, writing is performed in field units when the spatial position due to image shift is different between an even field and an odd field. When the spatial position due to pixel shift is the same in the even field and the odd field, frame writing is performed. The camera control device according to claim 1, wherein the writing is performed. 3. The camera control device according to claim 1, wherein a bus is connected to a digital data line connecting the analog-to-digital converter and the image signal processing circuit. 4. In the write mode, the output side of the analog-to-digital converter is controlled to have a low impedance by writing the output signal of the analog-to-digital converter to a memory. In the read-out mode, the output side of the analog-to-digital converter is set to have a high impedance. 4. The camera control device according to claim 3, wherein the image signal is transmitted from the memory to the image signal processing circuit under control. 5. A method for controlling a camera having a pixel-shifted image acquisition mode, wherein a plurality of frame images having different spatial positions due to the pixel shift are reduced in the number of the frame images in the pixel-shifted image acquisition mode. In the write mode in which the image is synthesized into an image of a corresponding size and written into the memory, writing is performed by changing the writing unit according to the spatial position due to the pixel shift of the even field and the odd field, and the synthesized image is written. In a read mode in which the image data is divided into a size suitable for an image signal processing circuit and transmitted from the memory. 6. In the write mode, writing is performed in field units when the spatial position due to image shift is different between the even field and the odd field. When the spatial position due to the pixel shift is the same in the even field and the odd field, frame writing is performed. The camera control method according to claim 5, wherein writing is performed. 7. In a write mode, the output side of the analog-to-digital converter is controlled to have a low impedance to write the output signal of the analog-to-digital converter to a memory. In a read-out mode, the output side of the analog-to-digital converter is set to a high impedance. 7. The method according to claim 5, wherein the control is performed to transmit an image signal from the memory to the image signal processing circuit. 8. A control device for a camera having a pixel-shifted image acquisition mode, wherein in the pixel-shifted image acquisition mode, a plurality of frame images having different spatial positions due to the pixel shift are determined according to the number of the frame images. In the writing mode in which the image is synthesized with the size of the image and writing is performed in the memory, the writing unit is changed according to the spatial position by the pixel shift between the even field and the odd field, and the writing is performed. A storage medium storing a program for realizing control to perform reading in units of fields in a reading mode in which the data is divided into a size suitable for a signal processing circuit and transmitted from the memory. 9. In the write mode, writing is performed in field units when the spatial position due to image shift is different between the even field and the odd field, and when the spatial position due to the pixel shift is the same in the even field and the odd field, the frame unit is written. 9. The storage medium according to claim 8, wherein a program for realizing the writing of data is stored. 10. In the write mode, the output side of the analog-to-digital converter is controlled to low impedance to write the output signal of the analog-to-digital converter to the memory. In the read mode, the output side of the analog-to-digital converter is set to high impedance. 10. The storage medium according to claim 8, wherein a program for controlling the transmission of the image signal from the memory to the image signal processing circuit is stored.