JPH1175218A - Video signal processing circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To apply output control to a video signal subject to various video signal processing with simple memory control not needing address control. SOLUTION: A video signal processing circuit used for an electronic endoscope or the like has a memory circuit 15 that is used for generating a master slave image patterns and generates a moving image output and a still image output on respective master and slave screens. Video data subject to simultaneous processing based on RGB area sequential signals are delayed in a delay memory 22 by at least 3 field periods and written in a master screen still image memory 23. The written video data are read from a master screen still image memory 23 and sent to a monitor as a still image output via an output control circuit 24 and an excellent still video image without a defect such as flicker is displayed on the monitor screen.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a video signal processing circuit used for video signal processing in an electronic endoscope device or the like.

[0002]

2. Description of the Related Art Conventionally, various types of electronic endoscope devices having a small solid-state imaging device such as a CCD have been proposed, and have been widely used in recent years.

[0003] In an electronic endoscope apparatus, an image of a target portion obtained by an endoscope is displayed on a monitor as a real-time moving image, and the image is frozen and displayed on the monitor as a still image. Recording can be done. For example, Japanese Patent Publication No. 5-8915 discloses that a moving image can be displayed even while a still image is being frozen and a still image is being photographed so that the state inside the body cavity can be constantly observed. An endoscope device is disclosed.

[0004]

Problems to be Solved by the Invention Japanese Patent Publication No. Hei 5-8
The device configuration disclosed in Japanese Patent No. 915 uses a memory that requires address control as an image memory for freezing an image, and thus has a problem in that output control of a video signal is complicated.

SUMMARY OF THE INVENTION The present invention has been made in view of the above circumstances, and can perform output control of video signals subjected to various video signal processings by simple memory control which does not require address control. It is an object of the present invention to provide a video signal processing circuit capable of reducing the number of steps and the number of design steps.

[0006]

A video signal processing circuit according to the present invention synchronizes three different color signals obtained by image pickup with a frame sequential image pickup means by a synchronizing means, and outputs a signal for a predetermined period from the synchronizing means. In a video signal processing circuit that processes three different color signals output to the unit as a predetermined unit signal to generate a still image, the three different color signals output from the synchronization unit are converted into at least three unit signals. Delay storage means for delaying an obtainable period, a still image storage means for storing an output signal of the delay storage means for forming a still image based on an output signal of the delay storage means,
It is characterized by having.

[0007]

Embodiments of the present invention will be described below with reference to the drawings. 1 to 3 relate to a first embodiment of the present invention, FIG. 1 is a block diagram showing an overall configuration of an electronic endoscope device, FIG. 2 is a block diagram showing a configuration of a memory circuit, and FIG. 6 is a timing chart illustrating an operation.

As shown in FIG. 1, an electronic endoscope apparatus according to the present embodiment has an electronic endoscope 1 provided with an image pickup means, and is connected to the electronic endoscope 1 and output from the electronic endoscope 1. Video signal processing unit 2 that performs various video signal processing on the imaging signal
And a light source unit 3 that supplies illumination light to the electronic endoscope 1 and a monitor 4 that is connected to the video signal processing unit 2 and displays an image of an output video signal.

The insertion section 5 of the electronic endoscope 1 is provided with an objective lens 6 at the tip thereof, and a solid-state imaging device 7 composed of a charge-coupled device (CCD) is arranged at an image forming position of the object of the objective lens 6. Have been. In addition, a light guide 8 for transmitting illumination light is provided in the insertion section 5 so as to extend to the proximal end. The light source unit 3 includes a light source lamp 9 for generating white light.
And a rotating RGB filter 10 that passes white light from the light source lamp 9 and makes illumination light of the three primary colors of RGB.

The white light emitted from the light source lamp 9 is rotated by a motor (not shown) at a constant speed.
The illumination light becomes RGB illumination light through the B filter 10 and enters the end of the light guide 8 of the electronic endoscope 1. This illumination light is transmitted to the distal end side by the light guide 8 and is emitted from the distal end of the insertion section 5 toward the subject. The illuminated subject is imaged by the objective lens 6 of the electronic endoscope 1, photoelectrically converted by the solid-state imaging device 7, and sent to the video signal processing unit 2 as an imaging signal.

The video signal processing unit 2 includes a pre-processing circuit 11 for performing pre-processing of the imaging signal, a CCD driving circuit 12 for driving the solid-state imaging device 7, and an A / D converter 13 for performing analog-digital conversion. , An enlargement / reduction circuit 14 for performing enlargement / reduction processing of video data, a memory circuit 15 for storing video data, and a D for performing digital-analog conversion.
An A / A converter 16 and a control signal generating circuit 17 for generating a timing signal for controlling each unit are provided. Pre-processing circuit 11 at the previous stage and CCD
The drive circuit 12 is connected to the solid-state imaging device 7 via the connector 18.
The D / A converter 16 at the subsequent stage is connected to the monitor 4 via the connector 19.

The video signal processing section 2 performs imaging in a frame sequential manner. Control signal generation circuit 17
Generates a timing signal for control and supplies the timing signal to each unit. The CCD drive circuit 12 generates a drive signal for driving the solid-state imaging device 7 according to a timing signal from the control signal generation circuit 17.
An imaging signal output from the solid-state imaging device 7 driven by the CCD driving circuit 12 is input to a pre-processing circuit 11 and subjected to predetermined processing such as amplification and waveform shaping. The signal is converted into a digital signal by the device 13 and converted into data.

The video signal (video data) converted into digital data is subjected to enlargement / reduction processing by an enlargement / reduction circuit 14 and then synchronized and input to a memory circuit 15 for various video signal processing. Will be applied. The video data after the video signal processing is output from the memory circuit 15 and converted into an analog signal by the D / A converter 16 to become a video signal.
It is sent to the monitor 4. The image of the video signal is displayed on the screen of the monitor 4, and the video of the subject is reproduced.

FIG. 2 shows the configuration of the memory circuit 15. The memory circuit 15 searches for a color shift of a still image and outputs a still image data update signal, and a still image color shift prevention circuit 21.
Memory for delaying video data (first-in, first-out memory (FIFO memory)) 2
2, a main screen still image memory (FIFO memory) 23 for storing a main screen still image, an output control circuit 24 for controlling the video output to the main screen, and an output control for controlling the video output to the child screen. A circuit 25 and a child screen memory (FIFO memory) 26 for generating video data of the child screen are configured to generate video data of the parent / child screen and output it to the D / A converter 16. Has become.

Next, the operation of this embodiment will be described focusing on the operation of the memory circuit 15.

Image data subjected to enlargement / reduction processing in the enlargement / reduction circuit 14 and synchronized by a synchronization memory (not shown) is input to the memory circuit 15 and processed by the memory circuit unit having the configuration shown in FIG. Is applied. The memory circuit 15 controls a FIFO memory that does not require address control, and performs output control of a moving image and a still image, output control of a parent screen and a child screen, and video data exchange control of a parent screen and a child screen. Hereinafter, the flow of video data will be described for each output video of a moving image / still image and for each screen of a parent screen / child screen.

In the case of the main screen moving image output, the video data is directly output to the D / A converter 16 via the output control circuit 24 by the control signal from the control signal generating circuit 17. Then, the video signal is converted into an analog signal by the D / A converter 16 and transmitted to the monitor 4 via the connector 19 as a video signal, and the moving image of the subject is reproduced on the main screen (parent screen) of the monitor 4.

In the case of the main screen still image output, the still image color shift preventing circuit 21 searches the still image for a color shift of the still image of the video data in units of one field during the still image generation period, and determines the color shift from the previous field data. When the count number of the shift element is small, the update of the still image is instructed to the main screen still image memory 23. Further, in the delay memory 22, after the color shift search by the still image color shift prevention circuit 21, the video data is delayed for three field periods as a still image data writing period for preventing still image flicker. When RGB plane-sequential video data is synchronized into color video data, a delay of three fields is required to prevent flicker of still image data.

FIG. 3 shows the timing of the video data and control signal at this time. In FIG. 3, the oblong oblong part is 1
This shows video data in a case where video data is formed by combining data having different time zones in an odd field and an even field in a frame, resulting in flicker. The lower three fields indicate a writing period necessary to prevent flicker in still image data. In this case, by composing the video data by combining the data of the even field of the third frame and the data of the odd field of the fourth frame as in the oval portion to the right of the oblique line, still image data without flicker can be obtained.

At this time, the control signal generation circuit 17
, A write enable signal (WE) is generated and sent to the parent screen still image memory 23 to control writing. That is, under the control of the write enable signal (WE), the output video data of the delay memory 22 is written to the parent screen still image memory 23 so as to prevent the still image flicker, and the still image data is updated. Here, WE1 is used as the write enable signal instead of WE2, and 3
By writing video data in the field period, a good still image with little color shift and no flicker is generated.

At the time of video output, video data is output to the D / A converter 16 via the output control circuit 24 by the control signal from the control signal generation circuit 17,
After being converted into an analog signal by the / A converter 16, it is sent to the monitor 4 via the connector 19 as a video signal, and a still image of the subject is reproduced on the main screen of the monitor 4.

In the case of the small-screen moving image output, the video data is written to the small-screen memory 26 via the output control circuit 25 in accordance with the control signal from the control signal generating circuit 17. At the time of writing, under control of a write enable signal (WE) generated by the control signal generation circuit 17, video data is thinned out to a size of 1/2, 1/3, 1/4. Then, at the time of video output, video data is read from the small-screen memory 26 under the control of the output enable signal (OE) generated by the control signal generation circuit 17, and D / A
After being converted into an analog signal by the converter 16, it is sent to the monitor 4 via the connector 19 as a video signal, and the moving image of the subject is reproduced on the sub-screen (small screen) of the monitor 4.

In the case of a small-screen still image output, the still image data written in the parent-screen still image memory 23 is transferred to the small-screen memory 26 via the output control circuit 25.
Is written to. The writing control method at this time is the same as the control of the small screen memory 26 at the time of the small screen moving image output. At the time of video output, the output enable signal (O) generated by the control signal generation circuit 17 is output.
Under the control of E), the video data is read from the small-screen memory 26, converted into an analog signal by the D / A converter 16, and then sent to the monitor 4 via the connector 19 as a video signal. The still image of the subject is reproduced on the sub-screen.

In the flow described above, writing and reading of video data to and from the memory are controlled, and various video signal processing and output control are performed. In the present embodiment, FIG.
With the configuration of the memory circuit 15 shown in FIG. 1, a write enable signal (W
E), the video data is controlled only by the control signal of the output enable signal (OE) or the read enable signal (RE).

In this embodiment, the FI that does not require address control is used.
The memory circuit 15 that handles video data only by the FO memory is configured. According to such a configuration of the video signal processing circuit, the video signal processing of the video signal is performed only by the FIFO memory that does not require address control in the memory circuit. And a video signal can be output to a video reproducing unit at the subsequent stage. This eliminates the need for address control, makes it easy to control the input / output processing of video signals, and eliminates the need for signal generation means for address control, thereby reducing the number of design steps involved in designing the address control signal circuit. There is an effect that can be done. Further, since an address control signal is not required, there is no need to provide an address control line on a circuit board, and there is an effect that a board layout can be easily performed.

Further, in the generation of the sub-screen output video, the video data is thinned out and written into the memory by controlling the write enable signal (WE), so that it is not necessary to divide the clock for the timing control. In the configuration of the memory circuit shown in FIG. 2, only one clock is required, and the circuit configuration can be simplified. Further, since the same memory is used for the moving image output and the still image output for the memory for generating the sub-screen, the processing can be performed, so that the number of memories can be reduced.

A second embodiment of the present invention will be described with reference to FIGS. FIG. 4 is an explanatory diagram showing a scanning line image of the video output screen, and FIG. 5 is a timing chart for explaining the operation of the sub-screen memory.

The configuration of the second embodiment is the same as that of the first embodiment shown in FIGS. 1 and 2, and a detailed description is omitted here, and only different operations will be described.

In the second embodiment, in the method of controlling the small-screen memory 26, even when a FIFO memory that does not require address control is used, moire is reduced without lowering the resolution of the small-screen video as much as possible. The control method will be described.

FIG. 4 shows a scanning line image of a video output screen. In the sub-screen image generation, one of the parent screens
When the number of pixels to be decimated increases when decimating video data such as / 3, 1/4,..., The resolution decreases and moiré becomes a concern. Therefore, in the present embodiment, moiré is reduced by changing the timing at which the video data is written.

FIG. 5 shows a method of controlling the small-screen memory 26 when thinning out to 1/3 size as an example. By changing the write enable signal (WE) of the small-screen memory 26 between the odd field and the even field, video data of different lines is written to the small-screen memory 26. In this example, a write enable signal (WE) is output by shifting the odd-numbered field and the even-numbered field by three fields so as to write the field data of the next line, and the horizontal direction (H
Direction), a write operation is performed once for three pixels.

As described above, by performing the write control by shifting the timing of the write enable signal (WE) of the small picture memory 26 between the odd field and the even field, the odd field and the even field are simply the same as in the prior art. In the small-screen output video data, the number of lines thinned out in both odd and even fields is smaller than in the method of thinning out lines.

Therefore, according to the present embodiment, the number of lines that are not output in both the odd and even fields is reduced, so that a reduction in resolution can be prevented, and a good small-screen output image with less occurrence of moire can be obtained. There is.

A third embodiment of the present invention will be described with reference to FIGS. FIG. 6 is a timing chart for explaining the operation of the child screen memory, and FIG. 7 is an explanatory diagram showing the display positions of the parent screen and the child screen.

The configuration of the third embodiment is the same as that of the first embodiment shown in FIGS. 1 and 2, and a detailed description thereof will be omitted here, and only different operations will be described.

In the third embodiment, in the control method of the small-screen memory 26, the overtaking of the display position of the small-screen, particularly the display position in the monitor screen when outputting a moving image, is performed even when the FIFO memory is used. A control method for preventing the display position and arbitrarily determining the display position will be described.

FIG. 6 shows a control method in the small-screen memory 26. In this embodiment, a write reset signal and a read reset signal in response to the write enable signal (WE) and the read enable signal (RE) are shown. Are shifted by one frame, and both are reset every two frames, and the video data is output with a delay of one frame (two fields).

When a FIFO memory is used, in a conventional control method for securing the addresses of WE and RE, as shown in FIG. 7, in order to secure the address difference and to prevent the overtaking of data, The child screen must be displayed several lines (Ln) lower than the parent screen in the vertical direction (V direction).

On the other hand, by performing write / read control by shifting the write reset signal and the read reset signal as in the present embodiment, no matter where the sub-screen is displayed on the monitor screen, a delay of one frame occurs. WE
Since the address difference between RE and RE has been completely secured,
There is an effect that the display position of the small screen can be arbitrarily determined without data overtaking peculiar to the FO memory.

A fourth embodiment of the present invention will be described with reference to FIGS. FIG. 8 is a configuration diagram showing a configuration of a delay memory, and FIG. 9 is an explanatory diagram showing field inversion of video data in a moving image and a still image.

The configuration of the fourth embodiment is almost the same as that of the first embodiment shown in FIGS. 1 and 2, and the detailed description is omitted here, and only the configuration and operation of different parts will be described.

In the fourth embodiment, the delay memory 22 shown in FIG.
Is changed, and as shown in FIG.
The delay memory of the FO memory is configured by providing an odd field data delay memory 22a and an even field data delay memory 22b in parallel.

As described in the first embodiment, in the operation of outputting a still image to the main screen, when the color shift search is performed to update the still image data in the main screen still image memory 23, the color After the deviation search, writing takes at least three field periods to prevent still image flicker.
At this time, the delay is absorbed by the delay memory 22.
When the delay time is an odd field period such as three fields, as shown in FIG.
In the still image data, the video data of the odd field and the even field are inverted and output in the same time zone, and the still image is output in the reverse order of the odd field line and the even field line. turn into.

Therefore, in this embodiment, as shown in FIG. 8, an odd field data delay memory 22a and an even field data delay memory 22b are separately provided to constitute a delay memory, and an odd field and an even field are output in reverse order. To prevent.

That is, the video data of the odd field is separately written into the delay memory 22a and the video data of the even field is separately written into the delay memory 22b, and read enable (RE) control (or output enable (OE) control) is performed. When the delay of the still image data with respect to the moving image data is in the odd field period, the reading of the video data from the delay memories 22a and 22b is reversed in the odd field and the even field.

As described above, the delay memories 22a and 22b
By reading the video data from the odd field and the even field in reverse, even if the delay of the still image data with respect to the moving image data is in the odd field period, the still image is read with respect to the moving image. There is an effect that odd field lines and even field lines can be displayed in order without inversion of odd field video data and even field video data of video.

Even if the delay memory 22 is not divided into an odd-field memory and an even-field memory, for example, if a three-field delay is added by one field and a four-field delay is added, moving picture video data and still Since the odd field and the even field of the image data are not reversed, an effect of similarly displaying the odd field line and the even field line in order can be obtained.

Referring to FIGS. 10 and 11, the fifth embodiment of the present invention will be described.
An embodiment will be described. FIG. 10 is an explanatory diagram showing an incorrect still image video data output in the main screen still image memory, and FIG.
FIG. 1 is an explanatory diagram showing a normal still image video data output in the main screen still image memory.

The configuration of the fifth embodiment is the same as that of the first embodiment shown in FIGS. 1 and 2, and a detailed description thereof will be omitted here, and only different operations will be described.

In the fifth embodiment, a control method for controlling the parent screen still image memory 23 is to prevent the output of erroneous still image data immediately after a freeze.

When freeze-on is performed in the even-numbered field of the main screen moving image to generate a still image, if the control of the write enable (WE) operation of the main screen still image memory 23 is started immediately after the freeze, FIG. As shown in (1), in the case of the FIFO memory, since the data is read ahead, the video data of the even field is written to the address where the video data of the odd field is to be written until the first write reset due to the freeze timing. . Here, newly written video data is indicated by oblique lines. Since it takes three fields to write new still image data in both the odd field and the even field, incorrect still image data is output during that period.

In order to solve such a problem, in the present embodiment, in the operation of outputting a still image to the parent screen, a write enable (WE) operation is started from the time when a moving image is being output, and the FIFO memory is stored in the FIFO memory. Even if it is used, incorrect video data is prevented from being output to the main screen still image video output immediately after the freeze.

That is, as shown in FIG. 11, in the parent screen still image memory 23, the WE operation is controlled from the time when the moving image is output to the parent screen, and the image is stored in the parent screen still image memory 23. Write data. Here, similarly to FIG. 10, the newly written video data is indicated by oblique lines. When the freeze is executed and a still image with little color shift is determined, the main screen still image memory 23
The writing to the file is stopped and still image data without flicker is obtained.

However, when a still image is to be output to the child screen even though a moving image is being output to the parent screen, the still image video data written in the parent screen still image memory 23 is converted to the still image video of the child screen. Since it is used as data, writing to the main screen still image memory 23 is prohibited during at least one frame period during which still image video data is transferred from the main screen still image memory 23 to the child screen memory 26.

As described above, by performing the write control of the main screen still image memory 23, it is possible to prevent erroneous still image data from being output to the monitor immediately after the freeze, and to output a good still image image. There is an effect that can be.

As a sixth embodiment, a modification of the fifth embodiment will be described. As described in the fifth embodiment, in the case of the FIFO memory, since the data is read ahead, the WE operation is controlled immediately after the moving image is output to the small screen, and the small screen moving image video data is written to the small screen memory 26. When you start,
Depending on the freeze timing of the main screen, the video data of the even field may be written to the address where the video data of the odd field is to be written until the first write reset.

In order to solve such a problem, in the sixth embodiment, in the operation of outputting a moving picture image to a child screen, a write enable (WE) operation is started when no video data is output to the child screen. A method of controlling the small-screen memory 26 so that erroneous video data is not output in the small-screen moving image video output immediately after the freeze even when the FIFO memory is used.

That is, in the small-screen memory 26 composed of a FIFO memory, when no video data is output to the small-screen, the WE operation is controlled so that the video data is written into the small-screen memory 26. And
When a moving image output instruction is issued to the small screen, moving image video data is output from the small screen memory 26.

As described above, by performing the writing control of the child screen memory 26, immediately after the main screen freezes,
It is possible to prevent erroneous moving picture video data from being output to the monitor, and it is possible to output a good small-screen moving picture video.

According to the embodiment described above, the video signal processing circuit is configured by using a memory that does not require address control, so that a video signal that has been subjected to various video signal processes with simple control that does not require address control can be obtained. Output control can be performed, and the problem that output control of video signals becomes complicated when a memory that requires address control is used as in the related art can be solved. Further, since a signal generating means for address control becomes unnecessary, the circuit configuration can be simplified, and the number of design steps for designing the address control signal circuit can be reduced.

[Supplementary Notes] (1) Three different color signals obtained by imaging by the frame sequential imaging means are synchronized by the synchronization means, and three different color signals output from the synchronization means in a predetermined period In a video signal processing circuit that generates a still image by processing the three different color signals output from the synchronization means for a period during which at least three unit signals can be obtained. A video signal processing circuit comprising: a storage unit; and a still image storage unit that stores an output signal of the delay storage unit in order to form a still image based on an output signal of the delay storage unit.

(2) Three different color signals obtained by imaging by the frame sequential imaging means are synchronized by the synchronizing means, and the three different color signals output from the synchronizing means in a predetermined period are converted into a predetermined unit. In a video signal processing circuit that generates a still image by processing as a signal, a first delay that delays the three different color signals output from the synchronization unit for a period during which at least three unit signals can be obtained. A first storage unit based on an output signal of the first delay storage unit;
A second delay storage unit that delay-stores the output signal of the first delay storage unit, and thins out the first still image based on the output signal of the second delay storage unit to form a still image of A third delay storage unit for delay-storing the output signal of the second delay storage unit in order to form a second still image formed by the video signal processing circuit.

(3) The video signal processing circuit according to claim 1, wherein the delay storage means delays the signal by at least three fields as the delay period.

(4) The video signal processing circuit according to appendix 2, wherein the first delay storage means delays at least three fields as the delay period.

(5) Output control means having a moving picture video output function and a still picture video output function, switching between the output of the still picture storage means and the output not passing through the delay storage means and the still picture storage means. 3. The video signal processing circuit according to claim 1, wherein

(6) The video signal processing circuit according to appendix 5, wherein the still image storage means writes the moving image data even when outputting the moving image.

(7) The first delay storage means or the second delay storage means is capable of reading video signals output to the third delay storage means in an even field and an odd field. 3. The video signal processing circuit according to claim 2, wherein

(8) The second delay storage means is a parent screen still image memory for outputting a parent screen still image, and the third delay storage means outputs a child screen still image. 3. The video signal processing circuit according to claim 2, wherein the video signal processing circuit is a memory for a small screen.

(9) The outputs of the parent screen still image memory and the child screen memory are switched, and a parent screen output and a child screen output, a moving image video output and a still image video output to each screen, and a parent screen and a child screen are output. 9. The video signal processing circuit according to claim 8, further comprising output control means having a video data exchange function.

(10) The video signal processing circuit according to appendix 8, wherein the small-screen memory comprises a single memory that also serves as a still-picture video output and a moving-picture video output of the small screen.

(11) The video signal processing circuit according to attachment 8, wherein the child screen memory delays the output of the parent screen still image memory by at least two fields.

(12) The sub-screen memory selects and writes a signal of a different line between an even field and an odd field of a video signal when thinning and writing the output of the main screen still image memory. 8. The video signal processing circuit according to claim 8, wherein

(13) In the sub-screen memory, when the output of the parent screen still image memory is thinned out and written, the interval between the odd field line and the even field line of the selected video signal is made equal. 9. The video signal processing circuit according to claim 8, wherein

(14) The parent screen still image memory includes:
The video signal processing circuit according to claim 8, wherein the video signal data is written into the memory even when the main screen video image is output.

(15) The video signal processing circuit according to appendix 8, wherein the small-screen memory writes the moving-image video data into the memory even when the small-screen video is not output.

[0076]

As described above, according to the present invention, it is possible to perform output control of video signals subjected to various video signal processings by simple memory control which does not require address control, and to simplify the device configuration. In addition, there is an effect that the number of design steps can be reduced.

[Brief description of the drawings]

FIG. 1 is a block diagram showing an overall configuration of an electronic endoscope apparatus according to an embodiment of the present invention.

FIG. 2 is a block diagram showing a configuration of a memory circuit according to the embodiment;

FIG. 3 is a timing chart for explaining the operation of the memory circuit according to the first embodiment;

FIG. 4 is an explanatory diagram showing a scanning line image of a video output screen.

FIG. 5 is a timing chart for explaining the operation of the small-screen memory according to the second embodiment;

FIG. 6 is a timing chart illustrating the operation of the small-screen memory according to the third embodiment;

FIG. 7 is an explanatory diagram showing display positions of a parent screen and a child screen.

FIG. 8 is a configuration diagram showing a configuration of a delay memory according to a fourth embodiment;

FIG. 9 is an explanatory diagram showing field inversion of video data between a moving image and a still image.

FIG. 10 is an explanatory diagram showing an incorrect still image video data output in a main screen still image memory;

FIG. 11 is an explanatory diagram showing normal still image video data output in the parent screen still image memory according to the fifth embodiment.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 ... Electronic endoscope 2 ... Video signal processing part 4 ... Monitor 7 ... Solid-state image sensor 11 ... Pre-processing circuit 14 ... Enlargement / reduction circuit 15 ... Memory circuit 17 ... Control signal generation circuit 21 ... Still image color shift prevention circuit 22 ... Delay memory 23 ... Main screen still image memory 24,25 ... Output control circuit 26 ... Sub screen memory

Claims (1)

[Claims] 1. A synchronizing unit synchronizes three different color signals obtained by imaging with a frame sequential imaging unit, and outputs three different color signals output from the synchronizing unit in a predetermined period into a predetermined unit signal. A video signal processing circuit that generates a still image by processing as follows: a delay storage unit that delays the three different color signals output from the synchronization unit for a period during which at least three unit signals can be obtained; A video signal processing circuit, comprising: a still image storage unit that stores an output signal of the delay storage unit in order to form a still image based on an output signal of the delay storage unit.