JPH0583182B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a method of manufacturing a semiconductor device, and particularly to a method of forming element isolation regions and wells.

[Conventional technology]

Conventionally, in order to miniaturize semiconductor devices and improve their reliability, grooves were formed on the surface of a semiconductor substrate and filled with an insulating material.
``Groove separation type'' element isolation methods such as those disclosed in No.-61430 and Japanese Patent Application Laid-Open No. 61-168241 are being studied.

In addition, in these conventional element isolation regions, when a thermal oxide film is formed at the upper corner of the trench, as in the process of forming a gate insulating film, the oxide film becomes thinner than the flat part, as shown in Figure 6a, which is undesirable. A phenomenon can be seen. The reason for this development is that the oxidation rate is reduced in the convex or concave portions of the silicon surface of the trenches for element isolation regions provided in the semiconductor substrate due to the concentration of stress generated during thermal oxidation.
The concentration of stress becomes more significant as the radius of curvature of the convex or concave portions becomes smaller, and therefore, the thickness of the thermal oxide film becomes more pronounced in the convex or concave portions compared to the flat portions. Furthermore, electric field concentration occurs in convex and concave parts due to the three-dimensional shape, so the Fowler−
The Nondheim current increases significantly and the insulation properties of the oxide film deteriorate. In addition, this phenomenon is the same as connecting two transistors with different gate film thicknesses in parallel in element isolation.
As a combination of the tail characteristics 601 and 602 in FIG. 7a, a hump occurs in the Vgs-Ids characteristics in the tail region of the transistor as shown in 603 in FIG. 7b.

In FIGS. 7a and 7b, 601 is the tail characteristic of the transistor formed in the plane part, 602 is the tail characteristic of the transistor formed in the corner part, and 602 is the tail characteristic of the transistor formed in the corner part.
03 shows the combined tail characteristics of 601 and 602.

To avoid these phenomena, for example,
63-45848, Japanese Patent Application Laid-open No. 61-276226, etc., a rounding process using thermal oxidation is known to alleviate the electric field in convex and concave areas, and by forming a gate insulating film after this process, A gate insulating film having a uniform thickness as shown in FIG. 6b can be obtained.

In other words, it is common knowledge that this technology is necessary to put a trench-type element isolation region into practical use.

However, these techniques, after forming the well,
After driving the channel stopper into the groove,
The rounding process described above continues with the process of burying an insulator into the trench, and is completed by forming transistors and wiring. For example, they are formed as shown in FIGS. 5a to 5g according to the process flow shown in FIG. 8b. Here, a case of a CMOS structure will be explained as an example.

In FIG. 5, 101 is a semiconductor substrate made of N-type silicon, etc., 102 is an element isolation region, and 105 is a semiconductor substrate made of N-type silicon or the like;
is P well, 112 is channel stopper, 11
5 is an N well, 116a to 116d are resists,
117 and 119 are ion beams, 118 is phosphorus
(P) and 120 are boron (B), 121a and 121b are thermal oxide films, and 122 is a CVD oxide film.

First, wells 105 and 115 are formed to form P and N channels (FIGS. 5a to 5c).
At this time, wells 105 and 11 are heated by heat treatment.
5 is formed at a depth of several μm.

Next, a CVD oxide film 122 such as a silicon oxide film is formed on the substrate on which the wells 105 and 115 have been formed, and this and the semiconductor substrate 101 are etched using the photoresist 116c as a mask. Etching the CVD oxide film 122 at this time is necessary because the channel stopper 112 will be formed only in the groove in the next step (FIG. 5d).

Next, using the CVD oxide film 122 and the new photoresist 116d as a mask, a channel stopper is ion-implanted into the groove on the P-well 105, and rounded at 1150°C in a 10% oxygen atmosphere.
Oxidize 1500Å. At this time, the well expands to 1.5 to 2 times its original depth due to heat treatment. Then, the resist 116d and the CVD oxide film 122 are removed by etching (FIGS. 5e to 5f).

Next, a new CVD silicon oxide film is formed and etched back to form an element isolation region 102 filled with an insulator (FIG. 5g).

Next, transistors, wiring, and protective films are formed as necessary to complete the process. However, due to these combinations, the technology can point out some problems.

[Problem to be solved by the invention]

However, with the above-mentioned conventional technology, the upper corner of the semiconductor device is removed after forming the groove because the gate breakdown voltage deteriorates due to electric field concentration at the corner of the gate end of the semiconductor device, and the device characteristics deteriorate such as a hump in the tail characteristic. In order to round it, it was oxidized by more than 1500 Å in an oxygen atmosphere at a temperature of more than 1150°C.

At this time, the concentration on the surface of the semiconductor substrate decreases due to oxidation, that is, the portions of the substrate surface region made of silicon etc. with high impurity concentration are converted into oxides, resulting in parasitic effects that occur in the element isolation region.
The disadvantage is that the threshold voltages of the MOS transistors 130, 140, and 150 are lowered, making it impossible to obtain sufficient performance.
This has the disadvantage that leakage occurs between wells due to field inversion due to a decrease in the surface concentration of . This phenomenon occurs because boron, which is an impurity, is easily incorporated into the oxide film during oxidation. Therefore, P is usually used as a channel stopper.
By implanting boron ions only into the well trenches, the threshold of parasitic MOS transistors that occur in device isolation regions is raised. In this case, on the contrary, the channel stopper diffuses to the surface of the substrate, raising the threshold of the transistor in the element region. Furthermore, this phenomenon becomes noticeable at the boundary with the element isolation region, resulting in the dependence of the threshold voltage of the transistor on the channel width. This is generally referred to as a narrow channel effect, and deteriorates the characteristics of the device.

Furthermore, since the depth of the wells cannot be made shallow, the diffusion in the lateral direction also increases, requiring nearly twice the separation distance between the wells.

The present invention solves the above-mentioned problems and provides a parasitic MOS transistor in an element isolation region without deterioration of gate breakdown voltage due to electric field concentration at the corner of the gate end of a semiconductor device or deterioration of device characteristics such as a hump in the tail characteristics. Semiconductors with sufficient threshold capability, particularly suppressing leakage between wells, preventing narrow channel effects, and reducing the number of steps by which the separation distance between wells can be reduced to about half. The purpose is to provide a method for manufacturing the device.

[Means to solve the problem]

The present invention is characterized in that, after trenches serving as element isolation regions are selectively formed in a substrate, impurities for forming well regions are introduced into the substrate.

Further, in the present invention, after introducing impurities into the substrate as described above, the grooved substrate is thermally oxidized preferably at a temperature of about 1050°C or higher to form a thermal oxide film with a thickness of preferably about 500 Å or more. It is characterized by simultaneously forming a well region by activating impurities introduced into the substrate.

By these means, the present invention can solve the conventional problems.

[Effect]

According to the above steps of the present invention, after forming a trench to serve as an element isolation region, impurities for forming a well are implanted, the well is activated by thermal diffusion, and the upper corner of the trench in the element isolation region is rounded. As a result of the combination of The threshold voltage of the parasitic MOS transistor in the element isolation region has sufficient capability compared to the conventional one. In other words, the phenomenon of field inversion, which is undesirable for semiconductor devices, does not occur.

In addition, the present invention provides that when oxidized to a thickness of 500 Å or more in an oxygen gas atmosphere or a nitrogen gas atmosphere containing oxygen gas at a temperature of 1050° C. or higher, gate breakdown voltage may deteriorate due to electric field concentration at the gate end corners of a semiconductor device. It is possible to obtain highly reliable element and element isolation characteristics without deterioration of element characteristics such as a hump in tail characteristics.

In the present invention, the threshold value of the parasitic MOS transistor in the element isolation region has sufficient capability, and the thermal process time can be reduced to less than half compared to the conventional method. This suppresses the occurrence of leakage because it is difficult for an inverted region to form. Further, since the present invention allows the wells to be made shallow, the separation distance between the wells can be reduced to less than half.

〔Example〕

EMBODIMENT OF THE INVENTION Hereinafter, the manufacturing method of the semiconductor device of this invention will be explained in detail based on an Example.

FIG. 1 is a main sectional view for explaining a first embodiment of the present invention. 101 is a semiconductor substrate made of N-type silicon or the like; 102 is an element isolation region; 11
5 and 105 are N well and P well, respectively. 103 and 104 are N ⁺ diffusion layer and N ^- diffusion layer respectively, and 113 and 114 are P ⁺ diffusion layer and P ^- respectively.
In the diffusion layer, 106 is a gate electrode, 107 is a sidewall, and 111 is a gate insulating film. Also,
108 is an interlayer insulating film, 109 is Al, Al-Si, Al
- Wiring made of Si-Cu, high melting point metal, etc., 110
indicates a protective film. At this time, 130 represents a parasitic MOS transistor formed under the wiring 109;
40 is a parasitic film formed under the gate electrode 106.
It represents a MOS transistor, and 150 is the wiring 10
9 represents a parasitic MOS transistor formed under 9 and spanning wells 115 and 105.

FIGS. 2a to 2f are cross-sectional views of main steps shown in the order of steps to explain the first embodiment of the present invention.

Here, the steps required up to the formation of the element isolation region will be described. Therefore, in order to realize, for example, a MOS LSI, it is necessary to add subsequent steps that are normally well known.

First, as shown in FIG. 2a, a silicon substrate 101 of, for example, N type as a first conductivity type is coated with, for example, RIE using, for example, a photoresist 116a as a mask.
Grooves are formed by anisotropic etching such as (Reactive Ion Etching). Here, for example, depth 0.8μ
m grooves are formed using CBrF ₃ gas at 400 mTorr. Of course, the etching gas is not limited to this, and any chlorine-based gas may be used as long as it is capable of etching silicon anisotropically.
In addition to the photoresist 116a, an oxide film, a nitride film, etc. may be used as a mask for etching the silicon substrate.

Next, as shown in FIGS. 2b to 2c, after removing the photoresist 116a, the resist 116a is placed at an arbitrary position on the semiconductor substrate 101.
Using 6b and 116c as masks, ion beam 1
17,119, for example, the same impurity as the silicon substrate, for example, phosphorus 118, is used as the first conductivity type impurity.
2E13 (/cm ² ) ion implantation at 120KeV, then,
For example, boron 120 is used as the second conductivity type impurity.
1E13 (/cm ² ) ions are implanted at 80KeV. Although an N-type silicon substrate is used here, it is of course not limited to this, and a P-type silicon substrate may also be used. The first and second impurities are also not limited to these, and the order is free. be. Further, impurity implantation is generally performed using a resist as a mask.

Next, a rounding oxidation process is performed to remove the corners of the grooves that will become element isolation regions. This rounding oxidation process utilizes the fact that when the silicon or the like at the corner is thermally oxidized, the radius of curvature of the silicon or the like at the corner increases. As shown in FIG. 2d, a silicon substrate 10
1 at, for example, 1150°C in an atmosphere consisting of nitrogen gas containing, for example, 20% oxygen gas, for example, about 5
The thermal oxide film 121 is oxidized for 1500 Å for a time of 1500Å.
form a. In other words, this thermal oxide film 121a is an oxide film in the rounding oxidation process. here,
The oxidation conditions are not limited to these.

Figures 11 and 12 show rounding to 200 after oxidation treatment.
A graph showing the breakdown in terms of electric field strength when the gate insulating film 111 is formed is shown below. Figure 11 shows the oxide film thickness at an oxidation temperature of 1150°C, assuming that the ratio of oxygen gas to the total gas in the atmosphere for thermally oxidizing silicon, etc. of a semiconductor substrate is 5%, 20%, 50%, and 100%, respectively. This figure shows the relationship between the electric field strength of the gate oxide film and the electric field strength of the gate oxide film. What can be seen from this figure is that the thickness of the oxide film during rounding oxidation treatment is preferably 50 nm (500 Å) or more, and more preferably
If the thickness is 100 nm (1000 Å) or more, the electric field strength for subsequent breakdown of the gate insulating film can be maintained at a good level.

In addition, Figure 12 shows when the ratio of oxygen gas to the total gas in the atmosphere is 5%, 20%, and 100%, respectively, when converting silicon, etc. of a semiconductor substrate into an oxide film with a thickness of 150 nm (1500 Å). It shows the relationship between rounding oxidation temperature and gate oxide film electric field strength.
What can be seen from this figure is that the temperature during rounding oxidation treatment is preferably 1050℃ or higher, more preferably 1100℃ or higher.
If the temperature is above .degree. C., the electric field strength for subsequent breakdown of the gate insulating film can be maintained at a good level. Preferably 1050℃ as shown in this graph
Preferably in the above oxygen gas atmosphere or in an atmosphere consisting of nitrogen gas containing oxygen gas.
The electric field strength of the gate oxide film is improved by oxidizing it to a thickness of 500 Å or more. At this time, at the same time, phosphorus 118 as the impurity of the first conductivity type and boron 120 as the impurity of the second conductivity type are diffused, that is, the impurities are activated by heat to form the wells 115 and 10.
form 5. Further, the profile of the well at this time is as shown in FIGS. 9 and 10.

Here, FIG. 9 shows the impurity concentration with respect to the depth of the P well, and FIG. 10 shows the impurity concentration with respect to the depth of the N well.

What can be seen from these drawings is that the impurity concentration in the surface portion of the semiconductor substrate including the element isolation region is higher in the present invention than in the conventional method. This reduces parasitics in the element isolation region.
The threshold value of the MOS transistor has sufficient capability, and the phenomenon of field inversion, which is undesirable for semiconductor devices, does not occur.

Furthermore, the thermal oxide film 121a in FIG. 2d, which was formed by the rounding oxidation treatment performed to improve the electric field strength of the gate insulating film described above, may or may not be removed by etching immediately after its formation. It's good. If the thermal oxide film 121a is not removed by etching, the thermal oxide film 121a is generally removed by etching before forming a gate insulating film using a thermal oxide film later. By this etching removal, since the etched film contains dirt and the like, a clean gate insulating film is formed on the substrate surface.

Next, as shown in Figure 2e, an insulating film with a thickness greater than the depth of the groove is formed on the silicon substrate surface.
A CVD oxide film 122 is formed. At this time, the insulating film formed is not limited to an oxide film, but may be a silicon nitride film. Next, as shown in Figure 2 f, CVD
The oxide film 122 is left in the trench by anisotropic etching such as RIE using CHF ₃ gas.
In addition, in order to further flatten the insulating film in the element isolation region, we formed a CVD oxide film on the silicon substrate surface as an insulating film thicker than the depth of the trench, and then coated a polymer resin film. Resin film and CVD
Equal etching rate of oxide film, e.g.
Another method is to leave the CVD oxide film in the trench by RIE using CHF ₃ gas and oxygen gas. At this time,
A photoresist film or the like can be used as the polymer resin film, but a film with particularly good flatness is desired. Also,
The method of filling the trenches with insulators is not limited to the one shown here; for example, polycrystalline silicon is buried in the trenches and then the polycrystalline silicon is thermally oxidized to turn it into an oxide, which is then buried in the trenches. Various techniques are used, such as methods.

In addition, if you want to form MOSLSI after this,
Subsequently, the steps after forming the gate oxide film are continued.

Of course, in this case, since the impurity for forming the well is introduced after forming the trench for the element isolation region, the concentration profile of the substrate under the element isolation region and the concentration profile of the substrate in the element formation region are different. I think you can see that it is the same. However, the inversion voltage of the parasitic MOS transistor on the N-channel side may decrease depending on the concentration of the well, etc.
In this case, adjustment can be made by forming a well at the same time as the rounding oxidation treatment as shown in FIGS. 3a and 3b, and then further introducing boron 120 as an impurity of the same conductivity type as the well.

Therefore, compared to the conventional case in which the concentration under the element isolation region is lowered, in this embodiment, the threshold value of the parasitic MOS transistor in the element isolation region has sufficient capability, and in particular, leakage between wells can be reduced. is less likely to occur.

Furthermore, in this example, since the impurity for forming the well is introduced after forming the trench for the element isolation region, the concentration profile of the substrate under the element isolation region and the concentration profile of the substrate in the element formation region are different. Therefore, the step of introducing impurities for forming a stopper region, which was necessary in the conventional method, can basically be omitted. However, as shown in FIGS. 3a and 3b above, depending on the concentration of the well, it may be necessary to further introduce impurities, especially into the N channel side.

Although the CMOS structure has been described here, the structure is not limited to this, and if only one channel is desired to be formed, one well may not be formed. It goes without saying that it can be similarly applied to bipolar and BICMOS devices.

Furthermore, it was possible to obtain highly reliable device and device isolation characteristics without deterioration of gate breakdown voltage due to electric field concentration or deterioration of device characteristics such as hump in tail characteristics at the corners of the gate end of the semiconductor device.

Further, in FIGS. 8a and 8b, a shows an outline of the process flow of the present invention, and b shows an outline of a conventional process flow. In other words, the present invention can significantly reduce the number of steps compared to the conventional method as shown in FIGS. 8a and 8b.

〔Effect of the invention〕

As described above, the present invention combines thermal diffusion of the well and rounding of the upper corner of the trench in the element isolation region, so that the concentration at the bottom of the trench is not reduced. Therefore, the concentration profile under the formed element isolation region is the same as the concentration profile of the element formation region. This is because the threshold value of the parasitic MOS transistor in the device isolation region has sufficient capability in the present invention, especially when leakage between wells occurs, compared to the conventional case where the concentration under the device isolation region is lower. This has the effect of making it possible to obtain a transistor that is difficult to fabricate. Furthermore, the present invention makes it possible to obtain highly reliable device and device isolation characteristics without deterioration of gate breakdown voltage due to electric field concentration or deterioration of device characteristics such as a hump in tail characteristics at the corner of the gate edge of a semiconductor device. There is an effect that can be achieved. Furthermore, since the present invention can significantly reduce the number of manufacturing steps for semiconductor devices, it also has the effect of improving yields and reducing manufacturing costs.

[Brief explanation of drawings]

FIG. 1 is a main sectional view showing an embodiment of the semiconductor device of the present invention, and FIGS. 2 a to 2f are main process sectional views showing an embodiment of the method of manufacturing the semiconductor device of the invention. FIGS. 3a and 3b are cross-sectional views of main steps showing an embodiment of the method for manufacturing a semiconductor device of the present invention. FIG. 4 is a main cross-sectional view showing a conventional semiconductor device. FIGS. 5a to 5g are main process cross-sectional views showing a conventional method for manufacturing a semiconductor device. FIGS. 6a and 6b are main cross-sectional views after gate oxidation with and without rounding oxidation treatment. FIGS. 7a and 7b are diagrams illustrating tail characteristics of transistors with and without rounding oxidation treatment. Figure 8 a and b are
FIG. 2 is a process flow diagram showing a method of manufacturing a semiconductor device according to the present invention and a conventional method. FIG. 9 is a gelatin diagram showing concentration profiles of P-wells of semiconductor devices of the present invention and a conventional semiconductor device. FIG. 10 is a graph showing N-well concentration profiles of the present invention and conventional semiconductor devices.
FIG. 11 is a graph showing the relationship between the rounded oxide film thickness and the gate oxide film electric field strength. FIG. 12 is a graph showing the relationship between rounding oxidation temperature and gate oxide film electric field strength. 101...Semiconductor substrate, 102...Element isolation region, 103...N ⁺ diffusion layer, 104...N ^- diffusion layer, 105...P well, 106...Gate electrode, side wall of 107, 108...Interlayer Insulating film, 109... Wiring, 110... Protective film, 11
DESCRIPTION OF SYMBOLS 1...Gate insulating film, 112...Channel stopper, 113...P ⁺ diffusion layer, 114...P ^- diffusion layer, 115...N well, 116a-d...Photoresist, 117, 119...Ion Beam, 118...Phosphorus, 120...Boron, 121
a, b...thermal oxide film, 122...CVD oxide film,
130... Parasitic transistor whose gate material serves as a gate electrode, 140... Parasitic transistor whose wiring material serves as a gate electrode, 150...
A parasitic transistor spanning both wells whose wiring material serves as a gate electrode, 601...Tail characteristics of a transistor formed on a plane portion, 602...
...Tail characteristics of the transistor formed at the corner,
603...Synthesized tail characteristics of 601 and 602.

Claims (1)

[Claims] 1. (a) A method for manufacturing a semiconductor device having an element isolation region formed by burying an insulator in a groove provided in a semiconductor substrate, including (b) selecting the semiconductor substrate. (c) selectively introducing impurities into the semiconductor substrate in which the grooves are formed; (d) the semiconductor substrate into which the impurities are introduced and the grooves formed; By thermally oxidizing the semiconductor substrate,
A thermal oxide film is formed on the corners of the semiconductor substrate at least above and below the groove to round the corners and at the same time activate the impurity introduced into the semiconductor substrate to form a well that will become an element formation region. A method for manufacturing a semiconductor device, comprising the steps of: (e) forming an element isolation region by burying an insulating material in the trench having rounded corners. 2. The method of manufacturing a semiconductor device according to claim 1, wherein the temperature of the thermal oxidation is about 1050° C. or more, and the thickness of the thermal oxidation film is about 500 Å or more. 3 (a) A method for manufacturing a semiconductor device having an element isolation region formed by burying an insulator in a groove provided in a semiconductor substrate, (b) a first region and a second region of the semiconductor substrate. (c) introducing a first impurity of a first conductivity type into the first region of the semiconductor substrate in which the groove is formed; (d) introducing a second impurity of a second conductivity type into the second region of the semiconductor substrate which has been doped; (d) the semiconductor substrate into which the first impurity and the second impurity are introduced and in which the groove is provided; By thermally oxidizing, a thermal oxide film is formed on the corners of the semiconductor substrate at least at the upper and lower parts of the groove, and the corners are rounded. At the same time, the first impurity introduced into the semiconductor substrate and the activating a second impurity to form a first well region and a second well region, respectively; (e) forming an element isolation region by burying an insulator in the groove with rounded corners; 1. A method for manufacturing a semiconductor device, comprising the steps of: 4. The method of manufacturing a semiconductor device according to claim 3, wherein the temperature of the thermal oxidation is about 1050° C. or more, and the thickness of the thermal oxidation film is about 500 Å or more. 5. In a semiconductor device having an element isolation region formed by burying an insulator in a groove provided in a semiconductor substrate, the groove serving as the element isolation region has rounded corners at the upper and lower parts; The semiconductor substrate has a well region serving as an element formation region provided at a predetermined position of the semiconductor substrate, and an impurity concentration distribution under the groove portion and an impurity concentration distribution in the well region are substantially the same. semiconductor devices. 6. In a semiconductor device having an element isolation region formed by burying an insulator in a groove provided in a semiconductor substrate, the groove serving as the element isolation region has rounded corners at the upper and lower parts; The semiconductor substrate has a well region provided at a predetermined position to serve as an element formation region, and the impurity concentration of the surface portion of the semiconductor substrate located at the bottom of the groove portion and the surface portion of the well region that serves as the element formation region are determined. 1. A semiconductor device characterized in that impurity concentrations are substantially the same.