JPH0582969B2 - - Google Patents
Info
- Publication number
- JPH0582969B2 JPH0582969B2 JP61152388A JP15238886A JPH0582969B2 JP H0582969 B2 JPH0582969 B2 JP H0582969B2 JP 61152388 A JP61152388 A JP 61152388A JP 15238886 A JP15238886 A JP 15238886A JP H0582969 B2 JPH0582969 B2 JP H0582969B2
- Authority
- JP
- Japan
- Prior art keywords
- semiconductor
- film
- insulating film
- semiconductor device
- electrode structure
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
- 239000004065 semiconductor Substances 0.000 claims description 67
- 229910052751 metal Inorganic materials 0.000 claims description 24
- 239000002184 metal Substances 0.000 claims description 24
- 230000003014 reinforcing effect Effects 0.000 claims description 15
- 150000001875 compounds Chemical class 0.000 claims description 5
- 229910001218 Gallium arsenide Inorganic materials 0.000 claims description 2
- 229910000673 Indium arsenide Inorganic materials 0.000 claims description 2
- 229910000661 Mercury cadmium telluride Inorganic materials 0.000 claims description 2
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 2
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 2
- 239000013078 crystal Substances 0.000 claims description 2
- WPYVAWXEWQSOGY-UHFFFAOYSA-N indium antimonide Chemical compound [Sb]#[In] WPYVAWXEWQSOGY-UHFFFAOYSA-N 0.000 claims description 2
- RPQDHPTXJYYUPQ-UHFFFAOYSA-N indium arsenide Chemical compound [In]#[As] RPQDHPTXJYYUPQ-UHFFFAOYSA-N 0.000 claims description 2
- TWNQGVIAIRXVLR-UHFFFAOYSA-N oxo(oxoalumanyloxy)alumane Chemical compound O=[Al]O[Al]=O TWNQGVIAIRXVLR-UHFFFAOYSA-N 0.000 claims description 2
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 2
- 229910052814 silicon oxide Inorganic materials 0.000 claims description 2
- 239000002131 composite material Substances 0.000 claims 1
- 239000000758 substrate Substances 0.000 description 8
- 238000000605 extraction Methods 0.000 description 5
- 238000000034 method Methods 0.000 description 5
- WABPQHHGFIMREM-UHFFFAOYSA-N lead(0) Chemical compound [Pb] WABPQHHGFIMREM-UHFFFAOYSA-N 0.000 description 4
- 238000004544 sputter deposition Methods 0.000 description 3
- XKRFYHLGVUSROY-UHFFFAOYSA-N Argon Chemical compound [Ar] XKRFYHLGVUSROY-UHFFFAOYSA-N 0.000 description 2
- 239000000470 constituent Substances 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 239000011261 inert gas Substances 0.000 description 2
- 238000004519 manufacturing process Methods 0.000 description 2
- JBRZTFJDHDCESZ-UHFFFAOYSA-N AsGa Chemical compound [As]#[Ga] JBRZTFJDHDCESZ-UHFFFAOYSA-N 0.000 description 1
- GPXJNWSHGFTCBW-UHFFFAOYSA-N Indium phosphide Chemical compound [In]#P GPXJNWSHGFTCBW-UHFFFAOYSA-N 0.000 description 1
- 229910052786 argon Inorganic materials 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 239000007789 gas Substances 0.000 description 1
- 239000012212 insulator Substances 0.000 description 1
- 150000002739 metals Chemical class 0.000 description 1
- 239000002356 single layer Substances 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
- 239000013077 target material Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
Landscapes
- Local Oxidation Of Silicon (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Description
【発明の詳細な説明】
［産業上の利用分野］
本発明は、半導体素子の構成要素としてスパツ
タ絶縁膜を用いる場合の半導体素子の電極構造に
関するものである。本発明によつて、スパツタ絶
縁膜を構成要素とする半導体素子の信頼性を高め
ることが出来るため、電子産業分野で大きな寄与
をするものである。DETAILED DESCRIPTION OF THE INVENTION [Industrial Field of Application] The present invention relates to an electrode structure of a semiconductor device when a sputtered insulating film is used as a component of the semiconductor device. The present invention makes it possible to improve the reliability of a semiconductor device having a sputtered insulating film as a component, making a significant contribution to the field of electronic industry.
［従来の技術］
半導体素子において重要な役割を果たす絶縁物
の生成方法については多くの方法がある。それら
の方法の中でも、アルゴンなどの不活性ガスまた
は不活性ガスを含むガス中の放電を利用して、タ
ーゲツト物質の表面を削り、半導体などの基板上
に堆積させる生成法はスパツタ堆積法といわれて
いる。このスパツタ絶縁膜上に電極を設ける場
合、従来は、電極の機械的強度を高めるための配
慮は特には払われていない。[Prior Art] There are many methods for producing insulators that play an important role in semiconductor devices. Among these methods, a production method that uses an inert gas such as argon or a discharge in a gas containing an inert gas to scrape the surface of a target material and deposit it on a substrate such as a semiconductor is called the sputter deposition method. ing. When providing electrodes on this sputtered insulating film, conventionally no particular consideration has been given to increasing the mechanical strength of the electrodes.
［発明が解決しようとしている問題点］
このスパツタ堆積法は低い温度で絶縁膜を生成
できるという大きな利点があるが、反面、生成の
際に半導体などの表面に損傷を与えるという欠点
もある。このため、スパツタ絶縁膜と半導体など
の基板の間の付着強度の低下を生じる。この付着
強度の低下は、機械的強度を必要とする外部への
電気的接続のためのリード取り出し用の電極にお
いて大きな問題となる。[Problems to be Solved by the Invention] Although this sputter deposition method has the great advantage of being able to form an insulating film at a low temperature, it also has the disadvantage of damaging the surface of a semiconductor or the like during the formation. This results in a decrease in adhesion strength between the sputtered insulating film and the substrate such as a semiconductor. This decrease in adhesion strength poses a major problem in electrodes for lead extraction for external electrical connections that require mechanical strength.
本発明は、上記に鑑みなされたもので、金属膜
上に堆積させたスパツタ絶縁膜と金属との間の付
着力が極めて大きいことを利用して、スパツタ絶
縁膜と半導体または半導体の酸化物の間に金属膜
を挿入することにより、スパツタ絶縁膜を構成要
素として用いる半導体素子の、リード取り出し用
の電極の機械的強度を強めるための優れた電極構
造を提供することを目的としてなされたものであ
る。以下に本発明について説明する。 The present invention was made in view of the above, and takes advantage of the extremely strong adhesion between the sputtered insulating film deposited on the metal film and the metal to form a bond between the sputtered insulating film and the semiconductor or semiconductor oxide. The purpose was to provide an excellent electrode structure for increasing the mechanical strength of lead extraction electrodes for semiconductor devices that use sputtered insulating films as constituent elements by inserting a metal film between them. be. The present invention will be explained below.
［問題点を解決するための手段］
本発明は、スパツタ絶縁膜を構成要素として用
いる半導体素子において、このスパツタ絶縁膜上
に設けた外部接続用リード電極の機械的強度を強
くするために、リード電極下のスパツタ絶縁膜と
半導体または半導体の酸化膜の間に補強金属膜を
挿入した構造を用いることを特徴とするものであ
る。[Means for Solving the Problems] The present invention provides a semiconductor device using a sputtered insulating film as a component, in which a lead electrode is formed on the sputtered insulating film to strengthen the mechanical strength of the lead electrode for external connection provided on the sputtered insulating film. This method is characterized by using a structure in which a reinforcing metal film is inserted between a sputtered insulating film under the electrode and a semiconductor or semiconductor oxide film.
［作用］
金属膜上に堆積したスパツタ絶縁膜と金属の付
着力が極めて大きいことに着目し、スパツタ絶縁
膜と半導体または半導体の酸化膜の間に金属膜を
挿入する構造とすることにより、スパツタ絶縁膜
を構成要素として用いる半導体素子のリード取り
出し用の電極の機械的強度が高められる。[Function] Focusing on the extremely strong adhesion between the sputtered insulating film deposited on the metal film and the metal, we created a structure in which the metal film is inserted between the sputtered insulating film and the semiconductor or semiconductor oxide film, thereby reducing the sputtering. The mechanical strength of an electrode for lead extraction of a semiconductor device using an insulating film as a component is increased.
［実施例］
第１図は、リード取り出し用の電極下のスパツ
タ絶縁膜と半導体の間に金属膜を構成要素として
用いる半導体素子の電極構造に関する本発明の実
施例の概略構成図である。リード取り出し用電極
３（以下単にリード電極という）は、外部接続用
リード線５（以下単にリード線という）を取り付
けるためのものであり、スパツタ絶縁膜２によつ
て半導体１と電気的に絶縁されている。半導体１
とスパツタ絶縁膜２の間の補強金属膜４はリード
電極３の下部を完全に覆つている。この補強金属
膜４によつて、スパツタ絶縁膜２と半導体基板１
の間の付着力を増し、リード電極３にリード線５
を強固に取り付けられるようになつている。[Embodiment] FIG. 1 is a schematic diagram of an embodiment of the present invention relating to an electrode structure of a semiconductor element using a metal film as a component between a sputtered insulating film under an electrode for lead extraction and a semiconductor. The lead extraction electrode 3 (hereinafter simply referred to as a lead electrode) is for attaching an external connection lead wire 5 (hereinafter simply referred to as a lead wire), and is electrically insulated from the semiconductor 1 by a sputtered insulating film 2. ing. semiconductor 1
The reinforcing metal film 4 between the lead electrode 3 and the sputtered insulating film 2 completely covers the lower part of the lead electrode 3. By this reinforcing metal film 4, the sputtered insulating film 2 and the semiconductor substrate 1 are
Increase the adhesion between the lead electrode 3 and the lead wire 5.
It is designed to be firmly attached.
第２図は半導体基板１の表面がこの半導体の酸
化膜１’になつている場合である。従つて、この
場合には補強金属膜４は、半導体の酸化膜とスパ
ツタ絶縁膜の間の付着力を増す働きをする。 FIG. 2 shows a case where the surface of the semiconductor substrate 1 is an oxide film 1' of this semiconductor. Therefore, in this case, the reinforcing metal film 4 serves to increase the adhesion between the semiconductor oxide film and the sputtered insulating film.
第３図は補強金属膜４が半導体基板１とこの半
導体の酸化膜１’の両方に接した構造の場合であ
る。補強金属膜が半導体の酸化膜によつて半導体
基板から電気的に絶縁されることを避けるため
に、補強金属膜の一部が直接半導体基板に接する
ようになつている。第１図〜第３図にの実施例で
示したスパツタ絶縁膜として窒化シリコン、酸化
シリコン、酸化アルミニウムを用いる場合が多
い。 FIG. 3 shows a structure in which the reinforcing metal film 4 is in contact with both the semiconductor substrate 1 and the semiconductor oxide film 1'. In order to prevent the reinforcing metal film from being electrically insulated from the semiconductor substrate by the semiconductor oxide film, a portion of the reinforcing metal film is in direct contact with the semiconductor substrate. Silicon nitride, silicon oxide, or aluminum oxide is often used as the sputtered insulating film shown in the embodiments shown in FIGS. 1 to 3.
また、第１図〜第３図の実施例で示した補強金
属膜として、特に他の物質との付着力の強いCr、
Ni、Tiを用いるとより効果的である。補強金属
膜は必ずしも一種類の金属のみを用いる一層膜で
ある必要はない。スパツタ膜と接する上面と半導
体または半導体の酸化膜と接する下面にのみ付着
力の強いCr、Ni、Tiを用い、他の金属を中間に
挟んだ構造であつてもよい。 In addition, as the reinforcing metal film shown in the embodiments of FIGS. 1 to 3, Cr, which has particularly strong adhesion to other substances,
It is more effective to use Ni and Ti. The reinforcing metal film does not necessarily have to be a single layer film using only one type of metal. It may be a structure in which Cr, Ni, or Ti with strong adhesion is used only on the upper surface in contact with the sputtered film and the lower surface in contact with the semiconductor or semiconductor oxide film, and other metals are sandwiched in between.
スパツタ絶縁膜を半導体素子の構成要素として
用いるのは、低温で半導体素子を製作しなければ
ならない化合物半導体においてその必要性が大き
い。化合物半導体の中でも、ー属化合物の
InSb、GaAs、InAs、InPやこれらを含む混合結
晶、あるいはー属化合物のCdHgTeが特に低
温で半導体素子を製作する必要性が高い具体的な
半導体の例として考えられる。従つて、これらの
半導体が本発明の電極構造の構成要素である補強
金属を用いる効果が著しく大きい具体的な半導体
の例である。 The use of sputtered insulating films as constituent elements of semiconductor devices is highly necessary in compound semiconductors where semiconductor devices must be manufactured at low temperatures. Among compound semiconductors, -group compounds
InSb, GaAs, InAs, InP, mixed crystals containing these, and CdHgTe, which is a -group compound, can be considered as specific examples of semiconductors in which it is particularly necessary to manufacture semiconductor devices at low temperatures. Therefore, these semiconductors are specific examples of semiconductors in which the effect of using the reinforcing metal, which is a component of the electrode structure of the present invention, is extremely large.
［発明の効果］
以上説明したように、本発明は低温で形成でき
るスパツタ絶縁膜を構成要素として用いる半導体
素子において、強い付着力を必要としているリー
ド電極下部のスパツタ絶縁膜と半導体または半導
体の酸化膜との間に補強金属を挿入することによ
り、必要とする強い付着力を得ることを特徴とし
ている。[Effects of the Invention] As explained above, the present invention is applicable to a semiconductor device that uses a sputtered insulating film that can be formed at a low temperature as a component. It is characterized by the required strong adhesion force being obtained by inserting a reinforcing metal between the film and the film.
リード電極は半導体素子において必ず必要なも
のであり、半導体素子の信頼性に大きな影響を与
える部分である。従つて、リード電極の機械的強
度を高めることに大きな効果を持つ本発明は、電
子産業に寄与するところ極めて大きい。 A lead electrode is absolutely necessary in a semiconductor device, and is a part that greatly affects the reliability of the semiconductor device. Therefore, the present invention, which is highly effective in increasing the mechanical strength of lead electrodes, will greatly contribute to the electronic industry.
第１図、第２図、第３図は本発明の半導体素子
の電極構造の具体的な実施例を説明するための概
略図である。
図中、１は半導体基板、１’は半導体１の酸化
膜、２はスパツタ絶縁膜、３はリード電極、４は
補強金属膜、５はリード線である。
FIG. 1, FIG. 2, and FIG. 3 are schematic diagrams for explaining specific embodiments of the electrode structure of the semiconductor device of the present invention. In the figure, 1 is a semiconductor substrate, 1' is an oxide film of the semiconductor 1, 2 is a sputtered insulating film, 3 is a lead electrode, 4 is a reinforcing metal film, and 5 is a lead wire.
Claims (1)
縁膜を堆積形成し、該スパツタ絶縁膜上にリード
電極を設けるようにした半導体素子の電極構造に
おいて、リード電極下の半導体或は半導体の酸化
膜上に補強金属膜を形成した後スパツタ絶縁膜を
堆積形成してなることを特徴とする半導体素子の
電極構造。 ２ 特許請求の範囲第１項に記載の半導体素子の
電極構造において、補強金属膜が半導体と半導体
の酸化膜の両方に接することを特徴とする半導体
素子の電極構造。 ３ 特許請求の範囲第１項または第２項に記載の
半導体素子の電極構造において、スパツタ絶縁膜
として酸化シリコン、窒化シリコン、酸化アルミ
ニウムのいずれか一つまたは２種類以上を積層し
た複合膜を構成要素として用いていることを特徴
とする半導体素子の電極構造。 ４ 特許請求の範囲第１，第２項または第３項に
記載の半導体素子の電極構造において、スパツタ
絶縁膜と半導体または半導体の酸化膜の間に挿入
する補強金属膜として、スパツタ絶縁膜と接する
部分、或は半導体または半導体の酸化膜に接する
部分にCr、Ni、Tiのいずれかを用いることを特
徴とする半導体素子の電極構造。 ５ 特許請求の範囲第１項，第２項，第３項また
は第４項に記載の半導体素子の電極構造におい
て、半導体として化合物半導体を用いることを特
徴とする半導体素子の電極構造。 ６ 特許請求の範囲第５項に記載の半導体素子の
電極構造において、化合物半導体としてInSb、
InAs、GaAs、InPまたはこれらの混合結晶、或
はCdHgTeを用いることを特徴とする半導体素子
の電極構造。[Claims] 1. In an electrode structure of a semiconductor device in which a sputtered insulating film is deposited on a semiconductor or an oxide film of the semiconductor, and a lead electrode is provided on the sputtered insulating film, the semiconductor under the lead electrode Alternatively, an electrode structure for a semiconductor device, characterized in that a reinforcing metal film is formed on a semiconductor oxide film, and then a sputtered insulating film is deposited. 2. The electrode structure for a semiconductor device according to claim 1, wherein the reinforcing metal film is in contact with both the semiconductor and the oxide film of the semiconductor. 3. In the electrode structure of a semiconductor device according to claim 1 or 2, the sputtered insulating film is a composite film in which one or more of silicon oxide, silicon nitride, and aluminum oxide are laminated. An electrode structure of a semiconductor device characterized by being used as an element. 4. In the electrode structure of a semiconductor device according to claim 1, 2, or 3, a reinforcing metal film that is inserted between the sputtered insulating film and the semiconductor or the oxide film of the semiconductor is in contact with the sputtered insulating film. 1. An electrode structure for a semiconductor device, characterized in that one of Cr, Ni, and Ti is used in a portion or a portion in contact with a semiconductor or an oxide film of the semiconductor. 5. An electrode structure for a semiconductor device according to claim 1, 2, 3, or 4, characterized in that a compound semiconductor is used as the semiconductor. 6 In the electrode structure of the semiconductor device according to claim 5, InSb,
An electrode structure for a semiconductor device characterized by using InAs, GaAs, InP or a mixed crystal thereof, or CdHgTe.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP61152388A JPS637649A (en) | 1986-06-28 | 1986-06-28 | Electrode structure for semiconductor element |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP61152388A JPS637649A (en) | 1986-06-28 | 1986-06-28 | Electrode structure for semiconductor element |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS637649A JPS637649A (en) | 1988-01-13 |
| JPH0582969B2 true JPH0582969B2 (en) | 1993-11-24 |
Family
ID=15539424
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP61152388A Granted JPS637649A (en) | 1986-06-28 | 1986-06-28 | Electrode structure for semiconductor element |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS637649A (en) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2010177248A (en) * | 2009-01-27 | 2010-08-12 | Anritsu Corp | Semiconductor device and method of manufacturing the same |
-
1986
- 1986-06-28 JP JP61152388A patent/JPS637649A/en active Granted
Also Published As
| Publication number | Publication date |
|---|---|
| JPS637649A (en) | 1988-01-13 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US4772935A (en) | Die bonding process | |
| JP3126977B2 (en) | Reinforced direct bond copper structure | |
| US9852939B2 (en) | Solderable contact and passivation for semiconductor dies | |
| US20200075530A1 (en) | Electronic Device with Multi-Layer Contact and System | |
| JPH03214717A (en) | Electrode for electric ceramic oxide apparatus | |
| JPH0582991B2 (en) | ||
| US4848643A (en) | Process of bonding plates | |
| JPH0799169A (en) | Manufacture of silicon carbide electronic device | |
| US6191485B1 (en) | Semiconductor device | |
| JPH0582969B2 (en) | ||
| US6060771A (en) | Connecting lead for semiconductor devices and method for fabricating the lead | |
| JPH0193149A (en) | Semiconductor device | |
| US4921158A (en) | Brazing material | |
| JPS60193337A (en) | Manufacture of semiconductor device | |
| JPS6220338A (en) | Manufacture of semiconductor device | |
| JPS5873136A (en) | Method of producing semiconductor device | |
| JP2742686B2 (en) | Semiconductor device | |
| JPS60167352A (en) | Semiconductor element | |
| JPH0555296A (en) | Semiconductor device | |
| JPS63318139A (en) | Metallic thin film wiring | |
| JPS59161885A (en) | Hall element | |
| JPH03191527A (en) | Electrode structure of semiconductor element | |
| JPH0391240A (en) | Method of forming metallized electrode wiring | |
| JPS6329437B2 (en) | ||
| JPH01149428A (en) | Semiconductor device |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| EXPY | Cancellation because of completion of term |