JPS637649A - Electrode structure for semiconductor element - Google Patents
Electrode structure for semiconductor elementInfo
- Publication number
- JPS637649A JPS637649A JP61152388A JP15238886A JPS637649A JP S637649 A JPS637649 A JP S637649A JP 61152388 A JP61152388 A JP 61152388A JP 15238886 A JP15238886 A JP 15238886A JP S637649 A JPS637649 A JP S637649A
- Authority
- JP
- Japan
- Prior art keywords
- semiconductor
- insulating film
- film
- electrode structure
- electrode
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 59
- 229910052751 metal Inorganic materials 0.000 claims abstract description 21
- 239000002184 metal Substances 0.000 claims abstract description 21
- 230000003014 reinforcing effect Effects 0.000 claims abstract description 15
- 150000001875 compounds Chemical class 0.000 claims description 4
- 229910052759 nickel Inorganic materials 0.000 claims description 3
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 2
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 2
- TWNQGVIAIRXVLR-UHFFFAOYSA-N oxo(oxoalumanyloxy)alumane Chemical compound O=[Al]O[Al]=O TWNQGVIAIRXVLR-UHFFFAOYSA-N 0.000 claims description 2
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 2
- 229910052814 silicon oxide Inorganic materials 0.000 claims description 2
- 229910001218 Gallium arsenide Inorganic materials 0.000 claims 1
- 229910000661 Mercury cadmium telluride Inorganic materials 0.000 claims 1
- 239000002131 composite material Substances 0.000 claims 1
- 239000013078 crystal Substances 0.000 claims 1
- WPYVAWXEWQSOGY-UHFFFAOYSA-N indium antimonide Chemical group [Sb]#[In] WPYVAWXEWQSOGY-UHFFFAOYSA-N 0.000 claims 1
- 230000002787 reinforcement Effects 0.000 claims 1
- WABPQHHGFIMREM-UHFFFAOYSA-N lead(0) Chemical compound [Pb] WABPQHHGFIMREM-UHFFFAOYSA-N 0.000 abstract description 8
- 239000000758 substrate Substances 0.000 abstract description 7
- 238000000034 method Methods 0.000 description 4
- 238000000605 extraction Methods 0.000 description 3
- 238000010586 diagram Methods 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 238000004544 sputter deposition Methods 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 1
- 239000000470 constituent Substances 0.000 description 1
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 1
- 239000010931 gold Substances 0.000 description 1
- 229910052737 gold Inorganic materials 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 150000002739 metals Chemical class 0.000 description 1
- 239000000523 sample Substances 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
- 239000013077 target material Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
Landscapes
- Local Oxidation Of Silicon (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
Description
【発明の詳細な説明】
［産業上の利用分野コ
本発明は、半導体素子の構成要素としてスパッタ絶縁膜
を用いる場合の半導体素子の電極構造に関するものであ
る。本発明によって、スパッタ絶縁膜を構成要素とする
半導体素子の信頼性を高めることが出来るため、電子産
業分野で大きな寄与の方法の中でも、アルゴンなどの不
活性ガスまたは不活性ガスを含むガス中の放電を利用し
て、ターゲット物質の表面を削り、半導体なとの基板上
に堆積させる生成法はスパッタ堆積法といわれている。DETAILED DESCRIPTION OF THE INVENTION [Industrial Field of Application] The present invention relates to an electrode structure of a semiconductor device when a sputtered insulating film is used as a component of the semiconductor device. The present invention makes it possible to improve the reliability of semiconductor devices with sputtered insulating films as constituent elements. A production method that uses electrical discharge to scrape the surface of a target material and deposit it on a substrate such as a semiconductor is called a sputter deposition method.
このスパッタ絶縁膜上に電極を設ける場合、従来は、電
極の機械的強度を高めるための配慮は特には払われてい
ない。When providing electrodes on this sputtered insulating film, conventionally no particular consideration has been given to increasing the mechanical strength of the electrodes.
［発明が解決しようとしている問題点］このスパッタ堆
積法は低い温度で絶縁膜を生成できるという大きな利点
があるが、反面、生成の際に半導体なとの表面に損慣を
与えるという欠点もある。このため、スパッタ絶縁膜と
半導体なとの基板の間の付着強度の低下を生じる。この
付着強度の低下は、機械的強度を必要とする外部への電
気的接続のためのリード取り出し用の電極において大き
な問題となる。[Problem to be solved by the invention] This sputter deposition method has the great advantage of being able to generate an insulating film at a low temperature, but on the other hand, it also has the disadvantage of causing damage to the surface of the semiconductor during the formation. . This results in a decrease in adhesion strength between the sputtered insulating film and the semiconductor substrate. This decrease in adhesion strength poses a major problem in electrodes for lead extraction for external electrical connections that require mechanical strength.
本発明は・、上記に鑑みなされたもので、金属模索とし
て用いる半導体素子の、リード取り出し用の電極の機械
的強度を強めるための優れた電極構造を提供することを
目的としてなされたものである。以下に本発明について
説明する。The present invention has been made in view of the above, and has been made for the purpose of providing an excellent electrode structure for increasing the mechanical strength of an electrode for lead extraction of a semiconductor element used as a metal probe. . The present invention will be explained below.
［問題点を解決するための手段］
本発明は、スパッタ絶縁膜を構成要素として用いる半導
体素子において、このスパッタ絶縁膜上に設けた外部接
続用リード電極の機械的強度を強くするために、リード
電極下のスパッタ絶縁膜と半導体または半導体の酸化膜
の間に補強金属膜を挿入した構造を用いることを特徴と
するものである。[Means for Solving the Problems] The present invention provides a semiconductor device using a sputtered insulating film as a component, in which lead electrodes are formed on the sputtered insulating film to strengthen the mechanical strength of the lead electrodes for external connection provided on the sputtered insulating film. This method is characterized by using a structure in which a reinforcing metal film is inserted between a sputtered insulating film under an electrode and a semiconductor or semiconductor oxide film.
［作用コ
金属膜上に堆積したスパッタ絶縁膜と金属の付着力が極
めて大きいことに着目し、スパッタ絶縁［実施例コ
第１図は、リード取り出し用の電極下のスパッタ絶縁膜
と半導体の間に金属膜を構成要素として用いる半導体素
子の電極構造に関する本発明の実施例の概略構成図であ
る。リード取り出し用電極３（以下単にリード電極とい
う）は、外部接続用リード線６（以下単にリード線とい
う）を取り付けるためのものであり、スパッタ絶縁膜２
によって半導体１と電気的に絶縁されている。半導体１
とスパッタ絶縁膜２の間の補強金属膜４はリード電１５
ｉ３の下部を完全に覆っている。この補強金属膜４によ
って、スパッタ絶縁膜２と半導体基板ｌの間の付着力を
増し、リード電極３にリード線５を強固に取り付けられ
るようになっている。[Working example] Focusing on the extremely strong adhesion between the sputtered insulating film deposited on the metal film and the metal, sputter insulation [Example Fig. 1] 1 is a schematic configuration diagram of an embodiment of the present invention relating to an electrode structure of a semiconductor device using a metal film as a component; FIG. The lead extraction electrode 3 (hereinafter simply referred to as a lead electrode) is for attaching an external connection lead wire 6 (hereinafter simply referred to as a lead wire), and is used to attach a lead wire 6 for external connection (hereinafter simply referred to as a lead wire).
It is electrically insulated from the semiconductor 1 by. semiconductor 1
The reinforcing metal film 4 between the sputtered insulating film 2 and the lead electrode 15
It completely covers the bottom of the i3. This reinforcing metal film 4 increases the adhesion between the sputtered insulating film 2 and the semiconductor substrate l, so that the lead wire 5 can be firmly attached to the lead electrode 3.
第２図は半導体基板ｌの表面がこの半導体の酸化膜１゛
になっている場合である。従って、この場合には補強金
属膜４は、半導体の酸化膜とスパッタ絶縁膜の間の付着
力を増す働きをする。FIG. 2 shows a case where the surface of the semiconductor substrate 1 is an oxide film 1 of this semiconductor. Therefore, in this case, the reinforcing metal film 4 serves to increase the adhesion between the semiconductor oxide film and the sputtered insulating film.
補強金属膜の一部が直接半導体基板に接するようになっ
ている。 第１図〜第３図にの実施例で示したスパッタ
絶縁膜として窒化シリコン、酸化シリコン、酸化アルミ
ニウムを用いる場合が多い。A portion of the reinforcing metal film is in direct contact with the semiconductor substrate. Silicon nitride, silicon oxide, or aluminum oxide is often used as the sputtered insulating film shown in the embodiments shown in FIGS. 1 to 3.
また、第１図〜第３図の実施例で示した補強金属膜とし
て、特に池の物質との付着力の強いＣｒ、Ｎｉ、Ｔｉを
用いるとより効果的である。補強金、ｌＸ膜は必ずしも
一種類の金属のみを用いるーｐｓ膜である必要はない。Furthermore, it is more effective to use Cr, Ni, and Ti, which have particularly strong adhesion to pond substances, as the reinforcing metal film shown in the embodiments of FIGS. 1 to 3. The reinforcing gold and IX films do not necessarily need to be ps films using only one type of metal.
スパッタ膜と接する上面と半導体または半導体の酸化膜
と接する下面にのみ付着力の強いＣｒ、Ｎｉ、Ｔｉを用
い、他の金属を中間に挟んだ構造であってもよい。It may be a structure in which Cr, Ni, or Ti, which has strong adhesion, is used only on the upper surface in contact with the sputtered film and the lower surface in contact with the semiconductor or the oxide film of the semiconductor, and other metals are sandwiched in between.
スパッタ絶縁膜を半導体素子の構成要素として用いるの
は、低温で半導体素子を製作しなければならない化合物
半導体においてその必要性が太き必要性が高い具体的な
半導体の例として考えられる。従って、これらの半導体
が本発明の電極構造の構成要素である補強金属を用いる
効果が著しく大きい具体的な半導体の例である。The use of a sputtered insulating film as a component of a semiconductor device can be considered as a specific example of a compound semiconductor in which the necessity is high in compound semiconductors where semiconductor devices must be manufactured at low temperatures. Therefore, these semiconductors are specific examples of semiconductors in which the effect of using the reinforcing metal, which is a component of the electrode structure of the present invention, is extremely large.
［発明の効果コ
以上説明したように、本発明は低温で形成できるスパッ
タ絶縁膜を構成要素として用いる半導体素子において、
強い付着力を必要としているり一ド電極下部のスパッタ
絶縁膜と半導体または半導体の酸化膜との間に補強金属
を挿入することにより、必要とする強い付着力を得るこ
とを特徴としている。[Effects of the Invention] As explained above, the present invention provides a semiconductor device that uses a sputtered insulating film that can be formed at a low temperature as a component.
The method is characterized in that the required strong adhesion force is obtained by inserting a reinforcing metal between the sputtered insulating film and the semiconductor or semiconductor oxide film below the electrode, which requires strong adhesion force.
リード電極は半導体素子において必ず必要なものであり
、半導体素子の信頼性に大きな影響を与える部分である
。従って、リード電極の機械的強度を高めることに大き
な効果を持つ本発明は、電子産業に寄与するところ極め
て大きい。A lead electrode is absolutely necessary in a semiconductor device, and is a part that greatly affects the reliability of the semiconductor device. Therefore, the present invention, which is highly effective in increasing the mechanical strength of lead electrodes, will greatly contribute to the electronic industry.
第１図、第２図、第３図は本発明の半導体素子の電極構
造の具体的な実施例を説明するための概略図である。
図中、１は半導体基板、１′は半導体１の酸化膜、２は
スパッタ絶縁膜、３はリード電極、４は補強金属膜、５
はリード線である。
第１図
第２図
第３図FIG. 1, FIG. 2, and FIG. 3 are schematic diagrams for explaining specific embodiments of the electrode structure of the semiconductor device of the present invention. In the figure, 1 is a semiconductor substrate, 1' is an oxide film of semiconductor 1, 2 is a sputtered insulating film, 3 is a lead electrode, 4 is a reinforcing metal film, and 5
is the lead wire. Figure 1 Figure 2 Figure 3
Claims (6)
体素子において、リード電極下のスパッタ絶縁膜と半導
体または半導体の酸化膜の間に補強金属膜を挿入した構
造を用いることを特徴とする半導体素子の電極構造。(1) A semiconductor device using a sputtered insulating film as a component, characterized in that a reinforcing metal film is inserted between the sputtered insulating film under the lead electrode and the semiconductor or the oxide film of the semiconductor. electrode structure.
電極構造において、補強金属膜が半導体と半導体の酸化
膜の両方に接することを特徴とする半導体素子の電極構
造。(2) An electrode structure for a semiconductor device according to claim (1), wherein the reinforcing metal film is in contact with both the semiconductor and the oxide film of the semiconductor.
載の半導体素子の電極構造において、スパッタ絶縁膜と
して酸化シリコン、窒化シリコン、酸化アルミニウムの
いずれか一つまたは２種類以上を積層した複合膜を構成
要素として用いていることを特徴とする半導体素子の電
極構造。(3) In the electrode structure of a semiconductor device according to claim (1) or (2), one or more of silicon oxide, silicon nitride, and aluminum oxide is used as the sputtered insulating film. An electrode structure for a semiconductor device characterized by using a laminated composite film as a component.
（３）項に記載の半導体素子の電極構造において、スパ
ッタ絶縁膜と半導体または半導体の酸化膜の間に挿入す
る補強金属膜として、スパッタ絶縁膜と接する部分、或
いは、半導体または半導体の酸化膜に接する部分にＣｒ
、Ｎｉ、Ｔｉのいずれかを用いることを特徴とする半導
体素子の電極構造。(4) In the electrode structure of a semiconductor device according to claim (1), (2), or (3), reinforcement inserted between a sputtered insulating film and a semiconductor or an oxide film of a semiconductor. Cr is used as the metal film in the part in contact with the sputtered insulating film or in the part in contact with the semiconductor or semiconductor oxide film.
, Ni, or Ti.
）項または第（４）項に記載の半導体素子の電極構造に
おいて、半導体として化合物半導体を用いることを特徴
とする半導体素子の電極構造。(5) Claims (1), (2), (3)
An electrode structure for a semiconductor device according to item (4) or (4), characterized in that a compound semiconductor is used as the semiconductor.
電極構造において、化合物半導体としてＩｎＳｂ、Ｉｎ
Ａｓ、ＧａＡｓ、ＩｎＰまたはこれらの混合結晶、或い
は、ＣｄＨｇＴｅを用いることを特徴とする半導体素子
の電極構造。(6) In the electrode structure of the semiconductor device according to claim (5), the compound semiconductor is InSb, In
An electrode structure for a semiconductor device characterized by using As, GaAs, InP, a mixed crystal thereof, or CdHgTe.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP61152388A JPS637649A (en) | 1986-06-28 | 1986-06-28 | Electrode structure for semiconductor element |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP61152388A JPS637649A (en) | 1986-06-28 | 1986-06-28 | Electrode structure for semiconductor element |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS637649A true JPS637649A (en) | 1988-01-13 |
| JPH0582969B2 JPH0582969B2 (en) | 1993-11-24 |
Family
ID=15539424
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP61152388A Granted JPS637649A (en) | 1986-06-28 | 1986-06-28 | Electrode structure for semiconductor element |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS637649A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2010177248A (en) * | 2009-01-27 | 2010-08-12 | Anritsu Corp | Semiconductor device and method of manufacturing the same |
-
1986
- 1986-06-28 JP JP61152388A patent/JPS637649A/en active Granted
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2010177248A (en) * | 2009-01-27 | 2010-08-12 | Anritsu Corp | Semiconductor device and method of manufacturing the same |
Also Published As
| Publication number | Publication date |
|---|---|
| JPH0582969B2 (en) | 1993-11-24 |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| EXPY | Cancellation because of completion of term |