JPH03238865A - Semiconductor element - Google Patents
Semiconductor elementInfo
- Publication number
- JPH03238865A JPH03238865A JP3447890A JP3447890A JPH03238865A JP H03238865 A JPH03238865 A JP H03238865A JP 3447890 A JP3447890 A JP 3447890A JP 3447890 A JP3447890 A JP 3447890A JP H03238865 A JPH03238865 A JP H03238865A
- Authority
- JP
- Japan
- Prior art keywords
- layer
- phosphorus
- plating
- electrode
- element base
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 13
- PXHVJJICTQNCMI-UHFFFAOYSA-N nickel Substances [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 claims abstract description 75
- 229910052698 phosphorus Inorganic materials 0.000 claims abstract description 22
- 239000011574 phosphorus Substances 0.000 claims abstract description 22
- 238000007747 plating Methods 0.000 claims abstract description 22
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 claims abstract description 21
- 229910052759 nickel Inorganic materials 0.000 claims abstract description 15
- 239000004020 conductor Substances 0.000 claims abstract description 11
- 229910052710 silicon Inorganic materials 0.000 claims description 7
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 6
- 239000010703 silicon Substances 0.000 claims description 6
- BHEPBYXIRTUNPN-UHFFFAOYSA-N hydridophosphorus(.) (triplet) Chemical compound [PH] BHEPBYXIRTUNPN-UHFFFAOYSA-N 0.000 claims description 4
- 238000010030 laminating Methods 0.000 claims 1
- 229910000679 solder Inorganic materials 0.000 abstract description 13
- 230000007797 corrosion Effects 0.000 abstract description 5
- 238000005260 corrosion Methods 0.000 abstract description 5
- 238000000034 method Methods 0.000 abstract description 3
- 238000005476 soldering Methods 0.000 abstract description 2
- 235000012431 wafers Nutrition 0.000 description 14
- 238000005219 brazing Methods 0.000 description 6
- WABPQHHGFIMREM-UHFFFAOYSA-N lead(0) Chemical compound [Pb] WABPQHHGFIMREM-UHFFFAOYSA-N 0.000 description 4
- 239000000463 material Substances 0.000 description 4
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 3
- 229910052796 boron Inorganic materials 0.000 description 3
- 239000006071 cream Substances 0.000 description 3
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 2
- 229910045601 alloy Inorganic materials 0.000 description 2
- 239000000956 alloy Substances 0.000 description 2
- 238000004519 manufacturing process Methods 0.000 description 2
- 229910052802 copper Inorganic materials 0.000 description 1
- 239000010949 copper Substances 0.000 description 1
- 230000006378 damage Effects 0.000 description 1
- 230000007423 decrease Effects 0.000 description 1
- 230000006866 deterioration Effects 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- 238000007772 electroless plating Methods 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 239000012535 impurity Substances 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 229910052751 metal Inorganic materials 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
Landscapes
- Chemically Coating (AREA)
- Electrodes Of Semiconductors (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は、接続導体のろう付けのためにシリコン素体の
表面に金属電極を設けた半導体素子に関する。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor device in which a metal electrode is provided on the surface of a silicon body for brazing connection conductors.
半導体素子においては、不純物拡散等によりＰＮ接合を
形成したＳｉウェーハあるいはＳｉチップなどのＳｉ素
体との電気的接続を行う必要がある。そのためには、従
来ＳｉウェーハにＮｉめっきをほどこして電極とし、ウ
ェーハのままあるいはチップに分割後、その電極に銅な
どからなる接続導体をはんだを用いてろう付けしていた
。電極の形成には、先ず、ＰＮ接合を形成したＳｉウェ
ーハの表面にめっきにより第−Ｎｉ層を被着する。 Ｎ
ｉの材質は燐含有量２〜５％の低燐タイプあるいは燐含
有量６〜９％の中燐タイプであり、Ｎｉ層の厚さ０．３
〜１．Ｏｎである０次に第−Ｎｉ層を被着したＳｉウェ
ーハを３００〜７５０℃の温度で約１時間熱処理し、第
−Ｎｉ層とＳｉウェーハの界面にＮｉとＳｉの合金層を
形成する。熱処理を終えたＳｉウェーへの第−Ｎｉ層の
上にめっきにより第二Ｎｉ層を被着し、はんだのぬれ性
の同上を図る。第二Ｎｉ層のＮｉの材質としては、硼素
含有量２〜３％の低ポロンタイプあるいは低燐タイプが
用いられ、Ｎｉ層の厚さは０．２〜１．０−である。In semiconductor devices, it is necessary to make electrical connections with Si elements such as Si wafers or Si chips in which PN junctions are formed by impurity diffusion or the like. To achieve this, conventionally, a Si wafer is plated with Ni to form an electrode, and a connecting conductor made of copper or the like is brazed to the electrode using solder, either as a wafer or after being divided into chips. To form the electrode, first, a -th Ni layer is deposited by plating on the surface of the Si wafer on which the PN junction has been formed. N
The material of i is a low phosphorus type with a phosphorus content of 2 to 5% or a medium phosphorus type with a phosphorus content of 6 to 9%, and the thickness of the Ni layer is 0.3%.
~1. The Si wafer coated with the 0th-order -Ni layer that is on is heat-treated at a temperature of 300 to 750° C. for about 1 hour to form an alloy layer of Ni and Si at the interface between the -Ni layer and the Si wafer. A second Ni layer is deposited by plating on the -th Ni layer of the heat-treated Si wafer to improve solder wettability. As the Ni material of the second Ni layer, a low poron type or a low phosphorus type with a boron content of 2 to 3% is used, and the thickness of the Ni layer is 0.2 to 1.0.
このあと、第一、第二Ｎｉ層を表面に有するＳｉウェー
ハを分割してチップにし、はんだ板あるいはクリームは
んだ等をろう材として接続導体とろう付けする。 ＰＮ
接合を形成したシリコン板を何枚も積重ねたスタックタ
イプの高圧ダイオードの場合は、両面にＮｉ層極を設け
たＳｉウェーハを、ろう材としてのはんだ板あるいはク
リームはんだ等を用いてろう付けして積層する。Thereafter, the Si wafer having the first and second Ni layers on its surface is divided into chips and brazed with a connecting conductor using a solder plate or cream solder as a brazing material. P.N.
In the case of a stack-type high-voltage diode in which a number of bonded silicon plates are stacked, a Si wafer with Ni layer electrodes on both sides is brazed using a solder plate or cream solder as a brazing material. Stack.
しかし、従来の半導体素子では、第一にＮｉ電極に対す
るはんだのぬれ性が良好でないため、接続導体との均一
なろう付けができないこと、第二にＳｉウェーハにＮｉ
層から応力が加わり、Ｓｉウェーハの内部に歪みが生じ
、特性劣化ないしチンプが破壊に至ることの問題があっ
た。However, in conventional semiconductor devices, firstly, the wettability of solder to Ni electrodes is not good, so uniform brazing with connecting conductors cannot be achieved, and secondly, Ni is not used on Si wafers.
There is a problem that stress is applied from the layers, causing distortion inside the Si wafer, resulting in deterioration of characteristics or destruction of chimps.
本発明の目的は、以上二つの問題を解決し、Ｓｉ素体上
の電極と接続導体とのろう付けが均一に行われ、また電
極層からＳｉ素体に加わる応力が小さくて信頼性の高い
半導体素子を提供することにある。The purpose of the present invention is to solve the above two problems, to achieve uniform brazing between the electrode on the Si element body and the connecting conductor, and to achieve high reliability by reducing the stress applied to the Si element body from the electrode layer. The purpose of the present invention is to provide semiconductor devices.
Ｃ課題を解決するための手段〕
上記の目的を遠戚するために、本発明は、シリコン素体
の表面に設けられた電極に接続導体がはんだ付けされる
半導体素子において、電極が素体側から燐含有量６〜９
％の中燐タイプ・ニッケルめっきにより形成された厚さ
０．２〜１．０μの第一ニッケル層と燐含有１２〜５％
の低燐タイプ・ニッケルめっきにより形成された厚さ０
．５〜１．５μｍの第二ニッケル層を積層してなるもの
とする。Means for Solving Problem C] In order to achieve the above-mentioned object distantly, the present invention provides a semiconductor element in which a connecting conductor is soldered to an electrode provided on the surface of a silicon element, in which the electrode is connected from the element side. Phosphorus content 6-9
% medium phosphorus type nickel plating with a thickness of 0.2-1.0μ first nickel layer and phosphorus content of 12-5%
0 thickness formed by low phosphorus type nickel plating.
．． The second nickel layer is laminated with a thickness of 5 to 1.5 μm.
Ｓｉ素体に被着したＮｉめっき層から加わる応力は、め
っき層とＳｉとの熱膨張係数の差乙二基づく、シリコン
との熱膨張係数の差は、中燐タイプのＮｉめっき層、低
燐タイプのＮｉめっき層、低ボロンタイプのＮｉめっき
層の順に大きくなる。シリコン素体への応力は、特に素
体に接する層の熱膨張係数に支配される部分が大きいの
で、Ｓｉ素体側の第−Ｎｉ層に中燐タイプ・ニッケルめ
っきを適用してＳｉ素体への応力を少なくし、Ｓｉ素体
内の歪みを小さくする。しかし、めっき厚さが１．０ｆ
ｍを超えると応力が大きくなり、０，２μ以上であると
熱処理工程で形成されるＮｉとＳｔの合金が薄くなり、
Ｓｉ素体とＮｉ層との密着強度が低下する。さらに、第
−Ｎｉ層のみではＮｉの酸化がすすみ、はんだ付けが困
難であるため、第二Ｎｉ層を表面側に設ける。この第二
Ｎｉ層では、耐食性、はんだのぬれ性および温度変化に
よる耐久性が重要である。めっきの種類とこれらめっき
層の性質の優劣を第１表に示す０表中の番号は、番号の
若い方が優れていることを示す。The stress applied from the Ni plating layer deposited on the Si element body is based on the difference in thermal expansion coefficient between the plating layer and Si. The size of the Ni plating layer increases in the order of type Ni plating layer and low boron type Ni plating layer. The stress on the silicon element body is largely controlled by the coefficient of thermal expansion of the layer in contact with the element body, so a medium phosphorous type nickel plating is applied to the -Ni layer on the side of the Si element body. This reduces stress within the Si element body and reduces strain within the Si element body. However, the plating thickness is 1.0f.
If it exceeds m, the stress increases, and if it exceeds 0.2μ, the Ni and St alloy formed in the heat treatment process becomes thin,
The adhesion strength between the Si element body and the Ni layer decreases. Further, if only the -Ni layer is used, oxidation of Ni progresses and soldering is difficult, so a second Ni layer is provided on the surface side. Corrosion resistance, solder wettability, and durability against temperature changes are important for this second Ni layer. Table 1 shows the types of plating and the superiority and inferiority of the properties of these plating layers.The numbers in Table 0 indicate that the smaller the number, the better.
第１表 第１表より分かるように、低燐タイプは耐食性。Table 1 As you can see from Table 1, the low phosphorus type is corrosion resistant.
はんだぬれ性、耐久性の点で中燐、低ボロンタイプより
優れている。しかし、第二Ｎｉ層の厚さが０．５μ以下
になると、中燐タイプの第−Ｎｉ層の燐の影響を受けて
以上の特性が劣化してくる。また、厚さが１．５ｎ以上
であると、Ｓｉ素体に与える応力が大きくなり、Ｓｉ素
体内部に歪みが生してくる。Superior to medium phosphorous and low boron types in terms of solderability and durability. However, when the thickness of the second Ni layer becomes 0.5 μm or less, the above-mentioned characteristics deteriorate due to the influence of phosphorus in the medium-phosphorus type -Ni layer. Moreover, if the thickness is 1.5 nm or more, stress applied to the Si element body becomes large, causing distortion inside the Si element body.
第１図（ａ）〜（イ）は本発明の実施例の半導体素子製
造工程の一部を示す、既に不純物拡散工程により内部６
二ＰＮ接合に形成されたＳｉウェーハ１に燐含有量６〜
９％の中燐タイプのＮｉ無電解めっきを施して厚さ０．
２〜１．Ｏμｍの範囲内で第−Ｎｉ層２を形成し、次い
で燐含有量２〜５％の低燐タイプのＮｉ無電解めっきを
施し、厚さ０．５〜１．５ｓの範囲内で第二Ｎ３層３を
形成する０次に、はんだ板あるいはクリームはんだを用
いてはんだ層４により第二Ｎ３層３とリード線５の頭部
５１とのはんだ付けを行う。FIGS. 1(a) to 1(a) show a part of the manufacturing process of a semiconductor device according to an embodiment of the present invention.
Si wafer 1 formed with two PN junctions has a phosphorus content of 6~
9% medium phosphorous type Ni electroless plating is applied to a thickness of 0.
2-1. A second Ni layer 2 is formed within the range of 0.0 μm, then electroless Ni plating with a low phosphorus type with a phosphorus content of 2 to 5% is applied, and a second Ni layer 2 is formed to a thickness of 0.5 to 1.5 s. Forming the layer 3 Next, the second N3 layer 3 and the head 51 of the lead wire 5 are soldered using the solder layer 4 using a solder plate or cream solder.
リード線５は銀めっき銅線で、ヘッダ加工により頭部５
１を形成したものである。実際の工程ではリード線ろう
何部にＳｉウェーハを切断して小さい寸法のＳｉチップ
にしておく、そして、図示しないがＳｉチップのリード
線５をろう付した側と反対側の面にも第一、第二Ｎｉ層
を設けておき、その面を容器底板に固着し、Ｓｉチップ
を気密封止して半導体素子を完成する。The lead wire 5 is a silver-plated copper wire, and the head 5 is formed by header processing.
1 was formed. In the actual process, the Si wafer is cut into small-sized Si chips at the lead wire brazing part, and a first layer is also placed on the side opposite to the side where the lead wires 5 are brazed, although not shown. , a second Ni layer is provided, its surface is fixed to the bottom plate of the container, and the Si chip is hermetically sealed to complete the semiconductor device.
このようにして製造された半導体素子のＳｉ素体には、
歪み、耐食性、耐久性およびリード線との接続部につい
て問題が発生しなかった。In the Si element body of the semiconductor device manufactured in this way,
There were no problems with distortion, corrosion resistance, durability, or connections with lead wires.
本発明によれば、シリコン素体表面の接続導体がはんだ
付けされる電極を、中燐タイプＮｉのめっきによる第−
Ｎｉ層と低燐タイプＮｉのめっきによる第二Ｎｉ層との
厚さを適正にした積層により形成することにより、第−
Ｎｉ層よりＳｉ素体に加わる応力を小さくして素体内部
の歪みの発生を抑えると共に、第二Ｎｉ層により電極表
面の耐食性、耐久性。According to the present invention, the electrode to which the connection conductor on the surface of the silicon body is soldered is plated with medium phosphorus type Ni.
By forming a Ni layer and a second Ni layer formed by low phosphorus type Ni plating with appropriate thickness,
The stress applied to the Si element body is lower than that of the Ni layer, suppressing the occurrence of distortion inside the element body, and the second Ni layer improves corrosion resistance and durability of the electrode surface.
はんだ付性を確保して信頼性の高い半導体素子を得るこ
とができた。It was possible to obtain a highly reliable semiconductor element with good solderability.
第１図は本発明の一実施例の半導体素子の製造工程の一
部の流れを示す断面図である。
１：Ｓｉウェーハ、２：第−Ｎｉ層、３：第二Ｎｉ層、
４：はんだ、５：リード線。
第１FIG. 1 is a sectional view showing a part of the manufacturing process of a semiconductor device according to an embodiment of the present invention. 1: Si wafer, 2: -th Ni layer, 3: second Ni layer,
4: Solder, 5: Lead wire. 1st
Claims (1)
はんだ付けされるものにおいて、電極が素子側から燐含
有量６〜９％の中燐タイプ・ニッケルめっきにより形成
された厚さ０．２〜１．０μｍの第一ニッケル層と燐含
有量２〜５％の低燐タイプ・ニッケルめっきにより形成
された厚さ０．５〜１．５μｍの第二ニッケル層を積層
してなることを特徴とする半導体素子。1) In a device in which a connecting conductor is soldered to an electrode provided on the surface of a silicon element, the electrode is formed from the element side by medium phosphorous type nickel plating with a phosphorus content of 6 to 9%. It is made by laminating a first nickel layer of 2 to 1.0 μm and a second nickel layer of 0.5 to 1.5 μm thick formed by low phosphorus type nickel plating with a phosphorus content of 2 to 5%. Characteristic semiconductor elements.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP3447890A JPH03238865A (en) | 1990-02-15 | 1990-02-15 | Semiconductor element |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP3447890A JPH03238865A (en) | 1990-02-15 | 1990-02-15 | Semiconductor element |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH03238865A true JPH03238865A (en) | 1991-10-24 |
Family
ID=12415360
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP3447890A Pending JPH03238865A (en) | 1990-02-15 | 1990-02-15 | Semiconductor element |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH03238865A (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2008190866A (en) * | 2007-01-31 | 2008-08-21 | Nippon Liniax Kk | Pressure sensor |
| JP2010174322A (en) * | 2009-01-29 | 2010-08-12 | Alps Electric Co Ltd | Elastic contact and method of manufacturing the same, and contact substrate and method of manufacturing the same |
| CN111354626A (en) * | 2018-12-21 | 2020-06-30 | 瑞萨电子株式会社 | Semiconductor device and method for manufacturing the same |
-
1990
- 1990-02-15 JP JP3447890A patent/JPH03238865A/en active Pending
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2008190866A (en) * | 2007-01-31 | 2008-08-21 | Nippon Liniax Kk | Pressure sensor |
| JP2010174322A (en) * | 2009-01-29 | 2010-08-12 | Alps Electric Co Ltd | Elastic contact and method of manufacturing the same, and contact substrate and method of manufacturing the same |
| CN111354626A (en) * | 2018-12-21 | 2020-06-30 | 瑞萨电子株式会社 | Semiconductor device and method for manufacturing the same |
| CN111354626B (en) * | 2018-12-21 | 2023-09-01 | 瑞萨电子株式会社 | Semiconductor device and method for manufacturing the same |
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