JP2003347487A - Semiconductor device - Google Patents

Semiconductor device

Info

Publication number
JP2003347487A
JP2003347487A JP2002155726A JP2002155726A JP2003347487A JP 2003347487 A JP2003347487 A JP 2003347487A JP 2002155726 A JP2002155726 A JP 2002155726A JP 2002155726 A JP2002155726 A JP 2002155726A JP 2003347487 A JP2003347487 A JP 2003347487A
Authority
JP
Japan
Prior art keywords
semiconductor
layer
semiconductor device
gold
radiator
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
JP2002155726A
Other languages
Japanese (ja)
Inventor
Shiyougo Kondo
松悟 近藤
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Renesas Semiconductor Manufacturing Co Ltd
Kansai Nippon Electric Co Ltd
Original Assignee
Renesas Semiconductor Manufacturing Co Ltd
Kansai Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Renesas Semiconductor Manufacturing Co Ltd, Kansai Nippon Electric Co Ltd filed Critical Renesas Semiconductor Manufacturing Co Ltd
Priority to JP2002155726A priority Critical patent/JP2003347487A/en
Publication of JP2003347487A publication Critical patent/JP2003347487A/en
Withdrawn legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/31Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L24/32Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805Shape
    • H01L2224/4809Loop shape
    • H01L2224/48091Arched
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481Disposition
    • H01L2224/48151Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491Disposition
    • H01L2224/4912Layout
    • H01L2224/49175Parallel arrangements
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732Location after the connecting process
    • H01L2224/73251Location after the connecting process on different surfaces
    • H01L2224/73265Layer and wire connectors
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/161Cap
    • H01L2924/1615Shape
    • H01L2924/16195Flat cap [not enclosing an internal cavity]

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)

Abstract

<P>PROBLEM TO BE SOLVED: To solve the problem that a semiconductor pellet is exfoliated from a back electrode when operation is repeated in a semiconductor device wherein the semiconductor pellet is mounted on a hollow resin package by using a gold tin alloy. <P>SOLUTION: A semiconductor pellet 11 having a back electrode 11b wherein a titanium layer 12, a nickel layer 13 and a layer 14 composed of gold or silver are formed in order from a semiconductor substrate 11a side is mounted on a radiator 1 by using the gold tin alloy 6. <P>COPYRIGHT: (C)2004,JPO

Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【0001】[0001]

【発明の属する技術分野】本発明は半導体装置に関し、
特に低融点合金を介して半導体ペレットを放熱体に固定
した半導体装置に関する。
The present invention relates to a semiconductor device,
In particular, the present invention relates to a semiconductor device in which a semiconductor pellet is fixed to a radiator via a low melting point alloy.

【0002】[0002]

【従来の技術】電力用半導体装置は半導体ペレットが発
生する熱を効率良く外部に放出するため、一般的に半導
体ペレットを放熱体に固定し、さらに必要に応じて放熱
体を外部の放熱器や冷却装置に接続している。この種半
導体装置の一例を図2及び図3に示す。図において、1
は導電性、熱伝導性が良好な金属や合金、複合材料など
の中から高温動作による熱膨張を考慮して選択された材
料からなる板状の放熱体で、両側に取付用貫通孔1a、
1bが穿設され中央部にはニッケル1dと金1eとを積
層しためっき層1cが形成されている。2a、2bは放
熱体1の中間位置両側に直交配置された板状のリード、
3は筒状の樹脂枠部で、放熱体1とリード2a、2bの
交差位置で放熱体1とリード2a、2bとを気密封着し
て一体化し樹脂パッケージ4を構成している。5は半導
体ペレットで、内部に半導体素子(図示せず)が形成さ
れた半導体基板5aの裏面全面に裏面電極5bが形成さ
れ、表面には内部の半導体素子の要部と電気的に接続さ
れた電極5c、5dが形成されている。6は半導体ペレ
ット5を樹脂パッケージ4の放熱体1上に接着する低融
点合金を示す。7a、7bは半導体ペレット5上の電極
5c、5dとリード2a、2bとを電気的に接続するワ
イヤを示す。電気抵抗やインダクタンスを低減させるた
め図示例では多数本並列接続している。8は樹脂パッケ
ージ4の枠部3開口端を気密封止する蓋部を示す。放熱
体1やリード2を支持した中空の樹脂パッケージ4は半
導体ペレット5などの主要部を外力や腐食性ガスから保
護するが、半導体ペレット5やワイヤ7を高誘電率の樹
脂から一定距離、離隔させることができるためGHz帯
で動作する高周波用半導体装置用パッケージとして用い
られる。
2. Description of the Related Art In a power semiconductor device, in order to efficiently release heat generated by a semiconductor pellet to the outside, the semiconductor pellet is generally fixed to a radiator, and if necessary, the radiator is connected to an external radiator or the like. Connected to cooling device. An example of this type of semiconductor device is shown in FIGS. In the figure, 1
Is a plate-shaped radiator made of a material selected from metals, alloys, composite materials, and the like having good conductivity and thermal conductivity in consideration of thermal expansion due to high-temperature operation, and mounting through holes 1a on both sides;
1b is formed, and a plating layer 1c formed by laminating nickel 1d and gold 1e is formed at the center. 2a and 2b are plate-shaped leads orthogonally arranged on both sides of the intermediate position of the heat radiator 1,
Numeral 3 is a cylindrical resin frame portion, and the heat radiator 1 and the leads 2a, 2b are hermetically sealed and integrated at a crossing position of the heat radiator 1 and the leads 2a, 2b to form a resin package 4. Reference numeral 5 denotes a semiconductor pellet. A back electrode 5b is formed on the entire back surface of a semiconductor substrate 5a having a semiconductor element (not shown) formed therein, and the front surface is electrically connected to a main part of the internal semiconductor element. Electrodes 5c and 5d are formed. Reference numeral 6 denotes a low melting point alloy for bonding the semiconductor pellet 5 onto the heat radiator 1 of the resin package 4. Reference numerals 7a and 7b denote wires for electrically connecting the electrodes 5c and 5d on the semiconductor pellet 5 and the leads 2a and 2b. In order to reduce electric resistance and inductance, many of them are connected in parallel in the illustrated example. Reference numeral 8 denotes a lid for hermetically sealing the open end of the frame 3 of the resin package 4. The hollow resin package 4 supporting the radiator 1 and the leads 2 protects the main part such as the semiconductor pellet 5 from external force and corrosive gas, but separates the semiconductor pellet 5 and the wire 7 from the resin having a high dielectric constant by a certain distance. Therefore, it is used as a high-frequency semiconductor device package that operates in the GHz band.

【0003】この種半導体装置9の製造方法を以下に説
明する。先ず、樹脂パッケージ4を高温雰囲気中に供給
し放熱体1を加熱する。次に加熱された放熱体1上に低
融点合金6を供給し溶融させる。そして溶融合金6上に
半導体ペレット5を供給し、放熱体1を冷却して半導体
ペレット5を固定する。次に樹脂パッケージ4をワイヤ
ボンディング工程に送り、半導体ペレット5上の電極5
c、5dとリード2a、2bとをワイヤ7a、7bで電
気的に接続する。このようにして樹脂パッケージ4内の
作業が終了すると、枠部3の開口端を蓋部8で封着し電
気的特性検査などの工程を経て完成した半導体装置9は
出荷される。
[0003] A method of manufacturing this type of semiconductor device 9 will be described below. First, the resin package 4 is supplied into a high-temperature atmosphere and the radiator 1 is heated. Next, the low melting point alloy 6 is supplied onto the heated radiator 1 and melted. Then, the semiconductor pellets 5 are supplied onto the molten alloy 6, and the radiator 1 is cooled to fix the semiconductor pellets 5. Next, the resin package 4 is sent to a wire bonding step, and the electrodes 5 on the semiconductor pellet 5 are formed.
c, 5d and the leads 2a, 2b are electrically connected by wires 7a, 7b. When the work in the resin package 4 is completed in this way, the semiconductor device 9 completed through processes such as electrical characteristic inspection after sealing the opening end of the frame 3 with the lid 8 is shipped.

【0004】この半導体装置9は動作、停止の繰返しに
より半導体ペレット5は温度上昇、降下し熱膨張、熱収
縮を繰返すが、半導体ペレット5、低融点合金6、放熱
体1のそれぞれの間の熱膨張係数に大きな開きがあると
その界面に応力が集中し、応力集中部が比較的短時間で
疲労して微細なクラックを生じる。微細クラックは半導
体ペレット5と放熱体1の間の熱伝導性を低下させるた
め半導体ペレット5で発生した熱の外部への伝達が阻止
され半導体ペレット5の温度上昇が著しくなり、この結
果、クラックが急速に成長し比較的短時間で半導体ペレ
ット5を破壊する。そのため、放熱体1、低融点合金
6、半導体ペレット5のそれぞれの間の熱膨張係数が大
きく異ならないように、放熱体1、低融点合金6の材
料、形状、寸法を選定している。
When the semiconductor device 9 is repeatedly operated and stopped, the temperature of the semiconductor pellet 5 rises and falls, and thermal expansion and contraction are repeated. However, the heat generated between the semiconductor pellet 5, the low melting point alloy 6 and the radiator 1 is reduced. If there is a large difference in the expansion coefficient, stress concentrates on the interface, and the stress concentration portion fatigues in a relatively short time, causing a fine crack. The fine cracks reduce the thermal conductivity between the semiconductor pellets 5 and the heat radiator 1, so that the heat generated in the semiconductor pellets 5 is prevented from being transferred to the outside, and the temperature of the semiconductor pellets 5 rises remarkably. It grows rapidly and destroys the semiconductor pellet 5 in a relatively short time. Therefore, the materials, shapes and dimensions of the heat radiator 1 and the low melting point alloy 6 are selected so that the thermal expansion coefficients of the heat radiator 1, the low melting point alloy 6 and the semiconductor pellet 5 do not greatly differ from each other.

【0005】一方、図2に示す半導体装置9は放熱体1
を加熱し半導体ペレット5を固定する際に熱衝撃を受け
ると樹脂パッケージ4の気密封着部に微細なクラックを
生じ、この微細クラックが成長して樹脂パッケージ4の
内外を連通すると中空部に水分が浸入しさらに蓄積され
る。この水分は温度が上昇すると気化し蒸気圧が上昇し
て半導体ペレット5上の電極5c、5dやワイヤ7a、
7bとの接続界面、ワイヤ7a、7bとリード2a、2
bの接続界面に浸入し局所的な電気分解反応を生じ接続
界面を腐食させる。この接続界面の腐食の進行にともな
って電気的接続面積が縮小し電気抵抗が上昇して電子回
路装置の特性を変化させ、最終的には接続界面の電気的
接続を損ない半導体装置を不良にする。
On the other hand, the semiconductor device 9 shown in FIG.
When the semiconductor package 5 is heated and subjected to a thermal shock when it is fixed, fine cracks are generated in the hermetically sealed portion of the resin package 4. When these fine cracks grow and communicate with the inside and outside of the resin package 4, moisture is formed in the hollow portion. Infiltrate and accumulate further. This water vaporizes as the temperature rises and the vapor pressure rises, causing the electrodes 5c, 5d and wires 7a,
7b, wires 7a, 7b and leads 2a, 2
b infiltrates the connection interface, causing a local electrolysis reaction and corroding the connection interface. As the corrosion of the connection interface progresses, the electrical connection area decreases, the electrical resistance increases, and the characteristics of the electronic circuit device are changed. .

【0006】また樹脂枠部3として用いられる樹脂は低
融点合金6の溶融温度に耐える耐熱性が要求されるが、
樹脂はその耐熱温度以下でも加熱時間が長引くと徐々に
炭化し電気的特性が劣化するため、耐熱温度が例えば3
40℃の樹脂の場合、低融点合金6として錫含有量20
重量%、融点290℃の金錫合金を用いるなどして、製
造過程で樹脂パッケージ4が熱衝撃を受けないように可
及的に短時間で接着作業を完了するように配慮してい
る。
[0006] The resin used as the resin frame 3 is required to have heat resistance to withstand the melting temperature of the low melting point alloy 6.
If the heating time is prolonged, the resin will gradually carbonize even if it is below its heat-resistant temperature, and its electrical characteristics will deteriorate.
In the case of resin at 40 ° C., tin content 20
By using a gold-tin alloy having a melting point of 290 ° C. in weight%, consideration is given to completing the bonding operation in as short a time as possible so that the resin package 4 is not subjected to thermal shock during the manufacturing process.

【0007】[0007]

【発明が解決しようとする課題】このように中空樹脂パ
ッケージを用いた半導体装置は、温度、湿度制御された
環境で樹脂枠部3と放熱体1、リード2の間にクラック
を生じないよう配慮されて製造されている。また半導体
ペレット5の裏面電極5bは図3に示すように、チタン
やニッケルなどからなるバリア性を有する層5eと金錫
合金に対して濡れ性が良好な金層5fとを積層した多層
構造としている。
In a semiconductor device using such a hollow resin package, care must be taken not to cause cracks between the resin frame 3 and the radiator 1 and the lead 2 in an environment where temperature and humidity are controlled. Has been manufactured. As shown in FIG. 3, the back electrode 5b of the semiconductor pellet 5 has a multilayer structure in which a barrier layer 5e made of titanium, nickel or the like and a gold layer 5f having good wettability with respect to a gold-tin alloy are laminated. I have.

【0008】しかしながら密閉された中空部内の半導体
ペレット5が加熱、冷却を繰返すと半導体ペレット5が
裏面電極5bから剥離するという問題があった。このよ
うに半導体ペレット5が裏面電極5bから剥離する原因
として、半導体ペレット5は繰返し加熱、冷却される
と、金錫合金6中の錫がバリア層5eを浸透して半導体
基板5a中に拡散してシリコンと結合し、この水溶性の
錫に水蒸気が接触すると錫は裏面電極5bから外部に溶
出し半導体ペレット5の裏面全面に多孔性領域を形成
し、半導体ペレット5の接着力を低下させるためと考え
られる。この錫が抜けた多孔性領域は熱伝導性が低く断
熱性が高いため半導体ペレット5から放熱体1への熱伝
達を阻害する。そのため半導体ペレット5は過熱し短時
間で不良となる。
However, when the semiconductor pellets 5 in the hermetically sealed hollow portion are repeatedly heated and cooled, there is a problem that the semiconductor pellets 5 are separated from the back electrode 5b. As a cause of the separation of the semiconductor pellet 5 from the back surface electrode 5b, when the semiconductor pellet 5 is repeatedly heated and cooled, tin in the gold-tin alloy 6 permeates the barrier layer 5e and diffuses into the semiconductor substrate 5a. When water vapor contacts the water-soluble tin, the tin elutes from the back electrode 5b to the outside to form a porous region on the entire back surface of the semiconductor pellet 5 and reduce the adhesive force of the semiconductor pellet 5. it is conceivable that. Since the porous region from which tin has been removed has low thermal conductivity and high heat insulation, heat transfer from the semiconductor pellet 5 to the radiator 1 is impeded. Therefore, the semiconductor pellet 5 is overheated and becomes defective in a short time.

【0009】このような問題を解決するには、錫を含ま
ない低融点合金6を用いれば良いが、融点が高くなるた
め樹脂パッケージ用合金としては不適当であった。また
金錫合金中の錫の拡散を防止するにはバリア層5eを厚
くすればよいが、外部リード2b(ドレイン電極)と放
熱体1(ソース電極)の間のPN接合に順方向に数Aの
大電流を流したときの電極間電圧Vfは、裏面電極5b
の電気抵抗によって変化し高くなるだけでなく電圧Vf
のばらつきが大きくなるため、バリア層5eを厚くする
にも限界があった。
In order to solve such a problem, a low melting point alloy 6 containing no tin may be used. However, since the melting point is high, it is not suitable as an alloy for a resin package. To prevent the diffusion of tin in the gold-tin alloy, the thickness of the barrier layer 5e may be increased, but a few A in the forward direction is formed at the PN junction between the external lead 2b (drain electrode) and the radiator 1 (source electrode). The voltage Vf between the electrodes when a large current flows through the back electrode 5b
Changes not only due to the electrical resistance of the
Therefore, there is a limit in increasing the thickness of the barrier layer 5e.

【0010】[0010]

【課題を解決するための手段】本発明は上記課題の解決
を目的として提案されたもので、半導体ペレットの裏面
電極を低融点合金を介して放熱体に固定した半導体装置
において、上記半導体ペレットの裏面電極は、半導体基
板側から、チタン層、ニッケル層、金又は銀の層を順次
積層してなり、低融点合金として金−錫合金を用いたこ
とを特徴とする半導体装置を提供する。
SUMMARY OF THE INVENTION The present invention has been proposed for the purpose of solving the above problems. In a semiconductor device in which a back electrode of a semiconductor pellet is fixed to a radiator through a low melting point alloy, the present invention provides The back electrode is provided by sequentially laminating a titanium layer, a nickel layer, and a gold or silver layer from the semiconductor substrate side, and provides a semiconductor device using a gold-tin alloy as a low melting point alloy.

【0011】[0011]

【発明の実施の形態】本発明による半導体装置は、裏面
電極として半導体基板側から、チタン層、ニッケル層、
金又は銀の層を順次積層した裏面電極を有する半導体ペ
レットを、金−錫合金を用いて放熱体に接続したから、
低融点合金中の錫の半導体基板内への浸入が阻止され、
長期間にわたって電気的に安定した半導体装置を実現す
ることができる。この半導体装置の裏面電極は、チタン
層の厚みを0.02〜0.5μmに、ニッケル層の厚み
を0.4〜2μmに、金又は銀の層の厚みを0.01〜
2μmに、それぞれ設定することにより特性が安定した
半導体装置を実現することができる。また放熱体の低融
点合金が被着される面に、ニッケル層、金層を順次積層
すことができる。本発明は、底部に放熱体の一部を露呈
させた箱状樹脂パッケージ内に半導体ペレットを収容し
た構造の半導体装置に好適である。
DESCRIPTION OF THE PREFERRED EMBODIMENTS In a semiconductor device according to the present invention, a titanium layer, a nickel layer,
Since the semiconductor pellet having a back electrode in which gold or silver layers were sequentially laminated was connected to a radiator using a gold-tin alloy,
The penetration of tin in the low melting point alloy into the semiconductor substrate is prevented,
A semiconductor device which is electrically stable for a long time can be realized. The back electrode of this semiconductor device has a titanium layer with a thickness of 0.02 to 0.5 μm, a nickel layer with a thickness of 0.4 to 2 μm, and a gold or silver layer with a thickness of 0.01 to 2 μm.
By setting each to 2 μm, a semiconductor device having stable characteristics can be realized. Further, a nickel layer and a gold layer can be sequentially laminated on the surface of the radiator on which the low melting point alloy is to be adhered. The present invention is suitable for a semiconductor device having a structure in which semiconductor pellets are accommodated in a box-shaped resin package in which a part of a heat radiator is exposed at the bottom.

【0012】[0012]

【実施例】以下に本発明の実施例を図1から説明する。
図において、図2と同一部分には同一符号を付し重複す
る説明を省略する。この半導体装置10は、図2半導体
装置9と同様に、放熱体1とリード2とを気密に貫通し
た樹脂パッケージ4に半導体ペレット11を収容して放
熱体1上に低融点合金6を介して半導体ペレット11を
マウントし、半導体ペレット11上の電極11c、11
dとリード2a、2bとを電気的に接続して、枠部3の
開口端を蓋部8で封止したもので、半導体基板11a側
から、チタン層12、ニッケル層13、金又は銀の層1
4を順次積層した裏面電極11bを有する半導体ペレッ
ト11を金錫合金6を用いて放熱体1に固定した点で図
2半導体装置9と相異する。この裏面電極11bの各層
の厚みは、チタン層12は0.02〜0.5μm、ニッ
ケル層13は0.4〜2μm、金又は銀の層14は0.
01〜2μmにそれぞれ設定されており、ニッケル層の
厚みを0.4〜2μmに設定したことを特徴とする。な
お、放熱体1には図2半導体装置9と同様にニッケル
(厚み1μm)1d、金(厚み1μm)1eを順次積層
している。
FIG. 1 shows an embodiment of the present invention.
In the figure, the same parts as those in FIG. 2 are denoted by the same reference numerals, and redundant description will be omitted. In the semiconductor device 10, similarly to the semiconductor device 9 of FIG. The semiconductor pellet 11 is mounted, and the electrodes 11 c and 11 on the semiconductor pellet 11 are mounted.
d and the leads 2a and 2b are electrically connected to each other, and the opening end of the frame 3 is sealed with the lid 8. The titanium layer 12, the nickel layer 13, the gold or silver Tier 1
The semiconductor device 9 differs from the semiconductor device 9 in FIG. 2 in that a semiconductor pellet 11 having a back surface electrode 11 b in which layers 4 are sequentially stacked is fixed to the heat radiator 1 using a gold-tin alloy 6. The thickness of each layer of the back surface electrode 11b is 0.02 to 0.5 μm for the titanium layer 12, 0.4 to 2 μm for the nickel layer 13, and 0.1 μm for the gold or silver layer 14.
The thickness of the nickel layer is set to 0.4 to 2 μm. As in the semiconductor device 9 shown in FIG.

【0013】従来技術による半導体装置を比較例1、2
として表1、表2に、本発明による半導体装置を実施例
1、2として表3、表4にそれぞれ示す。
Comparative Examples 1 and 2
Tables 1 and 2 show the semiconductor device according to the present invention as Examples 1 and 2 in Tables 3 and 4, respectively.

【表1】 [Table 1]

【表2】 [Table 2]

【表3】 [Table 3]

【表4】 [Table 4]

【0014】比較例1は表1に示すように、チタン層
(厚み0.02μm)と金層(厚み0.2μm)を積層
したもの(比較例1−No.1)と、チタン層(厚み
0.02μm)と金層(厚み2μm)を積層し、シンタ
ー条件を異ならせたもの(比較例1−No.2〜3)
で、いずれも初期Vfは良好であるが、比較例1−3で
は低融点合金との馴染み性が劣り、加圧水蒸気雰囲気で
の耐湿性試験(PCT)では比較例1−1、1−4がマ
ウント後加熱では比較例1−2、1−4がそれぞれ劣る
ため、総合評価はいずれも劣り安定生産には不適であ
る。
As shown in Table 1, in Comparative Example 1, a laminate of a titanium layer (thickness 0.02 μm) and a gold layer (thickness 0.2 μm) (Comparative Example 1-No. 1) 0.02 μm) and a gold layer (2 μm in thickness) with different sintering conditions (Comparative Example 1-Nos. 2-3)
In each case, the initial Vf was good, but in Comparative Example 1-3, the compatibility with the low melting point alloy was inferior, and in Comparative Example 1-1 and 1-4 in the moisture resistance test (PCT) in a pressurized steam atmosphere. In the case of heating after mounting, Comparative Examples 1-2 and 1-4 are inferior, respectively, so that the overall evaluation is inferior and is not suitable for stable production.

【0015】比較例2は表2に示すように、チタン層
(厚み0.02μm)と金層(厚み2μm)の間にニッ
ケル層を配置したもので、ニッケル層は厚みを0.02
μm、0.05μm、0.15μmとし比較例2−1〜
2−3の3種類に区分している。いずれもシンター条件
はマウント後、250℃、20分加熱とした。いずれの
比較例でも馴染み性、PCTは良好であったが、マウン
トした後加熱し実施したPCTではいずれの比較例も不
合格で、さらに比較例2−3では初期Vfが不合格とな
った。
In Comparative Example 2, as shown in Table 2, a nickel layer was disposed between a titanium layer (thickness 0.02 μm) and a gold layer (thickness 2 μm).
Comparative Examples 2-1 to μm, 0.05 μm, and 0.15 μm
It is classified into three types of 2-3. In each case, the sintering conditions were 250 ° C. for 20 minutes after mounting. In all the comparative examples, the conformability and PCT were good, but in the case of PCT which was mounted and then heated and performed, all the comparative examples failed, and further, in the comparative example 2-3, the initial Vf failed.

【0016】実施例1は比較例2と同様にチタン層(厚
み0.02μm)、金層(厚み2μm)の間にニッケル
層をはいちしたもので、ニッケル層の厚みは0.4μ
m、0.5μmの2通りとしさらにシンター条件をマウ
ント後250℃、20分加熱とマウント時320℃、2
0秒加熱の2通りに区分し、4つの組み合わせについて
比較した。実施例3−1、3−2に示すマウント後加熱
の場合、初期Vfがやや劣るもののマウント時の加熱時
間を延長することにより合格となり、実施例3全体では
良好な結果が得られた。
In Example 1, as in Comparative Example 2, a nickel layer was interposed between a titanium layer (0.02 μm in thickness) and a gold layer (2 μm in thickness), and the thickness of the nickel layer was 0.4 μm.
m and 0.5 μm, and the sintering conditions were 250 ° C. for 20 minutes after mounting, and 320 ° C.
It divided into two ways of 0 second heating, and compared about four combinations. In the case of the post-mounting heating shown in Examples 3-1 and 3-2, the initial Vf was slightly inferior, but the heating time at the time of mounting was extended, but the result was acceptable, and good results were obtained in Example 3 as a whole.

【0017】実施例2は表4に示すようにチタン層(厚
み0.02μm)上に、ニッケル層(厚み0.5μm)
を積層し、外層に銀層(厚み1μm)を形成したもの
で、シンター条件はウエハを400℃1時間加熱又はマ
ウント時320℃、20秒加熱した。この場合、馴染み
性、初期Vf、PCT、マウント後加熱して実施したP
CTのいずれの試験項目に合格し、安定した半導体装置
を実現できることがわかった。
In Example 2, as shown in Table 4, a nickel layer (0.5 μm in thickness) was formed on a titanium layer (0.02 μm in thickness).
And a silver layer (thickness: 1 μm) was formed as an outer layer. The sintering conditions were as follows: the wafer was heated at 400 ° C. for 1 hour or mounted at 320 ° C. for 20 seconds. In this case, familiarity, initial Vf, PCT, P
All the test items of CT were passed, and it was found that a stable semiconductor device could be realized.

【0018】銀は高湿度雰囲気ではマイグレーションを
生じる虞があるが、放熱体1を接地するなど低電位に保
つことにより実用上支障はない。なお、チタン層と金層
との間にニッケル層を配置すると初期Vfが大きくな
る。これを改善するにはウエハシンターを実施すれば良
いが、最外層の金層がえくぼ状に消失し低融点合金との
馴染み性が劣化するため、ウエハシンターはできない
が、最外層を銀層とすることによりウエハシンターが可
能となり半導体ペレット毎のばらつきを抑え容易に生産
することができる。またニッケル層の厚みは0.4μm
以下ではバリア性が低下し、2μmを超えると安定した
バリア性は得られるもののコストが上昇するため0.4
〜2μmの範囲に設定される。
Although silver may cause migration in a high-humidity atmosphere, there is no practical problem by keeping the radiator 1 at a low potential such as by grounding. When a nickel layer is arranged between the titanium layer and the gold layer, the initial Vf increases. In order to improve this, wafer sintering may be performed.However, since the outermost gold layer disappears in a dimple shape and the compatibility with the low melting point alloy is deteriorated, wafer sintering cannot be performed, but the outermost layer is replaced with a silver layer. By doing so, wafer sintering becomes possible, and variations can be suppressed for each semiconductor pellet, and production can be easily performed. The thickness of the nickel layer is 0.4 μm
In the following, the barrier property is lowered, and if it exceeds 2 μm, a stable barrier property is obtained, but the cost is increased.
22 μm.

【0019】実施例1、2に示す裏面電極11bを有す
る半導体ペレット11を樹脂パッケージ4の中空部に配
置された放熱体1上に金錫合金6を介してマウントした
半導体装置は、密閉された中空部内が温度上昇し水蒸気
の圧力が上昇しても、金錫合金中の錫の半導体基板11
aへの浸入が0.4μm以上のニッケル層によって阻止
されるため水溶性の錫を生成せず、高圧の水蒸気と接し
ても溶出することがなく、裏面電極11bの接着強度を
保持でき、半導体ヘ゜レットの剥離を防止できる。そのため
半導体ペレットが発生した熱を効率良く放熱体1に伝達
でき、半導体ペレットの温度上昇を抑えることができる
から、安定して大電力動作させることかできる。
The semiconductor device in which the semiconductor pellet 11 having the back electrode 11b shown in Examples 1 and 2 is mounted on the heat radiator 1 disposed in the hollow portion of the resin package 4 via the gold-tin alloy 6 is sealed. Even if the temperature inside the hollow portion rises and the pressure of water vapor rises, the semiconductor substrate 11 of tin in the gold-tin alloy
a is prevented by the nickel layer having a thickness of 0.4 μm or more, does not generate water-soluble tin, does not elute even in contact with high-pressure steam, can maintain the adhesive strength of the back electrode 11b, Peeling of the pellet can be prevented. Therefore, the heat generated by the semiconductor pellets can be efficiently transmitted to the heat radiator 1 and the temperature rise of the semiconductor pellets can be suppressed, so that a high power operation can be stably performed.

【0020】[0020]

【発明の効果】以上のように本発明によれば、半導体ペ
レットを金錫合金を用いて放熱体にマウントした半導体
装置の、半導体ペレットが放熱体から剥離するという課
題を解決し、大電力で安定動作させることのできる半導
体装置を実現できる。
As described above, according to the present invention, the problem that the semiconductor pellet is separated from the heat radiator in the semiconductor device in which the semiconductor pellet is mounted on the heat radiator by using a gold-tin alloy is solved, and high power is used. A semiconductor device that can operate stably can be realized.

【図面の簡単な説明】[Brief description of the drawings]

【図1】 本発明による半導体装置の要部側断面図FIG. 1 is a sectional side view of a main part of a semiconductor device according to the present invention;

【図2】 中空樹脂パッケージを用いた半導体装置の一
例を示し、(a)は一部破断平面図、(b)は正面図を
示す。
FIGS. 2A and 2B show an example of a semiconductor device using a hollow resin package, wherein FIG. 2A is a partially cutaway plan view, and FIG.

【図3】 (a)は図2半導体装置の側断面図、(b)
は要部拡大側断面図を示す。
3A is a side sectional view of the semiconductor device in FIG. 2, and FIG.
Shows an enlarged side sectional view of a main part.

【符号の説明】[Explanation of symbols]

1 放熱体 2a、2b リード 3 枠部 4 樹脂パッケージ 10 半導体装置 11 半導体ペレット 11a 半導体基板 11b 裏面電極 11c、11d 電極 12 チタン層 13 ニッケル層 14 金又は銀の層 1 heat sink 2a, 2b lead 3 Frame 4 Resin package 10 Semiconductor device 11 Semiconductor pellet 11a Semiconductor substrate 11b Back electrode 11c, 11d electrode 12 Titanium layer 13 Nickel layer 14 Gold or silver layer

Claims (4)

【特許請求の範囲】[Claims] 【請求項1】 半導体ペレットの裏面電極を低融点合金
を介して放熱体に固定した半導体装置において、 上記半導体ペレットの裏面電極は、半導体基板側から、
チタン層、ニッケル層、金又は銀の層を順次積層してな
り、低融点合金として金−錫合金を用いたことを特徴と
する半導体装置。
1. A semiconductor device in which a back electrode of a semiconductor pellet is fixed to a heat radiator via a low melting point alloy, wherein the back electrode of the semiconductor pellet is formed from a semiconductor substrate side.
A semiconductor device comprising a titanium layer, a nickel layer, and a gold or silver layer sequentially laminated, and using a gold-tin alloy as a low melting point alloy.
【請求項2】裏面電極の、チタン層の厚みを0.02〜
0.5μmに、ニッケル層の厚みを0.4〜2μmに、
金又は銀の層の厚みを0.01〜2μmに、それぞれ設
定したことを特徴とする請求項1に記載の半導体装置。
2. The thickness of the titanium layer of the back electrode is 0.02 to 0.02.
0.5 μm, the thickness of the nickel layer to 0.4-2 μm,
2. The semiconductor device according to claim 1, wherein the thickness of the gold or silver layer is set to 0.01 to 2 [mu] m.
【請求項3】放熱体の低融点合金が被着される面に、ニ
ッケル層、金層を順次積層したことを特徴とする請求項
1に記載の半導体装置。
3. The semiconductor device according to claim 1, wherein a nickel layer and a gold layer are sequentially laminated on the surface of the radiator on which the low melting point alloy is to be adhered.
【請求項4】底部に放熱体の一部を露呈させた箱状樹脂
パッケージ内に半導体ペレットを収容したことを特徴と
する請求項1に記載の半導体装置。
4. The semiconductor device according to claim 1, wherein the semiconductor pellet is housed in a box-shaped resin package having a part of the heat radiator exposed at the bottom.
JP2002155726A 2002-05-29 2002-05-29 Semiconductor device Withdrawn JP2003347487A (en)

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JP2009194275A (en) * 2008-02-18 2009-08-27 Sumitomo Electric Ind Ltd Assembling structure for packaging, and resin sealed semiconductor device
US7723743B2 (en) 2006-04-03 2010-05-25 Toyoda Gosei Co., Ltd. Semiconductor light emitting element
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US10431529B2 (en) 2013-03-21 2019-10-01 Rohm Co., Ltd. Semiconductor device
US10825758B2 (en) 2013-03-21 2020-11-03 Rohm Co., Ltd. Semiconductor device
KR20190095407A (en) 2016-12-22 2019-08-14 다나카 기킨조쿠 고교 가부시키가이샤 The electrode structure of the back electrode of a semiconductor substrate, its manufacturing method, and the sputtering target provided in manufacture of this electrode structure
RU2718134C1 (en) * 2016-12-22 2020-03-30 Танака Кикинзоку Когио К.К. Electrode structure of rear electrode of semiconductor substrate, method of its obtaining and sputtered target for use in production of electrode structure
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